include/asm-i386/msr.h

   1 #ifndef __ASM_MSR_H
   2 #define __ASM_MSR_H
   3
   4 #ifdef CONFIG_PARAVIRT
   5 #include <asm/paravirt.h>
   6 #else
   7
   8 /*
   9  * Access to machine-specific registers (available on 586 and better only)
  10  * Note: the rd* operations modify the parameters directly (without using
  11  * pointer indirection), this allows gcc to optimize better
  12  */
  13
  14 #define rdmsr(msr,val1,val2) \
  15         __asm__ __volatile__("rdmsr" \
  16                           : "=a" (val1), "=d" (val2) \
  17                           : "c" (msr))
  18
  19 #define wrmsr(msr,val1,val2) \
  20         __asm__ __volatile__("wrmsr" \
  21                           : /* no outputs */ \
  22                           : "c" (msr), "a" (val1), "d" (val2))
  23
  24 #define rdmsrl(msr,val) do { \
  25         unsigned long l__,h__; \
  26         rdmsr (msr, l__, h__);  \
  27         val = l__;  \
  28         val |= ((u64)h__<<32);  \
  29 } while(0)
  30
  31 static inline void wrmsrl (unsigned long msr, unsigned long long val)
  32 {
  33         unsigned long lo, hi;
  34         lo = (unsigned long) val;
  35         hi = val >> 32;
  36         wrmsr (msr, lo, hi);
  37 }
  38
  39 /* wrmsr with exception handling */
  40 #define wrmsr_safe(msr,a,b) ({ int ret__;                                               \
  41         asm volatile("2: wrmsr ; xorl %0,%0\n"                                          \
  42                      "1:\n\t"                                                           \
  43                      ".section .fixup,\"ax\"\n\t"                                       \
  44                      "3:  movl %4,%0 ; jmp 1b\n\t"                                      \
  45                      ".previous\n\t"                                                    \
  46                      ".section __ex_table,\"a\"\n"                                      \
  47                      "   .align 4\n\t"                                                  \
  48                      "   .long  2b,3b\n\t"                                              \
  49                      ".previous"                                                        \
  50                      : "=a" (ret__)                                                     \
  51                      : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT));\
  52         ret__; })
  53
  54 /* rdmsr with exception handling */
  55 #define rdmsr_safe(msr,a,b) ({ int ret__;                                               \
  56         asm volatile("2: rdmsr ; xorl %0,%0\n"                                          \
  57                      "1:\n\t"                                                           \
  58                      ".section .fixup,\"ax\"\n\t"                                       \
  59                      "3:  movl %4,%0 ; jmp 1b\n\t"                                      \
  60                      ".previous\n\t"                                                    \
  61                      ".section __ex_table,\"a\"\n"                                      \
  62                      "   .align 4\n\t"                                                  \
  63                      "   .long  2b,3b\n\t"                                              \
  64                      ".previous"                                                        \
  65                      : "=r" (ret__), "=a" (*(a)), "=d" (*(b))                           \
  66                      : "c" (msr), "i" (-EFAULT));\
  67         ret__; })
  68
  69 #define rdtsc(low,high) \
  70      __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
  71
  72 #define rdtscl(low) \
  73      __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
  74
  75 #define rdtscll(val) \
  76      __asm__ __volatile__("rdtsc" : "=A" (val))
  77
  78 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
  79
  80 #define rdpmc(counter,low,high) \
  81      __asm__ __volatile__("rdpmc" \
  82                           : "=a" (low), "=d" (high) \
  83                           : "c" (counter))
  84 #endif  /* !CONFIG_PARAVIRT */
  85
  86 /* symbolic names for some interesting MSRs */
  87 /* Intel defined MSRs. */
  88 #define MSR_IA32_P5_MC_ADDR             0
  89 #define MSR_IA32_P5_MC_TYPE             1
  90 #define MSR_IA32_PLATFORM_ID            0x17
  91 #define MSR_IA32_EBL_CR_POWERON         0x2a
  92
  93 #define MSR_IA32_APICBASE               0x1b
  94 #define MSR_IA32_APICBASE_BSP           (1<<8)
  95 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
  96 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
  97
  98 #define MSR_IA32_UCODE_WRITE            0x79
  99 #define MSR_IA32_UCODE_REV              0x8b
 100
 101 #define MSR_P6_PERFCTR0         0xc1
 102 #define MSR_P6_PERFCTR1         0xc2
 103 #define MSR_FSB_FREQ            0xcd
 104
 105
 106 #define MSR_IA32_BBL_CR_CTL             0x119
 107
 108 #define MSR_IA32_SYSENTER_CS            0x174
 109 #define MSR_IA32_SYSENTER_ESP           0x175
 110 #define MSR_IA32_SYSENTER_EIP           0x176
 111
 112 #define MSR_IA32_MCG_CAP                0x179
 113 #define MSR_IA32_MCG_STATUS             0x17a
 114 #define MSR_IA32_MCG_CTL                0x17b
 115
 116 /* P4/Xeon+ specific */
 117 #define MSR_IA32_MCG_EAX                0x180
 118 #define MSR_IA32_MCG_EBX                0x181
 119 #define MSR_IA32_MCG_ECX                0x182
 120 #define MSR_IA32_MCG_EDX                0x183
 121 #define MSR_IA32_MCG_ESI                0x184
 122 #define MSR_IA32_MCG_EDI                0x185
 123 #define MSR_IA32_MCG_EBP                0x186
 124 #define MSR_IA32_MCG_ESP                0x187
 125 #define MSR_IA32_MCG_EFLAGS             0x188
 126 #define MSR_IA32_MCG_EIP                0x189
 127 #define MSR_IA32_MCG_RESERVED           0x18A
 128
 129 #define MSR_P6_EVNTSEL0                 0x186
 130 #define MSR_P6_EVNTSEL1                 0x187
 131
 132 #define MSR_IA32_PERF_STATUS            0x198
 133 #define MSR_IA32_PERF_CTL               0x199
 134
 135 #define MSR_IA32_MPERF                  0xE7
 136 #define MSR_IA32_APERF                  0xE8
 137
 138 #define MSR_IA32_THERM_CONTROL          0x19a
 139 #define MSR_IA32_THERM_INTERRUPT        0x19b
 140 #define MSR_IA32_THERM_STATUS           0x19c
 141 #define MSR_IA32_MISC_ENABLE            0x1a0
 142
 143 #define MSR_IA32_DEBUGCTLMSR            0x1d9
 144 #define MSR_IA32_LASTBRANCHFROMIP       0x1db
 145 #define MSR_IA32_LASTBRANCHTOIP         0x1dc
 146 #define MSR_IA32_LASTINTFROMIP          0x1dd
 147 #define MSR_IA32_LASTINTTOIP            0x1de
 148
 149 #define MSR_IA32_MC0_CTL                0x400
 150 #define MSR_IA32_MC0_STATUS             0x401
 151 #define MSR_IA32_MC0_ADDR               0x402
 152 #define MSR_IA32_MC0_MISC               0x403
 153
 154 #define MSR_IA32_PEBS_ENABLE            0x3f1
 155 #define MSR_IA32_DS_AREA                0x600
 156 #define MSR_IA32_PERF_CAPABILITIES      0x345
 157
 158 /* Pentium IV performance counter MSRs */
 159 #define MSR_P4_BPU_PERFCTR0             0x300
 160 #define MSR_P4_BPU_PERFCTR1             0x301
 161 #define MSR_P4_BPU_PERFCTR2             0x302
 162 #define MSR_P4_BPU_PERFCTR3             0x303
 163 #define MSR_P4_MS_PERFCTR0              0x304
 164 #define MSR_P4_MS_PERFCTR1              0x305
 165 #define MSR_P4_MS_PERFCTR2              0x306
 166 #define MSR_P4_MS_PERFCTR3              0x307
 167 #define MSR_P4_FLAME_PERFCTR0           0x308
 168 #define MSR_P4_FLAME_PERFCTR1           0x309
 169 #define MSR_P4_FLAME_PERFCTR2           0x30a
 170 #define MSR_P4_FLAME_PERFCTR3           0x30b
 171 #define MSR_P4_IQ_PERFCTR0              0x30c
 172 #define MSR_P4_IQ_PERFCTR1              0x30d
 173 #define MSR_P4_IQ_PERFCTR2              0x30e
 174 #define MSR_P4_IQ_PERFCTR3              0x30f
 175 #define MSR_P4_IQ_PERFCTR4              0x310
 176 #define MSR_P4_IQ_PERFCTR5              0x311
 177 #define MSR_P4_BPU_CCCR0                0x360
 178 #define MSR_P4_BPU_CCCR1                0x361
 179 #define MSR_P4_BPU_CCCR2                0x362
 180 #define MSR_P4_BPU_CCCR3                0x363
 181 #define MSR_P4_MS_CCCR0                 0x364
 182 #define MSR_P4_MS_CCCR1                 0x365
 183 #define MSR_P4_MS_CCCR2                 0x366
 184 #define MSR_P4_MS_CCCR3                 0x367
 185 #define MSR_P4_FLAME_CCCR0              0x368
 186 #define MSR_P4_FLAME_CCCR1              0x369
 187 #define MSR_P4_FLAME_CCCR2              0x36a
 188 #define MSR_P4_FLAME_CCCR3              0x36b
 189 #define MSR_P4_IQ_CCCR0                 0x36c
 190 #define MSR_P4_IQ_CCCR1                 0x36d
 191 #define MSR_P4_IQ_CCCR2                 0x36e
 192 #define MSR_P4_IQ_CCCR3                 0x36f
 193 #define MSR_P4_IQ_CCCR4                 0x370
 194 #define MSR_P4_IQ_CCCR5                 0x371
 195 #define MSR_P4_ALF_ESCR0                0x3ca
 196 #define MSR_P4_ALF_ESCR1                0x3cb
 197 #define MSR_P4_BPU_ESCR0                0x3b2
 198 #define MSR_P4_BPU_ESCR1                0x3b3
 199 #define MSR_P4_BSU_ESCR0                0x3a0
 200 #define MSR_P4_BSU_ESCR1                0x3a1
 201 #define MSR_P4_CRU_ESCR0                0x3b8
 202 #define MSR_P4_CRU_ESCR1                0x3b9
 203 #define MSR_P4_CRU_ESCR2                0x3cc
 204 #define MSR_P4_CRU_ESCR3                0x3cd
 205 #define MSR_P4_CRU_ESCR4                0x3e0
 206 #define MSR_P4_CRU_ESCR5                0x3e1
 207 #define MSR_P4_DAC_ESCR0                0x3a8
 208 #define MSR_P4_DAC_ESCR1                0x3a9
 209 #define MSR_P4_FIRM_ESCR0               0x3a4
 210 #define MSR_P4_FIRM_ESCR1               0x3a5
 211 #define MSR_P4_FLAME_ESCR0              0x3a6
 212 #define MSR_P4_FLAME_ESCR1              0x3a7
 213 #define MSR_P4_FSB_ESCR0                0x3a2
 214 #define MSR_P4_FSB_ESCR1                0x3a3
 215 #define MSR_P4_IQ_ESCR0                 0x3ba
 216 #define MSR_P4_IQ_ESCR1                 0x3bb
 217 #define MSR_P4_IS_ESCR0                 0x3b4
 218 #define MSR_P4_IS_ESCR1                 0x3b5
 219 #define MSR_P4_ITLB_ESCR0               0x3b6
 220 #define MSR_P4_ITLB_ESCR1               0x3b7
 221 #define MSR_P4_IX_ESCR0                 0x3c8
 222 #define MSR_P4_IX_ESCR1                 0x3c9
 223 #define MSR_P4_MOB_ESCR0                0x3aa
 224 #define MSR_P4_MOB_ESCR1                0x3ab
 225 #define MSR_P4_MS_ESCR0                 0x3c0
 226 #define MSR_P4_MS_ESCR1                 0x3c1
 227 #define MSR_P4_PMH_ESCR0                0x3ac
 228 #define MSR_P4_PMH_ESCR1                0x3ad
 229 #define MSR_P4_RAT_ESCR0                0x3bc
 230 #define MSR_P4_RAT_ESCR1                0x3bd
 231 #define MSR_P4_SAAT_ESCR0               0x3ae
 232 #define MSR_P4_SAAT_ESCR1               0x3af
 233 #define MSR_P4_SSU_ESCR0                0x3be
 234 #define MSR_P4_SSU_ESCR1                0x3bf    /* guess: not defined in manual */
 235 #define MSR_P4_TBPU_ESCR0               0x3c2
 236 #define MSR_P4_TBPU_ESCR1               0x3c3
 237 #define MSR_P4_TC_ESCR0                 0x3c4
 238 #define MSR_P4_TC_ESCR1                 0x3c5
 239 #define MSR_P4_U2L_ESCR0                0x3b0
 240 #define MSR_P4_U2L_ESCR1                0x3b1
 241
 242 /* AMD Defined MSRs */
 243 #define MSR_K6_EFER                     0xC0000080
 244 #define MSR_K6_STAR                     0xC0000081
 245 #define MSR_K6_WHCR                     0xC0000082
 246 #define MSR_K6_UWCCR                    0xC0000085
 247 #define MSR_K6_EPMR                     0xC0000086
 248 #define MSR_K6_PSOR                     0xC0000087
 249 #define MSR_K6_PFIR                     0xC0000088
 250
 251 #define MSR_K7_EVNTSEL0                 0xC0010000
 252 #define MSR_K7_EVNTSEL1                 0xC0010001
 253 #define MSR_K7_EVNTSEL2                 0xC0010002
 254 #define MSR_K7_EVNTSEL3                 0xC0010003
 255 #define MSR_K7_PERFCTR0                 0xC0010004
 256 #define MSR_K7_PERFCTR1                 0xC0010005
 257 #define MSR_K7_PERFCTR2                 0xC0010006
 258 #define MSR_K7_PERFCTR3                 0xC0010007
 259 #define MSR_K7_HWCR                     0xC0010015
 260 #define MSR_K7_CLK_CTL                  0xC001001b
 261 #define MSR_K7_FID_VID_CTL              0xC0010041
 262 #define MSR_K7_FID_VID_STATUS           0xC0010042
 263
 264 /* extended feature register */
 265 #define MSR_EFER                        0xc0000080
 266
 267 /* EFER bits: */
 268
 269 /* Execute Disable enable */
 270 #define _EFER_NX                        11
 271 #define EFER_NX                         (1<<_EFER_NX)
 272
 273 /* Centaur-Hauls/IDT defined MSRs. */
 274 #define MSR_IDT_FCR1                    0x107
 275 #define MSR_IDT_FCR2                    0x108
 276 #define MSR_IDT_FCR3                    0x109
 277 #define MSR_IDT_FCR4                    0x10a
 278
 279 #define MSR_IDT_MCR0                    0x110
 280 #define MSR_IDT_MCR1                    0x111
 281 #define MSR_IDT_MCR2                    0x112
 282 #define MSR_IDT_MCR3                    0x113
 283 #define MSR_IDT_MCR4                    0x114
 284 #define MSR_IDT_MCR5                    0x115
 285 #define MSR_IDT_MCR6                    0x116
 286 #define MSR_IDT_MCR7                    0x117
 287 #define MSR_IDT_MCR_CTRL                0x120
 288
 289 /* VIA Cyrix defined MSRs*/
 290 #define MSR_VIA_FCR                     0x1107
 291 #define MSR_VIA_LONGHAUL                0x110a
 292 #define MSR_VIA_RNG                     0x110b
 293 #define MSR_VIA_BCR2                    0x1147
 294
 295 /* Transmeta defined MSRs */
 296 #define MSR_TMTA_LONGRUN_CTRL           0x80868010
 297 #define MSR_TMTA_LONGRUN_FLAGS          0x80868011
 298 #define MSR_TMTA_LRTI_READOUT           0x80868018
 299 #define MSR_TMTA_LRTI_VOLT_MHZ          0x8086801a
 300
 301 /* Intel Core-based CPU performance counters */
 302 #define MSR_CORE_PERF_FIXED_CTR0        0x309
 303 #define MSR_CORE_PERF_FIXED_CTR1        0x30a
 304 #define MSR_CORE_PERF_FIXED_CTR2        0x30b
 305 #define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
 306 #define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
 307 #define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
 308 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
 309
 310 #endif /* __ASM_MSR_H */