include/asm-sparc64/mmu_context.h

   1 /* $Id: mmu_context.h,v 1.42 2000/02/08 07:47:03 davem Exp $ */
   2 #ifndef __SPARC64_MMU_CONTEXT_H
   3 #define __SPARC64_MMU_CONTEXT_H
   4
   5 /* Derived heavily from Linus's Alpha/AXP ASN code... */
   6
   7 #ifndef __ASSEMBLY__
   8
   9 #include <linux/spinlock.h>
  10 #include <asm/system.h>
  11 #include <asm/spitfire.h>
  12
  13 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk, unsigned cpu)
  14 {
  15 }
  16
  17 extern spinlock_t ctx_alloc_lock;
  18 extern unsigned long tlb_context_cache;
  19 extern unsigned long mmu_context_bmap[];
  20
  21 #define CTX_VERSION_SHIFT       (PAGE_SHIFT - 3)
  22 #define CTX_VERSION_MASK        ((~0UL) << CTX_VERSION_SHIFT)
  23 #define CTX_FIRST_VERSION       ((1UL << CTX_VERSION_SHIFT) + 1UL)
  24 #define CTX_VALID(__ctx)        \
  25          (!(((__ctx) ^ tlb_context_cache) & CTX_VERSION_MASK))
  26 #define CTX_HWBITS(__ctx)       ((__ctx) & ~CTX_VERSION_MASK)
  27
  28 extern void get_new_mmu_context(struct mm_struct *mm);
  29
  30 /* Initialize a new mmu context.  This is invoked when a new
  31  * address space instance (unique or shared) is instantiated.
  32  * A fresh mm_struct is cleared out to zeros, so this need not
  33  * do anything on Sparc64 since the only thing we care about
  34  * is that mm->context is an invalid context (ie. zero).
  35  */
  36 #define init_new_context(__tsk, __mm)   do { } while(0)
  37
  38 /* Destroy a dead context.  This occurs when mmput drops the
  39  * mm_users count to zero, the mmaps have been released, and
  40  * all the page tables have been flushed.  Our job is to destroy
  41  * any remaining processor-specific state, and in the sparc64
  42  * case this just means freeing up the mmu context ID held by
  43  * this task if valid.
  44  */
  45 #define destroy_context(__mm)                                   \
  46 do {    spin_lock(&ctx_alloc_lock);                             \
  47         if (CTX_VALID((__mm)->context)) {                       \
  48                 unsigned long nr = CTX_HWBITS((__mm)->context); \
  49                 mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63)); \
  50         }                                                       \
  51         spin_unlock(&ctx_alloc_lock);                           \
  52 } while(0)
  53
  54 /* Reload the two core values used by TLB miss handler
  55  * processing on sparc64.  They are:
  56  * 1) The physical address of mm->pgd, when full page
  57  *    table walks are necessary, this is where the
  58  *    search begins.
  59  * 2) A "PGD cache".  For 32-bit tasks only pgd[0] is
  60  *    ever used since that maps the entire low 4GB
  61  *    completely.  To speed up TLB miss processing we
  62  *    make this value available to the handlers.  This
  63  *    decreases the amount of memory traffic incurred.
  64  */
  65 #define reload_tlbmiss_state(__tsk, __mm) \
  66 do { \
  67         register unsigned long paddr asm("o5"); \
  68         register unsigned long pgd_cache asm("o4"); \
  69         paddr = __pa((__mm)->pgd); \
  70         pgd_cache = 0UL; \
  71         if ((__tsk)->thread.flags & SPARC_FLAG_32BIT) \
  72                 pgd_cache = pgd_val((__mm)->pgd[0]) << 11UL; \
  73         __asm__ __volatile__("wrpr      %%g0, 0x494, %%pstate\n\t" \
  74                              "mov       %3, %%g4\n\t" \
  75                              "mov       %0, %%g7\n\t" \
  76                              "stxa      %1, [%%g4] %2\n\t" \
  77                              "wrpr      %%g0, 0x096, %%pstate" \
  78                              : /* no outputs */ \
  79                              : "r" (paddr), "r" (pgd_cache),\
  80                                "i" (ASI_DMMU), "i" (TSB_REG)); \
  81 } while(0)
  82
  83 /* Set MMU context in the actual hardware. */
  84 #define load_secondary_context(__mm) \
  85         __asm__ __volatile__("stxa      %0, [%1] %2\n\t" \
  86                              "flush     %%g6" \
  87                              : /* No outputs */ \
  88                              : "r" (CTX_HWBITS((__mm)->context)), \
  89                                "r" (0x10), "i" (0x58))
  90
  91 /* Clean out potential stale TLB entries due to previous
  92  * users of this TLB context.  We flush TLB contexts
  93  * lazily on sparc64.
  94  */
  95 #define clean_secondary_context() \
  96         __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t" \
  97                              "stxa      %%g0, [%0] %2\n\t" \
  98                              "flush     %%g6" \
  99                              : /* No outputs */ \
 100                              : "r" (0x50), "i" (0x5f), "i" (0x57))
 101
 102 /* Switch the current MM context. */
 103 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk, int cpu)
 104 {
 105         long dirty;
 106
 107         spin_lock(&mm->page_table_lock);
 108         if (CTX_VALID(mm->context))
 109                 dirty = 0;
 110         else
 111                 dirty = 1;
 112         if (dirty || (old_mm != mm)) {
 113                 unsigned long vm_mask;
 114
 115                 if (dirty)
 116                         get_new_mmu_context(mm);
 117
 118                 vm_mask = (1UL << cpu);
 119                 if (!(mm->cpu_vm_mask & vm_mask)) {
 120                         mm->cpu_vm_mask |= vm_mask;
 121                         dirty = 1;
 122                 }
 123
 124                 load_secondary_context(mm);
 125                 if (dirty != 0)
 126                         clean_secondary_context();
 127                 reload_tlbmiss_state(tsk, mm);
 128         }
 129         spin_unlock(&mm->page_table_lock);
 130 }
 131
 132 /* Activate a new MM instance for the current task. */
 133 static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
 134 {
 135         unsigned long vm_mask;
 136
 137         spin_lock(&mm->page_table_lock);
 138         if (!CTX_VALID(mm->context))
 139                 get_new_mmu_context(mm);
 140         vm_mask = (1UL << smp_processor_id());
 141         if (!(mm->cpu_vm_mask & vm_mask))
 142                 mm->cpu_vm_mask |= vm_mask;
 143         spin_unlock(&mm->page_table_lock);
 144
 145         load_secondary_context(mm);
 146         clean_secondary_context();
 147         reload_tlbmiss_state(current, mm);
 148 }
 149
 150 #endif /* !(__ASSEMBLY__) */
 151
 152 #endif /* !(__SPARC64_MMU_CONTEXT_H) */