include/asm-sparc64/irq.h

   1 /* $Id: irq.h,v 1.19 2000/06/26 19:40:27 davem Exp $
   2  * irq.h: IRQ registers on the 64-bit Sparc.
   3  *
   4  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
   6  */
   7
   8 #ifndef _SPARC64_IRQ_H
   9 #define _SPARC64_IRQ_H
  10
  11 #include <linux/config.h>
  12 #include <linux/linkage.h>
  13 #include <linux/kernel.h>
  14
  15 struct devid_cookie {
  16         int dummy;
  17 };
  18
  19 /* You should not mess with this directly. That's the job of irq.c.
  20  *
  21  * If you make changes here, please update hand coded assembler of
  22  * SBUS/floppy interrupt handler in entry.S -DaveM
  23  *
  24  * This is currently one DCACHE line, two buckets per L2 cache
  25  * line.  Keep this in mind please.
  26  */
  27 struct ino_bucket {
  28         /* Next handler in per-CPU PIL worklist.  We know that
  29          * bucket pointers have the high 32-bits clear, so to
  30          * save space we only store the bits we need.
  31          */
  32 /*0x00*/unsigned int irq_chain;
  33
  34         /* PIL to schedule this IVEC at. */
  35 /*0x04*/unsigned char pil;
  36
  37         /* If an IVEC arrives while irq_info is NULL, we
  38          * set this to notify request_irq() about the event.
  39          */
  40 /*0x05*/unsigned char pending;
  41
  42         /* Miscellaneous flags. */
  43 /*0x06*/unsigned char flags;
  44
  45         /* This is used to deal with IBF_DMA_SYNC on
  46          * Sabre systems.
  47          */
  48 /*0x07*/unsigned char synctab_ent;
  49
  50         /* Reference to handler for this IRQ.  If this is
  51          * non-NULL this means it is active and should be
  52          * serviced.  Else the pending member is set to one
  53          * and later registry of the interrupt checks for
  54          * this condition.
  55          *
  56          * Normally this is just an irq_action structure.
  57          * But, on PCI, if multiple interrupt sources behind
  58          * a bridge have multiple interrupt sources that share
  59          * the same INO bucket, this points to an array of
  60          * pointers to four IRQ action structures.
  61          */
  62 /*0x08*/void *irq_info;
  63
  64         /* Sun5 Interrupt Clear Register. */
  65 /*0x10*/unsigned long iclr;
  66
  67         /* Sun5 Interrupt Mapping Register. */
  68 /*0x18*/unsigned long imap;
  69
  70 };
  71
  72 #ifdef CONFIG_PCI
  73 extern unsigned long pci_dma_wsync;
  74 extern unsigned long dma_sync_reg_table[256];
  75 extern unsigned char dma_sync_reg_table_entry;
  76 #endif
  77
  78 /* IMAP/ICLR register defines */
  79 #define IMAP_VALID              0x80000000      /* IRQ Enabled          */
  80 #define IMAP_TID                0x7c000000      /* UPA TargetID         */
  81 #define IMAP_IGN                0x000007c0      /* IRQ Group Number     */
  82 #define IMAP_INO                0x0000003f      /* IRQ Number           */
  83 #define IMAP_INR                0x000007ff      /* Full interrupt number*/
  84
  85 #define ICLR_IDLE               0x00000000      /* Idle state           */
  86 #define ICLR_TRANSMIT           0x00000001      /* Transmit state       */
  87 #define ICLR_PENDING            0x00000003      /* Pending state        */
  88
  89 /* Only 8-bits are available, be careful.  -DaveM */
  90 #define IBF_DMA_SYNC    0x01    /* DMA synchronization behind PCI bridge needed. */
  91 #define IBF_PCI         0x02    /* Indicates PSYCHO/SABRE/SCHIZO PCI interrupt.  */
  92 #define IBF_ACTIVE      0x04    /* This interrupt is active and has a handler.   */
  93 #define IBF_MULTI       0x08    /* On PCI, indicates shared bucket.              */
  94
  95 #define NUM_IVECS       8192
  96 extern struct ino_bucket ivector_table[NUM_IVECS];
  97
  98 #define __irq_ino(irq) \
  99         (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
 100 #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
 101 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
 102 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
 103
 104 static __inline__ char *__irq_itoa(unsigned int irq)
 105 {
 106         static char buff[16];
 107
 108         sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
 109         return buff;
 110 }
 111
 112 #define NR_IRQS    15
 113
 114 extern void disable_irq(unsigned int);
 115 #define disable_irq_nosync disable_irq
 116 extern void enable_irq(unsigned int);
 117 extern void init_timers(void (*lvl10_irq)(int, void *, struct pt_regs *),
 118                         unsigned long *);
 119 extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
 120 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
 121 extern unsigned int psycho_build_irq(void *psycho, int imap_off, int ino, int need_dma_sync);
 122
 123 #ifdef CONFIG_SMP
 124 extern void set_cpu_int(int, int);
 125 extern void clear_cpu_int(int, int);
 126 extern void set_irq_udt(int);
 127 #endif
 128
 129 extern int request_fast_irq(unsigned int irq,
 130                             void (*handler)(int, void *, struct pt_regs *),
 131                             unsigned long flags, __const__ char *devname,
 132                             void *dev_id);
 133
 134 extern __inline__ void set_softint(unsigned long bits)
 135 {
 136         __asm__ __volatile__("wr        %0, 0x0, %%set_softint"
 137                              : /* No outputs */
 138                              : "r" (bits));
 139 }
 140
 141 extern __inline__ void clear_softint(unsigned long bits)
 142 {
 143         __asm__ __volatile__("wr        %0, 0x0, %%clear_softint"
 144                              : /* No outputs */
 145                              : "r" (bits));
 146 }
 147
 148 extern __inline__ unsigned long get_softint(void)
 149 {
 150         unsigned long retval;
 151
 152         __asm__ __volatile__("rd        %%softint, %0"
 153                              : "=r" (retval));
 154         return retval;
 155 }
 156
 157 #endif