include/asm-ppc/pgtable.h

   1 #ifndef _PPC_PGTABLE_H
   2 #define _PPC_PGTABLE_H
   3
   4 #include <linux/config.h>
   5
   6 #ifndef __ASSEMBLY__
   7 #include <linux/sched.h>
   8 #include <linux/threads.h>
   9 #include <asm/processor.h>              /* For TASK_SIZE */
  10 #include <asm/mmu.h>
  11 #include <asm/page.h>
  12
  13 #if defined(CONFIG_4xx)
  14 extern void local_flush_tlb_all(void);
  15 extern void local_flush_tlb_mm(struct mm_struct *mm);
  16 extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
  17 extern void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
  18                                   unsigned long end);
  19 extern inline void flush_hash_page(unsigned context, unsigned long va)
  20         { }
  21 #elif defined(CONFIG_8xx)
  22 #define __tlbia()       asm volatile ("tlbia" : : )
  23
  24 extern inline void local_flush_tlb_all(void)
  25         { __tlbia(); }
  26 extern inline void local_flush_tlb_mm(struct mm_struct *mm)
  27         { __tlbia(); }
  28 extern inline void local_flush_tlb_page(struct vm_area_struct *vma,
  29                                 unsigned long vmaddr)
  30         { __tlbia(); }
  31 extern inline void local_flush_tlb_range(struct mm_struct *mm,
  32                                 unsigned long start, unsigned long end)
  33         { __tlbia(); }
  34 extern inline void flush_hash_page(unsigned context, unsigned long va)
  35         { }
  36 #else
  37 struct mm_struct;
  38 struct vm_area_struct;
  39 extern void local_flush_tlb_all(void);
  40 extern void local_flush_tlb_mm(struct mm_struct *mm);
  41 extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
  42 extern void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
  43                             unsigned long end);
  44 #endif
  45
  46 #define flush_tlb_all local_flush_tlb_all
  47 #define flush_tlb_mm local_flush_tlb_mm
  48 #define flush_tlb_page local_flush_tlb_page
  49 #define flush_tlb_range local_flush_tlb_range
  50
  51 extern inline void flush_tlb_pgtables(struct mm_struct *mm,
  52                                 unsigned long start, unsigned long end)
  53 {
  54         /* PPC has hw page tables. */
  55 }
  56
  57 /*
  58  * No cache flushing is required when address mappings are
  59  * changed, because the caches on PowerPCs are physically
  60  * addressed.
  61  * Also, when SMP we use the coherency (M) bit of the
  62  * BATs and PTEs.  -- Cort
  63  */
  64 #define flush_cache_all()               do { } while (0)
  65 #define flush_cache_mm(mm)              do { } while (0)
  66 #define flush_cache_range(mm, a, b)     do { } while (0)
  67 #define flush_cache_page(vma, p)        do { } while (0)
  68 #define flush_icache_page(vma, page)    do { } while (0)
  69
  70 extern void flush_icache_range(unsigned long, unsigned long);
  71 extern void __flush_page_to_ram(unsigned long page_va);
  72 #define flush_page_to_ram(page) __flush_page_to_ram(page_address(page))
  73
  74 extern unsigned long va_to_phys(unsigned long address);
  75 extern pte_t *va_to_pte(unsigned long address);
  76 extern unsigned long ioremap_bot, ioremap_base;
  77 #endif /* __ASSEMBLY__ */
  78
  79 /*
  80  * The PowerPC MMU uses a hash table containing PTEs, together with
  81  * a set of 16 segment registers (on 32-bit implementations), to define
  82  * the virtual to physical address mapping.
  83  *
  84  * We use the hash table as an extended TLB, i.e. a cache of currently
  85  * active mappings.  We maintain a two-level page table tree, much like
  86  * that used by the i386, for the sake of the Linux memory management code.
  87  * Low-level assembler code in head.S (procedure hash_page) is responsible
  88  * for extracting ptes from the tree and putting them into the hash table
  89  * when necessary, and updating the accessed and modified bits in the
  90  * page table tree.
  91  */
  92
  93 /*
  94  * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
  95  * We also use the two level tables, but we can put the real bits in them
  96  * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
  97  * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
  98  * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
  99  * based upon user/super access.  The TLB does not have accessed nor write
 100  * protect.  We assume that if the TLB get loaded with an entry it is
 101  * accessed, and overload the changed bit for write protect.  We use
 102  * two bits in the software pte that are supposed to be set to zero in
 103  * the TLB entry (24 and 25) for these indicators.  Although the level 1
 104  * descriptor contains the guarded and writethrough/copyback bits, we can
 105  * set these at the page level since they get copied from the Mx_TWC
 106  * register when the TLB entry is loaded.  We will use bit 27 for guard, since
 107  * that is where it exists in the MD_TWC, and bit 26 for writethrough.
 108  * These will get masked from the level 2 descriptor at TLB load time, and
 109  * copied to the MD_TWC before it gets loaded.
 110  */
 111
 112 /*
 113  * At present, all PowerPC 400-class processors share a similar TLB
 114  * architecture. The instruction and data sides share a unified,
 115  * 64-entry, fully-associative TLB which is maintained totally under
 116  * software control. In addition, the instruction side has a
 117  * hardware-managed, 4-entry, fully-associative TLB which serves as a
 118  * first level to the shared TLB. These two TLBs are known as the UTLB
 119  * and ITLB, respectively (see "mmu.h" for definitions).
 120  */
 121
 122 /* PMD_SHIFT determines the size of the area mapped by the second-level page tables */
 123 #define PMD_SHIFT       22
 124 #define PMD_SIZE        (1UL << PMD_SHIFT)
 125 #define PMD_MASK        (~(PMD_SIZE-1))
 126
 127 /* PGDIR_SHIFT determines what a third-level page table entry can map */
 128 #define PGDIR_SHIFT     22
 129 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 130 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 131
 132 /*
 133  * entries per page directory level: our page-table tree is two-level, so
 134  * we don't really have any PMD directory.
 135  */
 136 #define PTRS_PER_PTE    1024
 137 #define PTRS_PER_PMD    1
 138 #define PTRS_PER_PGD    1024
 139 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
 140 #define FIRST_USER_PGD_NR       0
 141
 142 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
 143 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
 144
 145 #define pte_ERROR(e) \
 146         printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 147 #define pmd_ERROR(e) \
 148         printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 149 #define pgd_ERROR(e) \
 150         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 151
 152 /*
 153  * Just any arbitrary offset to the start of the vmalloc VM area: the
 154  * current 64MB value just means that there will be a 64MB "hole" after the
 155  * physical memory until the kernel virtual memory starts.  That means that
 156  * any out-of-bounds memory accesses will hopefully be caught.
 157  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 158  * area for the same reason. ;)
 159  *
 160  * We no longer map larger than phys RAM with the BATs so we don't have
 161  * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
 162  * about clashes between our early calls to ioremap() that start growing down
 163  * from ioremap_base being run into the VM area allocations (growing upwards
 164  * from VMALLOC_START).  For this reason we have ioremap_bot to check when
 165  * we actually run into our mappings setup in the early boot with the VM
 166  * system.  This really does become a problem for machines with good amounts
 167  * of RAM.  -- Cort
 168  */
 169 #define VMALLOC_OFFSET (0x1000000) /* 16M */
 170 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 171 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
 172 #define VMALLOC_END     ioremap_bot
 173
 174 /*
 175  * Bits in a linux-style PTE.  These match the bits in the
 176  * (hardware-defined) PowerPC PTE as closely as possible.
 177  */
 178
 179 #if defined(CONFIG_4xx)
 180 /* Definitions for 4xx embedded chips. */
 181 #define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
 182 #define _PAGE_COHERENT  0x002   /* M: enforece memory coherence */
 183 #define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
 184 #define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
 185 #define _PAGE_USER      0x010   /* matches one of the zone permission bits */
 186 #define _PAGE_PRESENT   0x040   /* software: PTE contains a translation */
 187 #define _PAGE_DIRTY     0x100   /* C: page changed */
 188 #define _PAGE_RW        0x200   /* Writes permitted */
 189 #define _PAGE_ACCESSED  0x400   /* R: page referenced */
 190 #define _PAGE_HWWRITE   0x800   /* software: _PAGE_RW & _PAGE_DIRTY */
 191 #define _PAGE_SHARED    0
 192
 193 #elif defined(CONFIG_8xx)
 194 /* Definitions for 8xx embedded chips. */
 195 #define _PAGE_PRESENT   0x0001  /* Page is valid */
 196 #define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
 197 #define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
 198
 199 /* These five software bits must be masked out when the entry is loaded
 200  * into the TLB.
 201  */
 202 #define _PAGE_DIRTY     0x0008  /* software: page changed */
 203 #define _PAGE_GUARDED   0x0010  /* software: guarded access */
 204 #define _PAGE_WRITETHRU 0x0020  /* software: use writethrough cache */
 205 #define _PAGE_RW        0x0040  /* software: user write access allowed */
 206 #define _PAGE_ACCESSED  0x0080  /* software: page referenced */
 207
 208 #define _PAGE_HWWRITE   0x0100  /* C: page changed (write protect) */
 209 #define _PAGE_USER      0x0800  /* One of the PP bits, the other must be 0 */
 210
 211 #else /* CONFIG_6xx */
 212 /* Definitions for 60x, 740/750, etc. */
 213 #define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
 214 #define _PAGE_USER      0x002   /* matches one of the PP bits */
 215 #define _PAGE_RW        0x004   /* software: user write access allowed */
 216 #define _PAGE_GUARDED   0x008
 217 #define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
 218 #define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
 219 #define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
 220 #define _PAGE_DIRTY     0x080   /* C: page changed */
 221 #define _PAGE_ACCESSED  0x100   /* R: page referenced */
 222 #define _PAGE_HWWRITE   0x200   /* software: _PAGE_RW & _PAGE_DIRTY */
 223 #define _PAGE_SHARED    0
 224 #endif
 225
 226 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 227
 228 #ifdef CONFIG_SMP
 229 #define _PAGE_BASE      _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT
 230 #else
 231 #define _PAGE_BASE      _PAGE_PRESENT | _PAGE_ACCESSED
 232 #endif
 233 #define _PAGE_WRENABLE  _PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE
 234
 235 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
 236
 237 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | \
 238                                  _PAGE_SHARED)
 239 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
 240 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
 241 #define PAGE_KERNEL     __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED)
 242 #define PAGE_KERNEL_CI  __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | \
 243                                  _PAGE_NO_CACHE )
 244
 245 /*
 246  * The PowerPC can only do execute protection on a segment (256MB) basis,
 247  * not on a page basis.  So we consider execute permission the same as read.
 248  * Also, write permissions imply read permissions.
 249  * This is the closest we can get..
 250  */
 251 #define __P000  PAGE_NONE
 252 #define __P001  PAGE_READONLY
 253 #define __P010  PAGE_COPY
 254 #define __P011  PAGE_COPY
 255 #define __P100  PAGE_READONLY
 256 #define __P101  PAGE_READONLY
 257 #define __P110  PAGE_COPY
 258 #define __P111  PAGE_COPY
 259
 260 #define __S000  PAGE_NONE
 261 #define __S001  PAGE_READONLY
 262 #define __S010  PAGE_SHARED
 263 #define __S011  PAGE_SHARED
 264 #define __S100  PAGE_READONLY
 265 #define __S101  PAGE_READONLY
 266 #define __S110  PAGE_SHARED
 267 #define __S111  PAGE_SHARED
 268
 269 #ifndef __ASSEMBLY__
 270 /*
 271  * ZERO_PAGE is a global shared page that is always zero: used
 272  * for zero-mapped memory areas etc..
 273  */
 274 extern unsigned long empty_zero_page[1024];
 275 #define ZERO_PAGE(vaddr) (mem_map + MAP_NR(empty_zero_page))
 276
 277 /*
 278  * BAD_PAGETABLE is used when we need a bogus page-table, while
 279  * BAD_PAGE is used for a bogus page.
 280  *
 281  * ZERO_PAGE is a global shared page that is always zero: used
 282  * for zero-mapped memory areas etc..
 283  */
 284 extern pte_t __bad_page(void);
 285 extern pte_t * __bad_pagetable(void);
 286
 287 #define BAD_PAGETABLE   __bad_pagetable()
 288 #define BAD_PAGE        __bad_page()
 289 #endif /* __ASSEMBLY__ */
 290
 291 /* number of bits that fit into a memory pointer */
 292 #define BITS_PER_PTR    (8*sizeof(unsigned long))
 293
 294 /* to align the pointer to a pointer address */
 295 #define PTR_MASK        (~(sizeof(void*)-1))
 296
 297 /* sizeof(void*) == 1<<SIZEOF_PTR_LOG2 */
 298 /* 64-bit machines, beware!  SRB. */
 299 #define SIZEOF_PTR_LOG2 2
 300
 301 #define pte_none(pte)           (!pte_val(pte))
 302 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
 303 #define pte_clear(ptep)         do { pte_val(*(ptep)) = 0; } while (0)
 304 #define pte_pagenr(x)           ((unsigned long)((pte_val(x) >> PAGE_SHIFT)))
 305
 306 #define pmd_none(pmd)           (!pmd_val(pmd))
 307 #define pmd_bad(pmd)            ((pmd_val(pmd) & ~PAGE_MASK) != 0)
 308 #define pmd_present(pmd)        ((pmd_val(pmd) & PAGE_MASK) != 0)
 309 #define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
 310
 311 /*
 312  * Permanent address of a page.
 313  */
 314 #define page_address(page)  ({ if (!(page)->virtual) BUG(); (page)->virtual; })
 315 #define pages_to_mb(x)          ((x) >> (20-PAGE_SHIFT))
 316 #define pte_page(x)             (mem_map+pte_pagenr(x))
 317
 318 #ifndef __ASSEMBLY__
 319 /*
 320  * The "pgd_xxx()" functions here are trivial for a folded two-level
 321  * setup: the pgd is never bad, and a pmd always exists (as it's folded
 322  * into the pgd entry)
 323  */
 324 extern inline int pgd_none(pgd_t pgd)           { return 0; }
 325 extern inline int pgd_bad(pgd_t pgd)            { return 0; }
 326 extern inline int pgd_present(pgd_t pgd)        { return 1; }
 327 #define pgd_clear(xp)                           do { } while (0)
 328
 329 #define pgd_page(pgd) \
 330         ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
 331
 332 /*
 333  * The following only work if pte_present() is true.
 334  * Undefined behaviour if not..
 335  */
 336 extern inline int pte_read(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
 337 extern inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
 338 extern inline int pte_exec(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
 339 extern inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 340 extern inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 341
 342 extern inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
 343 extern inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
 344
 345 extern inline pte_t pte_rdprotect(pte_t pte) {
 346         pte_val(pte) &= ~_PAGE_USER; return pte; }
 347 extern inline pte_t pte_exprotect(pte_t pte) {
 348         pte_val(pte) &= ~_PAGE_USER; return pte; }
 349 extern inline pte_t pte_wrprotect(pte_t pte) {
 350         pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
 351 extern inline pte_t pte_mkclean(pte_t pte) {
 352         pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
 353 extern inline pte_t pte_mkold(pte_t pte) {
 354         pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 355
 356 extern inline pte_t pte_mkread(pte_t pte) {
 357         pte_val(pte) |= _PAGE_USER; return pte; }
 358 extern inline pte_t pte_mkexec(pte_t pte) {
 359         pte_val(pte) |= _PAGE_USER; return pte; }
 360 extern inline pte_t pte_mkwrite(pte_t pte)
 361 {
 362         pte_val(pte) |= _PAGE_RW;
 363         if (pte_val(pte) & _PAGE_DIRTY)
 364                 pte_val(pte) |= _PAGE_HWWRITE;
 365         return pte;
 366 }
 367 extern inline pte_t pte_mkdirty(pte_t pte)
 368 {
 369         pte_val(pte) |= _PAGE_DIRTY;
 370         if (pte_val(pte) & _PAGE_RW)
 371                 pte_val(pte) |= _PAGE_HWWRITE;
 372         return pte;
 373 }
 374 extern inline pte_t pte_mkyoung(pte_t pte) {
 375         pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 376
 377 /* Certain architectures need to do special things when pte's
 378  * within a page table are directly modified.  Thus, the following
 379  * hook is made available.
 380  */
 381 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
 382
 383 /*
 384  * Conversion functions: convert a page and protection to a page entry,
 385  * and a page entry and page directory to the page they refer to.
 386  */
 387
 388 extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
 389 {
 390         pte_t pte;
 391         pte_val(pte) = physpage | pgprot_val(pgprot);
 392         return pte;
 393 }
 394
 395 #define mk_pte(page,pgprot) \
 396 ({                                                                      \
 397         pte_t pte;                                                      \
 398         pte_val(pte) = ((page - mem_map) << PAGE_SHIFT) | pgprot_val(pgprot); \
 399         pte;                                                    \
 400 })
 401
 402 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 403 {
 404         pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
 405         return pte;
 406 }
 407
 408 #define pmd_page(pmd)   (pmd_val(pmd))
 409
 410 /* to find an entry in a kernel page-table-directory */
 411 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 412
 413 /* to find an entry in a page-table-directory */
 414 #define pgd_index(address)       ((address) >> PGDIR_SHIFT)
 415 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 416
 417 /* Find an entry in the second-level page table.. */
 418 extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
 419 {
 420         return (pmd_t *) dir;
 421 }
 422
 423 /* Find an entry in the third-level page table.. */
 424 extern inline pte_t * pte_offset(pmd_t * dir, unsigned long address)
 425 {
 426         return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 427 }
 428
 429 extern pgd_t swapper_pg_dir[1024];
 430 extern void paging_init(void);
 431
 432 /*
 433  * Page tables may have changed.  We don't need to do anything here
 434  * as entries are faulted into the hash table by the low-level
 435  * data/instruction access exception handlers.
 436  */
 437 #define update_mmu_cache(vma, addr, pte)        do { } while (0)
 438
 439 /*
 440  * When flushing the tlb entry for a page, we also need to flush the
 441  * hash table entry.  flush_hash_page is assembler (for speed) in head.S.
 442  */
 443 extern void flush_hash_segments(unsigned low_vsid, unsigned high_vsid);
 444 extern void flush_hash_page(unsigned context, unsigned long va);
 445
 446 /* Encode and de-code a swap entry */
 447 #define SWP_TYPE(entry)                 (((entry).val >> 1) & 0x3f)
 448 #define SWP_OFFSET(entry)               ((entry).val >> 8)
 449 #define SWP_ENTRY(type, offset)         ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
 450 #define pte_to_swp_entry(pte)           ((swp_entry_t) { pte_val(pte) })
 451 #define swp_entry_to_pte(x)             ((pte_t) { (x).val })
 452
 453 #define module_map      vmalloc
 454 #define module_unmap    vfree
 455
 456 /* CONFIG_APUS */
 457 /* For virtual address to physical address conversion */
 458 extern void cache_clear(__u32 addr, int length);
 459 extern void cache_push(__u32 addr, int length);
 460 extern int mm_end_of_chunk (unsigned long addr, int len);
 461 extern unsigned long iopa(unsigned long addr);
 462 extern unsigned long mm_ptov(unsigned long addr) __attribute__ ((const));
 463
 464 /* Values for nocacheflag and cmode */
 465 /* These are not used by the APUS kernel_map, but prevents
 466    compilation errors. */
 467 #define KERNELMAP_FULL_CACHING          0
 468 #define KERNELMAP_NOCACHE_SER           1
 469 #define KERNELMAP_NOCACHE_NONSER        2
 470 #define KERNELMAP_NO_COPYBACK           3
 471
 472 /*
 473  * Map some physical address range into the kernel address space.
 474  */
 475 extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
 476                                 int nocacheflag, unsigned long *memavailp );
 477
 478 /*
 479  * Set cache mode of (kernel space) address range.
 480  */
 481 extern void kernel_set_cachemode (unsigned long address, unsigned long size,
 482                                  unsigned int cmode);
 483
 484 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 485 #define PageSkip(page)          (0)
 486 #define kern_addr_valid(addr)   (1)
 487
 488 #define io_remap_page_range remap_page_range
 489
 490
 491 #endif __ASSEMBLY__
 492 #endif /* _PPC_PGTABLE_H */