include/asm-ppc/mbx.h

   1
   2 /*
   3  * A collection of structures, addresses, and values associated with
   4  * the Motorola MBX boards.  This was originally created for the
   5  * MBX860, and probably needs revisions for other boards (like the 821).
   6  * When this file gets out of control, we can split it up into more
   7  * meaningful pieces.
   8  *
   9  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  10  */
  11 #ifndef __MACH_MBX_DEFS
  12 #define __MACH_MBX_DEFS
  13
  14 /* A Board Information structure that is given to a program when
  15  * EPPC-Bug starts it up.
  16  */
  17 typedef struct bd_info {
  18         unsigned int    bi_tag;         /* Should be 0x42444944 "BDID" */
  19         unsigned int    bi_size;        /* Size of this structure */
  20         unsigned int    bi_revision;    /* revision of this structure */
  21         unsigned int    bi_bdate;       /* EPPCbug date, i.e. 0x11061997 */
  22         unsigned int    bi_memstart;    /* Memory start address */
  23         unsigned int    bi_memsize;     /* Memory (end) size in bytes */
  24         unsigned int    bi_intfreq;     /* Internal Freq, in Hz */
  25         unsigned int    bi_busfreq;     /* Bus Freq, in Hz */
  26         unsigned int    bi_clun;        /* Boot device controller */
  27         unsigned int    bi_dlun;        /* Boot device logical dev */
  28 } bd_t;
  29
  30 /* Memory map for the MBX as configured by EPPC-Bug.  We could reprogram
  31  * The SIU and PCI bridge, and try to use larger MMU pages, but the
  32  * performance gain is not measureable and it certainly complicates the
  33  * generic MMU model.
  34  *
  35  * In a effort to minimize memory usage for embedded applications, any
  36  * PCI driver or ISA driver must request or map the region required by
  37  * the device.  For convenience (and since we can map up to 4 Mbytes with
  38  * a single page table page), the MMU initialization will map the
  39  * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI
  40  * Bridge CSRs 1:1 into the kernel address space.
  41  */
  42 #define PCI_ISA_IO_ADDR         ((unsigned)0x80000000)
  43 #define PCI_ISA_IO_SIZE         ((uint)(512 * 1024 * 1024))
  44 #define PCI_IDE_ADDR            ((unsigned)0x81000000)
  45 #define PCI_ISA_MEM_ADDR        ((unsigned)0xc0000000)
  46 #define PCI_ISA_MEM_SIZE        ((uint)(512 * 1024 * 1024))
  47 #define PCMCIA_MEM_ADDR         ((uint)0xe0000000)
  48 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024 * 1024))
  49 #define PCMCIA_DMA_ADDR         ((uint)0xe4000000)
  50 #define PCMCIA_DMA_SIZE         ((uint)(64 * 1024 * 1024))
  51 #define PCMCIA_ATTRB_ADDR       ((uint)0xe8000000)
  52 #define PCMCIA_ATTRB_SIZE       ((uint)(64 * 1024 * 1024))
  53 #define PCMCIA_IO_ADDR          ((uint)0xec000000)
  54 #define PCMCIA_IO_SIZE          ((uint)(64 * 1024 * 1024))
  55 #define NVRAM_ADDR              ((uint)0xfa000000)
  56 #define NVRAM_SIZE              ((uint)(1 * 1024 * 1024))
  57 #define MBX_CSR_ADDR            ((uint)0xfa100000)
  58 #define MBX_CSR_SIZE            ((uint)(1 * 1024 * 1024))
  59 #define IMAP_ADDR               ((uint)0xfa200000)
  60 #define IMAP_SIZE               ((uint)(64 * 1024))
  61 #define PCI_CSR_ADDR            ((uint)0xfa210000)
  62 #define PCI_CSR_SIZE            ((uint)(64 * 1024))
  63
  64 /* Map additional physical space into well known virtual addresses.  Due
  65  * to virtual address mapping, these physical addresses are not accessible
  66  * in a 1:1 virtual to physical mapping.
  67  */
  68 #define ISA_IO_VIRT_ADDR        ((uint)0xfa220000)
  69 #define ISA_IO_VIRT_SIZE        ((uint)64 * 1024)
  70
  71 /* Interrupt assignments.
  72  * These are defined (and fixed) by the MBX hardware implementation.
  73  */
  74 #define POWER_FAIL_INT  SIU_IRQ0        /* Power fail */
  75 #define TEMP_HILO_INT   SIU_IRQ1        /* Temperature sensor */
  76 #define QSPAN_INT       SIU_IRQ2        /* PCI Bridge (DMA CTLR?) */
  77 #define ISA_BRIDGE_INT  SIU_IRQ3        /* All those PC things */
  78 #define COMM_L_INT      SIU_IRQ6        /* MBX Comm expansion connector pin */
  79 #define STOP_ABRT_INT   SIU_IRQ7        /* Stop/Abort header pin */
  80
  81 /* The MBX uses the 8259.
  82 */
  83 #define NR_8259_INTS    16
  84
  85 /* Generic 8xx type
  86 */
  87 #define _MACH_8xx (_MACH_mbx)
  88 #endif