include/asm-ppc/immap_8260.h

   1
   2 /*
   3  * MPC8260 Internal Memory Map
   4  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
   5  *
   6  * The Internal Memory Map of the 8260.  I don't know how generic
   7  * this will be, as I don't have any knowledge of the subsequent
   8  * parts at this time.  I copied this from the 8xx_immap.h.
   9  */
  10 #ifndef __IMMAP_82XX__
  11 #define __IMMAP_82XX__
  12
  13 /* System configuration registers.
  14 */
  15 typedef struct sys_conf {
  16         uint    sc_siumcr;
  17         uint    sc_sypcr;
  18         char    res1[6];
  19         ushort  sc_swsr;
  20         char    res2[20];
  21         uint    sc_bcr;
  22         u_char  sc_ppc_acr;
  23         char    res3[3];
  24         uint    sc_ppc_alrh;
  25         uint    sc_ppc_alrl;
  26         u_char  sc_lcl_acr;
  27         char    res4[3];
  28         uint    sc_lcl_alrh;
  29         uint    sc_lcl_alrl;
  30         uint    sc_tescr1;
  31         uint    sc_tescr2;
  32         uint    sc_ltescr1;
  33         uint    sc_ltescr2;
  34         uint    sc_pdtea;
  35         u_char  sc_pdtem;
  36         char    res5[3];
  37         uint    sc_ldtea;
  38         u_char  sc_ldtem;
  39         char    res6[163];
  40 } sysconf8260_t;
  41
  42
  43 /* Memory controller registers.
  44 */
  45 typedef struct  mem_ctlr {
  46         uint    memc_br0;
  47         uint    memc_or0;
  48         uint    memc_br1;
  49         uint    memc_or1;
  50         uint    memc_br2;
  51         uint    memc_or2;
  52         uint    memc_br3;
  53         uint    memc_or3;
  54         uint    memc_br4;
  55         uint    memc_or4;
  56         uint    memc_br5;
  57         uint    memc_or5;
  58         uint    memc_br6;
  59         uint    memc_or6;
  60         uint    memc_br7;
  61         uint    memc_or7;
  62         uint    memc_br8;
  63         uint    memc_or8;
  64         uint    memc_br9;
  65         uint    memc_or9;
  66         uint    memc_br10;
  67         uint    memc_or10;
  68         uint    memc_br11;
  69         uint    memc_or11;
  70         char    res1[8];
  71         uint    memc_mar;
  72         char    res2[4];
  73         uint    memc_mamr;
  74         uint    memc_mbmr;
  75         uint    memc_mcmr;
  76         char    res3[8];
  77         ushort  memc_mptpr;
  78         char    res4[2];
  79         uint    memc_mdr;
  80         char    res5[4];
  81         uint    memc_psdmr;
  82         uint    memc_lsdmr;
  83         u_char  memc_purt;
  84         char    res6[3];
  85         u_char  memc_psrt;
  86         char    res7[3];
  87         u_char  memc_lurt;
  88         char    res8[3];
  89         u_char  memc_lsrt;
  90         char    res9[3];
  91         uint    memc_immr;
  92         char    res10[84];
  93 } memctl8260_t;
  94
  95 /* System Integration Timers.
  96 */
  97 typedef struct  sys_int_timers {
  98         char    res1[32];
  99         ushort  sit_tmcntsc;
 100         char    res2[2];
 101         uint    sit_tmcnt;
 102         char    res3[4];
 103         uint    sit_tmcntal;
 104         char    res4[16];
 105         ushort  sit_piscr;
 106         char    res5[2];
 107         uint    sit_pitc;
 108         uint    sit_pitr;
 109         char    res6[94];
 110         char    res7[2390];
 111 } sit8260_t;
 112
 113 #define PISCR_PIRQ_MASK         ((ushort)0xff00)
 114 #define PISCR_PS                ((ushort)0x0080)
 115 #define PISCR_PIE               ((ushort)0x0004)
 116 #define PISCR_PTF               ((ushort)0x0002)
 117 #define PISCR_PTE               ((ushort)0x0001)
 118
 119 /* Interrupt Controller.
 120 */
 121 typedef struct interrupt_controller {
 122         ushort  ic_sicr;
 123         char    res1[2];
 124         uint    ic_sivec;
 125         uint    ic_sipnrh;
 126         uint    ic_sipnrl;
 127         uint    ic_siprr;
 128         uint    ic_scprrh;
 129         uint    ic_scprrl;
 130         uint    ic_simrh;
 131         uint    ic_simrl;
 132         uint    ic_siexr;
 133         char    res2[88];
 134 } intctl8260_t;
 135
 136 /* Clocks and Reset.
 137 */
 138 typedef struct clk_and_reset {
 139         uint    car_sccr;
 140         char    res1[4];
 141         uint    car_scmr;
 142         char    res2[4];
 143         uint    car_rsr;
 144         uint    car_rmr;
 145         char    res[104];
 146 } car8260_t;
 147
 148 /* Input/Output Port control/status registers.
 149  * Names consistent with processor manual, although they are different
 150  * from the original 8xx names.......
 151  */
 152 typedef struct io_port {
 153         uint    iop_pdira;
 154         uint    iop_ppara;
 155         uint    iop_psora;
 156         uint    iop_podra;
 157         uint    iop_pdata;
 158         char    res1[12];
 159         uint    iop_pdirb;
 160         uint    iop_pparb;
 161         uint    iop_psorb;
 162         uint    iop_podrb;
 163         uint    iop_pdatb;
 164         char    res2[12];
 165         uint    iop_pdirc;
 166         uint    iop_pparc;
 167         uint    iop_psorc;
 168         uint    iop_podrc;
 169         uint    iop_pdatc;
 170         char    res3[12];
 171         uint    iop_pdird;
 172         uint    iop_ppard;
 173         uint    iop_psord;
 174         uint    iop_podrd;
 175         uint    iop_pdatd;
 176         char    res4[12];
 177 } iop8260_t;
 178
 179 /* Communication Processor Module Timers
 180 */
 181 typedef struct cpm_timers {
 182         u_char  cpmt_tgcr1;
 183         char    res1[3];
 184         u_char  cpmt_tgcr2;
 185         char    res2[11];
 186         ushort  cpmt_tmr1;
 187         ushort  cpmt_tmr2;
 188         ushort  cpmt_trr1;
 189         ushort  cpmt_trr2;
 190         ushort  cpmt_tcr1;
 191         ushort  cpmt_tcr2;
 192         ushort  cpmt_tcn1;
 193         ushort  cpmt_tcn2;
 194         ushort  cpmt_tmr3;
 195         ushort  cpmt_tmr4;
 196         ushort  cpmt_trr3;
 197         ushort  cpmt_trr4;
 198         ushort  cpmt_tcr3;
 199         ushort  cpmt_tcr4;
 200         ushort  cpmt_tcn3;
 201         ushort  cpmt_tcn4;
 202         ushort  cpmt_ter1;
 203         ushort  cpmt_ter2;
 204         ushort  cpmt_ter3;
 205         ushort  cpmt_ter4;
 206         char    res3[584];
 207 } cpmtimer8260_t;
 208
 209 /* DMA control/status registers.
 210 */
 211 typedef struct sdma_csr {
 212         char    res0[24];
 213         u_char  sdma_sdsr;
 214         char    res1[3];
 215         u_char  sdma_sdmr;
 216         char    res2[3];
 217         u_char  sdma_idsr1;
 218         char    res3[3];
 219         u_char  sdma_idmr1;
 220         char    res4[3];
 221         u_char  sdma_idsr2;
 222         char    res5[3];
 223         u_char  sdma_idmr2;
 224         char    res6[3];
 225         u_char  sdma_idsr3;
 226         char    res7[3];
 227         u_char  sdma_idmr3;
 228         char    res8[3];
 229         u_char  sdma_idsr4;
 230         char    res9[3];
 231         u_char  sdma_idmr4;
 232         char    res10[707];
 233 } sdma8260_t;
 234
 235 /* Fast controllers
 236 */
 237 typedef struct fcc {
 238         uint    fcc_gfmr;
 239         uint    fcc_fpsmr;
 240         ushort  fcc_ftodr;
 241         char    res1[2];
 242         ushort  fcc_fdsr;
 243         char    res2[2];
 244         uint    fcc_fcce;
 245         uint    fcc_fccm;
 246         u_char  fcc_fccs;
 247         char    res3[3];
 248         u_char  fcc_ftirr_phy[4];
 249 } fcc_t;
 250
 251 /* I2C
 252 */
 253 typedef struct i2c {
 254         u_char  i2c_i2mod;
 255         char    res1[3];
 256         u_char  i2c_i2add;
 257         char    res2[3];
 258         u_char  i2c_i2brg;
 259         char    res3[3];
 260         u_char  i2c_i2com;
 261         char    res4[3];
 262         u_char  i2c_i2cer;
 263         char    res5[3];
 264         u_char  i2c_i2cmr;
 265         char    res6[331];
 266 } i2c8260_t;
 267
 268 typedef struct scc {            /* Serial communication channels */
 269         uint    scc_gsmrl;
 270         uint    scc_gsmrh;
 271         ushort  scc_pmsr;
 272         char    res1[2];
 273         ushort  scc_todr;
 274         ushort  scc_dsr;
 275         ushort  scc_scce;
 276         char    res2[2];
 277         ushort  scc_sccm;
 278         char    res3;
 279         u_char  scc_sccs;
 280         char    res4[8];
 281 } scc_t;
 282
 283 typedef struct smc {            /* Serial management channels */
 284         char    res1[2];
 285         ushort  smc_smcmr;
 286         char    res2[2];
 287         u_char  smc_smce;
 288         char    res3[3];
 289         u_char  smc_smcm;
 290         char    res4[5];
 291 } smc_t;
 292
 293 /* Serial Peripheral Interface.
 294 */
 295 typedef struct spi {
 296         ushort  spi_spmode;
 297         char    res1[4];
 298         u_char  spi_spie;
 299         char    res2[3];
 300         u_char  spi_spim;
 301         char    res3[2];
 302         u_char  spi_spcom;
 303         char    res4[82];
 304 } spi_t;
 305
 306 /* CPM Mux.
 307 */
 308 typedef struct cpmux {
 309         u_char  cmx_si1cr;
 310         char    res1;
 311         u_char  cmx_si2cr;
 312         char    res2;
 313         uint    cmx_fcr;
 314         uint    cmx_scr;
 315         u_char  cmx_smr;
 316         char    res3;
 317         ushort  cmx_uar;
 318         char    res4[16];
 319 } cpmux_t;
 320
 321 /* SIRAM control
 322 */
 323 typedef struct siram {
 324         ushort  si_amr;
 325         ushort  si_bmr;
 326         ushort  si_cmr;
 327         ushort  si_dmr;
 328         u_char  si_gmr;
 329         char    res1;
 330         u_char  si_cmdr;
 331         char    res2;
 332         u_char  si_str;
 333         char    res3;
 334         ushort  si_rsr;
 335 } siramctl_t;
 336
 337 typedef struct mcc {
 338         ushort  mcc_mcce;
 339         char    res1[2];
 340         ushort  mcc_mccm;
 341         char    res2[2];
 342         u_char  mcc_mccf;
 343         char    res3[7];
 344 } mcc_t;
 345
 346 typedef struct comm_proc {
 347         uint    cp_cpcr;
 348         uint    cp_rccr;
 349         char    res1[14];
 350         ushort  cp_rter;
 351         char    res2[2];
 352         ushort  cp_rtmr;
 353         ushort  cp_rtscr;
 354         char    res3[2];
 355         uint    cp_rtsr;
 356         char    res4[12];
 357 } cpm8260_t;
 358
 359 /* ...and the whole thing wrapped up....
 360 */
 361 typedef struct immap {
 362         /* Some references are into the unique and known dpram spaces,
 363          * others are from the generic base.
 364          */
 365 #define im_dprambase    im_dpram1
 366         u_char          im_dpram1[16*1024];
 367         char            res1[16*1024];
 368         u_char          im_dpram2[4*1024];
 369         char            res2[8*1024];
 370         u_char          im_dpram3[4*1024];
 371         char            res3[16*1024];
 372
 373         sysconf8260_t   im_siu_conf;    /* SIU Configuration */
 374         memctl8260_t    im_memctl;      /* Memory Controller */
 375         sit8260_t       im_sit;         /* System Integration Timers */
 376         intctl8260_t    im_intctl;      /* Interrupt Controller */
 377         car8260_t       im_clkrst;      /* Clocks and reset */
 378         iop8260_t       im_ioport;      /* IO Port control/status */
 379         cpmtimer8260_t  im_cpmtimer;    /* CPM timers */
 380         sdma8260_t      im_sdma;        /* SDMA control/status */
 381
 382         fcc_t           im_fcc[3];      /* Three FCCs */
 383
 384         char            res4[159];
 385
 386         /* First set of baud rate generators.
 387         */
 388         char            res4a[496];
 389         uint            im_brgc5;
 390         uint            im_brgc6;
 391         uint            im_brgc7;
 392         uint            im_brgc8;
 393
 394         char            res5[608];
 395
 396         i2c8260_t       im_i2c;         /* I2C control/status */
 397         cpm8260_t       im_cpm;         /* Communication processor */
 398
 399         /* Second set of baud rate generators.
 400         */
 401         uint            im_brgc1;
 402         uint            im_brgc2;
 403         uint            im_brgc3;
 404         uint            im_brgc4;
 405
 406         scc_t           im_scc[4];      /* Four SCCs */
 407         smc_t           im_smc[2];      /* Couple of SMCs */
 408         spi_t           im_spi;         /* A SPI */
 409         cpmux_t         im_cpmux;       /* CPM clock route mux */
 410         siramctl_t      im_siramctl1;   /* First SI RAM Control */
 411         mcc_t           im_mcc1;        /* First MCC */
 412         siramctl_t      im_siramctl2;   /* Second SI RAM Control */
 413         mcc_t           im_mcc2;        /* Second MCC */
 414
 415         char            res6[1184];
 416
 417         ushort          im_si1txram[256];
 418         char            res7[512];
 419         ushort          im_si1rxram[256];
 420         char            res8[512];
 421         ushort          im_si2txram[256];
 422         char            res9[512];
 423         ushort          im_si2rxram[256];
 424         char            res10[512];
 425         char            res11[4096];
 426 } immap_t;
 427
 428 /* The 8260 relies heavily on the IMMR, so we keep it around as a
 429  * kernel global symbol now.  Should have done this for the 8xx......
 430  */
 431 immap_t *immr;
 432
 433 #endif /* __IMMAP_82XX__ */