include/asm-ppc/dma.h

   1 /* $Id: dma.h,v 1.3 1997/03/16 06:20:39 cort Exp $
   2  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   3  * Written by Hennus Bergman, 1992.
   4  * High DMA channel support & info by Hannu Savolainen
   5  * and John Boyd, Nov. 1992.
   6  * Changes for ppc sound by Christoph Nadig
   7  */
   8
   9 #include <linux/config.h>
  10 #include <asm/io.h>
  11 #include <linux/spinlock.h>
  12 #include <asm/system.h>
  13
  14 /*
  15  * Note: Adapted for PowerPC by Gary Thomas
  16  * Modified by Cort Dougan <cort@cs.nmt.edu>
  17  *
  18  * None of this really applies for Power Macintoshes.  There is
  19  * basically just enough here to get kernel/dma.c to compile.
  20  *
  21  * There may be some comments or restrictions made here which are
  22  * not valid for the PReP platform.  Take what you read
  23  * with a grain of salt.
  24  */
  25
  26
  27 #ifndef _ASM_DMA_H
  28 #define _ASM_DMA_H
  29
  30 #ifndef MAX_DMA_CHANNELS
  31 #define MAX_DMA_CHANNELS        8
  32 #endif
  33
  34 /* The maximum address that we can perform a DMA transfer to on this platform */
  35 /* Doesn't really apply... */
  36 #define MAX_DMA_ADDRESS      0xFFFFFFFF
  37
  38 /* in arch/ppc/kernel/setup.c -- Cort */
  39 extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
  40 extern unsigned long ISA_DMA_THRESHOLD;
  41
  42
  43 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  44 #define dma_outb        outb_p
  45 #else
  46 #define dma_outb        outb
  47 #endif
  48
  49 #define dma_inb         inb
  50
  51 /*
  52  * NOTES about DMA transfers:
  53  *
  54  *  controller 1: channels 0-3, byte operations, ports 00-1F
  55  *  controller 2: channels 4-7, word operations, ports C0-DF
  56  *
  57  *  - ALL registers are 8 bits only, regardless of transfer size
  58  *  - channel 4 is not used - cascades 1 into 2.
  59  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  60  *  - channels 5-7 are word - addresses/counts are for physical words
  61  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  62  *  - transfer count loaded to registers is 1 less than actual count
  63  *  - controller 2 offsets are all even (2x offsets for controller 1)
  64  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  65  *  - page registers for 0-3 use bit 0, represent 64K pages
  66  *
  67  * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
  68  * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
  69  * Note that addresses loaded into registers must be _physical_ addresses,
  70  * not logical addresses (which may differ if paging is active).
  71  *
  72  *  Address mapping for channels 0-3:
  73  *
  74  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  75  *    |  ...  |   |  ... |   |  ... |
  76  *    |  ...  |   |  ... |   |  ... |
  77  *    |  ...  |   |  ... |   |  ... |
  78  *   P7  ...  P0  A7 ... A0  A7 ... A0
  79  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  80  *
  81  *  Address mapping for channels 5-7:
  82  *
  83  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  84  *    |  ...  |   \   \   ... \  \  \  ... \  \
  85  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  86  *    |  ...  |     \   \   ... \  \  \  ... \
  87  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  88  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  89  *
  90  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  91  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  92  * the hardware level, so odd-byte transfers aren't possible).
  93  *
  94  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  95  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  96  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  97  *
  98  */
  99
 100 /* used in nasty hack for sound - see prep_setup_arch() -- Cort */
 101 extern long ppc_cs4232_dma, ppc_cs4232_dma2;
 102 #if defined(CONFIG_CS4232)
 103 #if defined(CONFIG_PREP) || defined(CONFIG_ALL_PPC)
 104 #define SND_DMA1 ppc_cs4232_dma
 105 #define SND_DMA2 ppc_cs4232_dma2
 106 #else /* !CONFIG_PREP && !CONFIG_ALL_PPC */
 107 #define SND_DMA1 -1
 108 #define SND_DMA2 -1
 109 #endif /* !CONFIG_PREP */
 110 #elif defined(CONFIG_MSS)
 111 #define SND_DMA1 CONFIG_MSS_DMA
 112 #define SND_DMA2 CONFIG_MSS_DMA2
 113 #else
 114 #define SND_DMA1 -1
 115 #define SND_DMA2 -1
 116 #endif
 117
 118 /* 8237 DMA controllers */
 119 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
 120 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
 121
 122 /* DMA controller registers */
 123 #define DMA1_CMD_REG            0x08    /* command register (w) */
 124 #define DMA1_STAT_REG           0x08    /* status register (r) */
 125 #define DMA1_REQ_REG            0x09    /* request register (w) */
 126 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
 127 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
 128 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
 129 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
 130 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
 131 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
 132 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 133
 134 #define DMA2_CMD_REG            0xD0    /* command register (w) */
 135 #define DMA2_STAT_REG           0xD0    /* status register (r) */
 136 #define DMA2_REQ_REG            0xD2    /* request register (w) */
 137 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 138 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
 139 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 140 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 141 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 142 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 143 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 144
 145 #define DMA_ADDR_0              0x00    /* DMA address registers */
 146 #define DMA_ADDR_1              0x02
 147 #define DMA_ADDR_2              0x04
 148 #define DMA_ADDR_3              0x06
 149 #define DMA_ADDR_4              0xC0
 150 #define DMA_ADDR_5              0xC4
 151 #define DMA_ADDR_6              0xC8
 152 #define DMA_ADDR_7              0xCC
 153
 154 #define DMA_CNT_0               0x01    /* DMA count registers */
 155 #define DMA_CNT_1               0x03
 156 #define DMA_CNT_2               0x05
 157 #define DMA_CNT_3               0x07
 158 #define DMA_CNT_4               0xC2
 159 #define DMA_CNT_5               0xC6
 160 #define DMA_CNT_6               0xCA
 161 #define DMA_CNT_7               0xCE
 162
 163 #define DMA_LO_PAGE_0              0x87    /* DMA page registers */
 164 #define DMA_LO_PAGE_1              0x83
 165 #define DMA_LO_PAGE_2              0x81
 166 #define DMA_LO_PAGE_3              0x82
 167 #define DMA_LO_PAGE_5              0x8B
 168 #define DMA_LO_PAGE_6              0x89
 169 #define DMA_LO_PAGE_7              0x8A
 170
 171 #define DMA_HI_PAGE_0              0x487    /* DMA page registers */
 172 #define DMA_HI_PAGE_1              0x483
 173 #define DMA_HI_PAGE_2              0x481
 174 #define DMA_HI_PAGE_3              0x482
 175 #define DMA_HI_PAGE_5              0x48B
 176 #define DMA_HI_PAGE_6              0x489
 177 #define DMA_HI_PAGE_7              0x48A
 178
 179 #define DMA1_EXT_REG               0x40B
 180 #define DMA2_EXT_REG               0x4D6
 181
 182 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 183 #define DMA_AUTOINIT     0x10
 184
 185 extern spinlock_t  dma_spin_lock;
 186
 187 static __inline__ unsigned long claim_dma_lock(void)
 188 {
 189         unsigned long flags;
 190         spin_lock_irqsave(&dma_spin_lock, flags);
 191         return flags;
 192 }
 193
 194 static __inline__ void release_dma_lock(unsigned long flags)
 195 {
 196         spin_unlock_irqrestore(&dma_spin_lock, flags);
 197 }
 198
 199 /* enable/disable a specific DMA channel */
 200 static __inline__ void enable_dma(unsigned int dmanr)
 201 {
 202         /*
 203          * The Radstone PPC2 and PPC2a boards have inverted DREQ
 204          * lines (active low) so each command needs to be logically
 205          * ORed with 0x40
 206          */
 207         unsigned char ucDmaCmd=0x00;
 208
 209 #if defined(CONFIG_PREP) || defined(CONFIG_ALL_PPC)
 210         if(_prep_type==_PREP_Radstone)
 211         {
 212                 switch(ucSystemType)
 213                 {
 214                         case RS_SYS_TYPE_PPC2:
 215                         case RS_SYS_TYPE_PPC2a:
 216                         case RS_SYS_TYPE_PPC2ep:
 217                         {
 218                                 /*
 219                                  * DREQ lines are active low
 220                                  */
 221                                 ucDmaCmd=0x40;
 222                                 break;
 223                         }
 224
 225                         default:
 226                         {
 227                                 /*
 228                                  * DREQ lines are active high
 229                                  */
 230                                 break;
 231                         }
 232                 }
 233         }
 234 #endif /* CONFIG_PREP || CONFIG_ALL_PPC */
 235
 236         if (dmanr != 4)
 237         {
 238                 dma_outb(0, DMA2_MASK_REG);  /* This may not be enabled */
 239                 dma_outb(ucDmaCmd, DMA2_CMD_REG);  /* Enable group */
 240         }
 241         if (dmanr<=3)
 242         {
 243                 dma_outb(dmanr,  DMA1_MASK_REG);
 244                 dma_outb(ucDmaCmd, DMA1_CMD_REG);  /* Enable group */
 245         } else
 246         {
 247                 dma_outb(dmanr & 3,  DMA2_MASK_REG);
 248         }
 249 }
 250
 251 static __inline__ void disable_dma(unsigned int dmanr)
 252 {
 253         if (dmanr<=3)
 254                 dma_outb(dmanr | 4,  DMA1_MASK_REG);
 255         else
 256                 dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 257 }
 258
 259 /* Clear the 'DMA Pointer Flip Flop'.
 260  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 261  * Use this once to initialize the FF to a known state.
 262  * After that, keep track of it. :-)
 263  * --- In order to do that, the DMA routines below should ---
 264  * --- only be used while interrupts are disabled! ---
 265  */
 266 static __inline__ void clear_dma_ff(unsigned int dmanr)
 267 {
 268         if (dmanr<=3)
 269                 dma_outb(0,  DMA1_CLEAR_FF_REG);
 270         else
 271                 dma_outb(0,  DMA2_CLEAR_FF_REG);
 272 }
 273
 274 /* set mode (above) for a specific DMA channel */
 275 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 276 {
 277         if (dmanr<=3)
 278                 dma_outb(mode | dmanr,  DMA1_MODE_REG);
 279         else
 280                 dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 281 }
 282
 283 /* Set only the page register bits of the transfer address.
 284  * This is used for successive transfers when we know the contents of
 285  * the lower 16 bits of the DMA current address register, but a 64k boundary
 286  * may have been crossed.
 287  */
 288 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
 289 {
 290         switch(dmanr) {
 291                 case 0:
 292                         dma_outb(pagenr, DMA_LO_PAGE_0);
 293                         dma_outb(pagenr>>8, DMA_HI_PAGE_0);
 294                         break;
 295                 case 1:
 296                         dma_outb(pagenr, DMA_LO_PAGE_1);
 297                         dma_outb(pagenr>>8, DMA_HI_PAGE_1);
 298                         break;
 299                 case 2:
 300                         dma_outb(pagenr, DMA_LO_PAGE_2);
 301                         dma_outb(pagenr>>8, DMA_HI_PAGE_2);
 302                         break;
 303                 case 3:
 304                         dma_outb(pagenr, DMA_LO_PAGE_3);
 305                         dma_outb(pagenr>>8, DMA_HI_PAGE_3);
 306                         break;
 307                 case 5:
 308                         if (SND_DMA1 == 5 || SND_DMA2 == 5)
 309                                 dma_outb(pagenr, DMA_LO_PAGE_5);
 310                         else
 311                                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
 312                         dma_outb(pagenr>>8, DMA_HI_PAGE_5);
 313                         break;
 314                 case 6:
 315                         if (SND_DMA1 == 6 || SND_DMA2 == 6)
 316                                 dma_outb(pagenr, DMA_LO_PAGE_6);
 317                         else
 318                                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
 319                         dma_outb(pagenr>>8, DMA_HI_PAGE_6);
 320                         break;
 321                 case 7:
 322                         if (SND_DMA1 == 7 || SND_DMA2 == 7)
 323                                 dma_outb(pagenr, DMA_LO_PAGE_7);
 324                         else
 325                                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
 326                         dma_outb(pagenr>>8, DMA_HI_PAGE_7);
 327                   break;
 328         }
 329 }
 330
 331
 332 /* Set transfer address & page bits for specific DMA channel.
 333  * Assumes dma flipflop is clear.
 334  */
 335 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
 336 {
 337         if (dmanr <= 3)  {
 338             dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 339             dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 340         }  else  {
 341           if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
 342             dma_outb( phys  & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 343             dma_outb( (phys>>8)  & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 344             dma_outb( (dmanr&3), DMA2_EXT_REG);
 345           } else {
 346             dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 347             dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 348           }
 349         }
 350         set_dma_page(dmanr, phys>>16);
 351 }
 352
 353
 354 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 355  * a specific DMA channel.
 356  * You must ensure the parameters are valid.
 357  * NOTE: from a manual: "the number of transfers is one more
 358  * than the initial word count"! This is taken into account.
 359  * Assumes dma flip-flop is clear.
 360  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 361  */
 362 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 363 {
 364         count--;
 365         if (dmanr <= 3)  {
 366             dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 367             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 368         } else {
 369           if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
 370             dma_outb( count & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 371             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 372           } else {
 373             dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 374             dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 375           }
 376         }
 377 }
 378
 379
 380 /* Get DMA residue count. After a DMA transfer, this
 381  * should return zero. Reading this while a DMA transfer is
 382  * still in progress will return unpredictable results.
 383  * If called before the channel has been used, it may return 1.
 384  * Otherwise, it returns the number of _bytes_ left to transfer.
 385  *
 386  * Assumes DMA flip-flop is clear.
 387  */
 388 static __inline__ int get_dma_residue(unsigned int dmanr)
 389 {
 390         unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 391                                          : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 392
 393         /* using short to get 16-bit wrap around */
 394         unsigned short count;
 395
 396         count = 1 + dma_inb(io_port);
 397         count += dma_inb(io_port) << 8;
 398
 399         return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
 400           ? count : (count<<1);
 401 }
 402
 403 /* These are in kernel/dma.c: */
 404 extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 405 extern void free_dma(unsigned int dmanr);       /* release it again */
 406
 407 #ifdef CONFIG_PCI
 408 extern int isa_dma_bridge_buggy;
 409 #else
 410 #define isa_dma_bridge_buggy   (0)
 411 #endif
 412 #endif /* _ASM_DMA_H */