Optimize andes_clear_page() and andes_copy_page() with prefetch
[linux-2.6/linux-mips.git] / include / asm-ppc / dbdma.h
blob38cd15803b51d1ff40b691d3723e500ae3898d5f
1 /*
2 * Definitions for using the Apple Descriptor-Based DMA controller
3 * in Power Macintosh computers.
5 * Copyright (C) 1996 Paul Mackerras.
6 */
8 #ifndef _ASM_DBDMA_H_
9 #define _ASM_DBDMA_H_
11 * DBDMA control/status registers. All little-endian.
13 struct dbdma_regs {
14 unsigned int control; /* lets you change bits in status */
15 unsigned int status; /* DMA and device status bits (see below) */
16 unsigned int cmdptr_hi; /* upper 32 bits of command address */
17 unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */
18 unsigned int intr_sel; /* select interrupt condition bit */
19 unsigned int br_sel; /* select branch condition bit */
20 unsigned int wait_sel; /* select wait condition bit */
21 unsigned int xfer_mode;
22 unsigned int data2ptr_hi;
23 unsigned int data2ptr;
24 unsigned int res1;
25 unsigned int address_hi;
26 unsigned int br_addr_hi;
27 unsigned int res2[3];
30 /* Bits in control and status registers */
31 #define RUN 0x8000
32 #define PAUSE 0x4000
33 #define FLUSH 0x2000
34 #define WAKE 0x1000
35 #define DEAD 0x0800
36 #define ACTIVE 0x0400
37 #define BT 0x0100
38 #define DEVSTAT 0x00ff
41 * DBDMA command structure. These fields are all little-endian!
43 struct dbdma_cmd {
44 unsigned short req_count; /* requested byte transfer count */
45 unsigned short command; /* command word (has bit-fields) */
46 unsigned int phy_addr; /* physical data address */
47 unsigned int cmd_dep; /* command-dependent field */
48 unsigned short res_count; /* residual count after completion */
49 unsigned short xfer_status; /* transfer status */
52 /* DBDMA command values in command field */
53 #define OUTPUT_MORE 0 /* transfer memory data to stream */
54 #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
55 #define INPUT_MORE 0x2000 /* transfer stream data to memory */
56 #define INPUT_LAST 0x3000 /* ditto, expect end marker */
57 #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
58 #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
59 #define DBDMA_NOP 0x6000 /* do nothing */
60 #define DBDMA_STOP 0x7000 /* suspend processing */
62 /* Key values in command field */
63 #define KEY_STREAM0 0 /* usual data stream */
64 #define KEY_STREAM1 0x100 /* control/status stream */
65 #define KEY_STREAM2 0x200 /* device-dependent stream */
66 #define KEY_STREAM3 0x300 /* device-dependent stream */
67 #define KEY_REGS 0x500 /* device register space */
68 #define KEY_SYSTEM 0x600 /* system memory-mapped space */
69 #define KEY_DEVICE 0x700 /* device memory-mapped space */
71 /* Interrupt control values in command field */
72 #define INTR_NEVER 0 /* don't interrupt */
73 #define INTR_IFSET 0x10 /* intr if condition bit is 1 */
74 #define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
75 #define INTR_ALWAYS 0x30 /* always interrupt */
77 /* Branch control values in command field */
78 #define BR_NEVER 0 /* don't branch */
79 #define BR_IFSET 0x4 /* branch if condition bit is 1 */
80 #define BR_IFCLR 0x8 /* branch if condition bit is 0 */
81 #define BR_ALWAYS 0xc /* always branch */
83 /* Wait control values in command field */
84 #define WAIT_NEVER 0 /* don't wait */
85 #define WAIT_IFSET 1 /* wait if condition bit is 1 */
86 #define WAIT_IFCLR 2 /* wait if condition bit is 0 */
87 #define WAIT_ALWAYS 3 /* always wait */
89 /* Align an address for a DBDMA command structure */
90 #define DBDMA_ALIGN(x) (((unsigned)(x) + sizeof(struct dbdma_cmd) - 1) \
91 & -sizeof(struct dbdma_cmd))
92 #endif /* _ASM_DBDMA_H_ */