include/asm-mips/sni.h

   1 /* $Id: sni.h,v 1.2 1998/09/19 19:19:39 ralf Exp $
   2  *
   3  * SNI specific definitions
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file "COPYING" in the main directory of this archive
   7  * for more details.
   8  *
   9  * Copyright (C) 1997, 1998 by Ralf Baechle
  10  */
  11 #ifndef __ASM_MIPS_SNI_H
  12 #define __ASM_MIPS_SNI_H
  13
  14 #define SNI_PORT_BASE   0xb4000000
  15
  16 /*
  17  * ASIC PCI registers for little endian configuration.
  18  */
  19 #ifndef __MIPSEL__
  20 #error "Fix me for big endian"
  21 #endif
  22 #define PCIMT_UCONF             0xbfff0000
  23 #define PCIMT_IOADTIMEOUT2      0xbfff0008
  24 #define PCIMT_IOMEMCONF         0xbfff0010
  25 #define PCIMT_IOMMU             0xbfff0018
  26 #define PCIMT_IOADTIMEOUT1      0xbfff0020
  27 #define PCIMT_DMAACCESS         0xbfff0028
  28 #define PCIMT_DMAHIT            0xbfff0030
  29 #define PCIMT_ERRSTATUS         0xbfff0038
  30 #define PCIMT_ERRADDR           0xbfff0040
  31 #define PCIMT_SYNDROME          0xbfff0048
  32 #define PCIMT_ITPEND            0xbfff0050
  33 #define PCIMT_IRQSEL            0xbfff0058
  34 #define PCIMT_TESTMEM           0xbfff0060
  35 #define PCIMT_ECCREG            0xbfff0068
  36 #define PCIMT_CONFIG_ADDRESS    0xbfff0070
  37 #define PCIMT_ASIC_ID           0xbfff0078      /* read */
  38 #define PCIMT_SOFT_RESET        0xbfff0078      /* write */
  39 #define PCIMT_PIA_OE            0xbfff0080
  40 #define PCIMT_PIA_DATAOUT       0xbfff0088
  41 #define PCIMT_PIA_DATAIN        0xbfff0090
  42 #define PCIMT_CACHECONF         0xbfff0098
  43 #define PCIMT_INVSPACE          0xbfff00a0
  44 #define PCIMT_PCI_CONF          0xbfff0100
  45
  46 /*
  47  * Data port for the PCI bus.
  48  */
  49 #define PCIMT_CONFIG_DATA       0xb4000cfc
  50
  51 /*
  52  * Board specific registers
  53  */
  54 #define PCIMT_CSMSR             0xbfd00000
  55 #define PCIMT_CSSWITCH          0xbfd10000
  56 #define PCIMT_CSITPEND          0xbfd20000
  57 #define PCIMT_AUTO_PO_EN        0xbfd30000
  58 #define PCIMT_CLR_TEMP          0xbfd40000
  59 #define PCIMT_AUTO_PO_DIS       0xbfd50000
  60 #define PCIMT_EXMSR             0xbfd60000
  61 #define PCIMT_UNUSED1           0xbfd70000
  62 #define PCIMT_CSWCSM            0xbfd80000
  63 #define PCIMT_UNUSED2           0xbfd90000
  64 #define PCIMT_CSLED             0xbfda0000
  65 #define PCIMT_CSMAPISA          0xbfdb0000
  66 #define PCIMT_CSRSTBP           0xbfdc0000
  67 #define PCIMT_CLRPOFF           0xbfdd0000
  68 #define PCIMT_CSTIMER           0xbfde0000
  69 #define PCIMT_PWDN              0xbfdf0000
  70
  71 /*
  72  * Interrupt 0-16 are EISA interrupts.  Interrupts from 16 on are assigned
  73  * to the other interrupts generated by ASIC PCI.
  74  */
  75 #define PCIMT_KEYBOARD_IRQ       1
  76 #define PCIMT_IRQ_ETHERNET      16
  77 #define PCIMT_IRQ_TEMPERATURE   17
  78 #define PCIMT_IRQ_EISA_NMI      18
  79 #define PCIMT_IRQ_POWER_OFF     19
  80 #define PCIMT_IRQ_BUTTON        20
  81 #define PCIMT_IRQ_INTA          21
  82 #define PCIMT_IRQ_INTB          22
  83 #define PCIMT_IRQ_INTC          23
  84 #define PCIMT_IRQ_INTD          24
  85 #define PCIMT_IRQ_SCSI          25
  86
  87 /*
  88  * Base address for the mapped 16mb EISA bus segment.
  89  */
  90 #define PCIMT_EISA_BASE         0xb0000000
  91
  92 /* PCI EISA Interrupt acknowledge  */
  93 #define PCIMT_INT_ACKNOWLEDGE   0xba000000
  94
  95 #endif /* __ASM_MIPS_SNI_H */