MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / arch / sparc / kernel / sun4m_smp.c
blob594768686525a9770b72ea09ef3aef19138ae29d
1 /*
2 * sun4m SMP support.
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 */
7 #include <linux/interrupt.h>
8 #include <linux/profile.h>
9 #include <linux/delay.h>
10 #include <linux/cpu.h>
12 #include <asm/cacheflush.h>
13 #include <asm/tlbflush.h>
15 #include "irq.h"
16 #include "kernel.h"
18 #define IRQ_IPI_SINGLE 12
19 #define IRQ_IPI_MASK 13
20 #define IRQ_IPI_RESCHED 14
21 #define IRQ_CROSS_CALL 15
23 static inline unsigned long
24 swap_ulong(volatile unsigned long *ptr, unsigned long val)
26 __asm__ __volatile__("swap [%1], %0\n\t" :
27 "=&r" (val), "=&r" (ptr) :
28 "0" (val), "1" (ptr));
29 return val;
32 static void smp4m_ipi_init(void);
33 static void smp_setup_percpu_timer(void);
35 void __cpuinit smp4m_callin(void)
37 int cpuid = hard_smp_processor_id();
39 local_flush_cache_all();
40 local_flush_tlb_all();
42 notify_cpu_starting(cpuid);
44 /* Get our local ticker going. */
45 smp_setup_percpu_timer();
47 calibrate_delay();
48 smp_store_cpu_info(cpuid);
50 local_flush_cache_all();
51 local_flush_tlb_all();
54 * Unblock the master CPU _only_ when the scheduler state
55 * of all secondary CPUs will be up-to-date, so after
56 * the SMP initialization the master will be just allowed
57 * to call the scheduler code.
59 /* Allow master to continue. */
60 swap_ulong(&cpu_callin_map[cpuid], 1);
62 /* XXX: What's up with all the flushes? */
63 local_flush_cache_all();
64 local_flush_tlb_all();
66 /* Fix idle thread fields. */
67 __asm__ __volatile__("ld [%0], %%g6\n\t"
68 : : "r" (&current_set[cpuid])
69 : "memory" /* paranoid */);
71 /* Attach to the address space of init_task. */
72 atomic_inc(&init_mm.mm_count);
73 current->active_mm = &init_mm;
75 while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
76 mb();
78 local_irq_enable();
80 set_cpu_online(cpuid, true);
84 * Cycle through the processors asking the PROM to start each one.
86 void __init smp4m_boot_cpus(void)
88 smp4m_ipi_init();
89 smp_setup_percpu_timer();
90 local_flush_cache_all();
93 int __cpuinit smp4m_boot_one_cpu(int i)
95 unsigned long *entry = &sun4m_cpu_startup;
96 struct task_struct *p;
97 int timeout;
98 int cpu_node;
100 cpu_find_by_mid(i, &cpu_node);
102 /* Cook up an idler for this guy. */
103 p = fork_idle(i);
104 current_set[i] = task_thread_info(p);
105 /* See trampoline.S for details... */
106 entry += ((i - 1) * 3);
109 * Initialize the contexts table
110 * Since the call to prom_startcpu() trashes the structure,
111 * we need to re-initialize it for each cpu
113 smp_penguin_ctable.which_io = 0;
114 smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
115 smp_penguin_ctable.reg_size = 0;
117 /* whirrr, whirrr, whirrrrrrrrr... */
118 printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
119 local_flush_cache_all();
120 prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
122 /* wheee... it's going... */
123 for (timeout = 0; timeout < 10000; timeout++) {
124 if (cpu_callin_map[i])
125 break;
126 udelay(200);
129 if (!(cpu_callin_map[i])) {
130 printk(KERN_ERR "Processor %d is stuck.\n", i);
131 return -ENODEV;
134 local_flush_cache_all();
135 return 0;
138 void __init smp4m_smp_done(void)
140 int i, first;
141 int *prev;
143 /* setup cpu list for irq rotation */
144 first = 0;
145 prev = &first;
146 for_each_online_cpu(i) {
147 *prev = i;
148 prev = &cpu_data(i).next;
150 *prev = first;
151 local_flush_cache_all();
153 /* Ok, they are spinning and ready to go. */
157 /* Initialize IPIs on the SUN4M SMP machine */
158 static void __init smp4m_ipi_init(void)
162 static void smp4m_ipi_resched(int cpu)
164 set_cpu_int(cpu, IRQ_IPI_RESCHED);
167 static void smp4m_ipi_single(int cpu)
169 set_cpu_int(cpu, IRQ_IPI_SINGLE);
172 static void smp4m_ipi_mask_one(int cpu)
174 set_cpu_int(cpu, IRQ_IPI_MASK);
177 static struct smp_funcall {
178 smpfunc_t func;
179 unsigned long arg1;
180 unsigned long arg2;
181 unsigned long arg3;
182 unsigned long arg4;
183 unsigned long arg5;
184 unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
185 unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
186 } ccall_info;
188 static DEFINE_SPINLOCK(cross_call_lock);
190 /* Cross calls must be serialized, at least currently. */
191 static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
192 unsigned long arg2, unsigned long arg3,
193 unsigned long arg4)
195 register int ncpus = SUN4M_NCPUS;
196 unsigned long flags;
198 spin_lock_irqsave(&cross_call_lock, flags);
200 /* Init function glue. */
201 ccall_info.func = func;
202 ccall_info.arg1 = arg1;
203 ccall_info.arg2 = arg2;
204 ccall_info.arg3 = arg3;
205 ccall_info.arg4 = arg4;
206 ccall_info.arg5 = 0;
208 /* Init receive/complete mapping, plus fire the IPI's off. */
210 register int i;
212 cpumask_clear_cpu(smp_processor_id(), &mask);
213 cpumask_and(&mask, cpu_online_mask, &mask);
214 for (i = 0; i < ncpus; i++) {
215 if (cpumask_test_cpu(i, &mask)) {
216 ccall_info.processors_in[i] = 0;
217 ccall_info.processors_out[i] = 0;
218 set_cpu_int(i, IRQ_CROSS_CALL);
219 } else {
220 ccall_info.processors_in[i] = 1;
221 ccall_info.processors_out[i] = 1;
227 register int i;
229 i = 0;
230 do {
231 if (!cpumask_test_cpu(i, &mask))
232 continue;
233 while (!ccall_info.processors_in[i])
234 barrier();
235 } while (++i < ncpus);
237 i = 0;
238 do {
239 if (!cpumask_test_cpu(i, &mask))
240 continue;
241 while (!ccall_info.processors_out[i])
242 barrier();
243 } while (++i < ncpus);
245 spin_unlock_irqrestore(&cross_call_lock, flags);
248 /* Running cross calls. */
249 void smp4m_cross_call_irq(void)
251 int i = smp_processor_id();
253 ccall_info.processors_in[i] = 1;
254 ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
255 ccall_info.arg4, ccall_info.arg5);
256 ccall_info.processors_out[i] = 1;
259 void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
261 struct pt_regs *old_regs;
262 int cpu = smp_processor_id();
264 old_regs = set_irq_regs(regs);
266 sun4m_clear_profile_irq(cpu);
268 profile_tick(CPU_PROFILING);
270 if (!--prof_counter(cpu)) {
271 int user = user_mode(regs);
273 irq_enter();
274 update_process_times(user);
275 irq_exit();
277 prof_counter(cpu) = prof_multiplier(cpu);
279 set_irq_regs(old_regs);
282 static void __cpuinit smp_setup_percpu_timer(void)
284 int cpu = smp_processor_id();
286 prof_counter(cpu) = prof_multiplier(cpu) = 1;
287 load_profile_irq(cpu, lvl14_resolution);
289 if (cpu == boot_cpu_id)
290 sun4m_unmask_profile_irq();
293 static void __init smp4m_blackbox_id(unsigned *addr)
295 int rd = *addr & 0x3e000000;
296 int rs1 = rd >> 11;
298 addr[0] = 0x81580000 | rd; /* rd %tbr, reg */
299 addr[1] = 0x8130200c | rd | rs1; /* srl reg, 0xc, reg */
300 addr[2] = 0x80082003 | rd | rs1; /* and reg, 3, reg */
303 static void __init smp4m_blackbox_current(unsigned *addr)
305 int rd = *addr & 0x3e000000;
306 int rs1 = rd >> 11;
308 addr[0] = 0x81580000 | rd; /* rd %tbr, reg */
309 addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */
310 addr[4] = 0x8008200c | rd | rs1; /* and reg, 0xc, reg */
313 void __init sun4m_init_smp(void)
315 BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
316 BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
317 BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
318 BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
319 BTFIXUPSET_CALL(smp_ipi_resched, smp4m_ipi_resched, BTFIXUPCALL_NORM);
320 BTFIXUPSET_CALL(smp_ipi_single, smp4m_ipi_single, BTFIXUPCALL_NORM);
321 BTFIXUPSET_CALL(smp_ipi_mask_one, smp4m_ipi_mask_one, BTFIXUPCALL_NORM);