2 * linux/drivers/usb/gadget/pxa2xx_udc.c
3 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6 * Copyright (C) 2003 Robert Schwebel, Pengutronix
7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8 * Copyright (C) 2003 David Brownell
9 * Copyright (C) 2003 Joshua Wise
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 // #define VERBOSE DBG_VERBOSE
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/ioport.h>
33 #include <linux/types.h>
34 #include <linux/errno.h>
35 #include <linux/delay.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/init.h>
39 #include <linux/timer.h>
40 #include <linux/list.h>
41 #include <linux/interrupt.h>
42 #include <linux/proc_fs.h>
44 #include <linux/platform_device.h>
45 #include <linux/dma-mapping.h>
47 #include <asm/byteorder.h>
51 #include <asm/system.h>
52 #include <asm/mach-types.h>
53 #include <asm/unaligned.h>
54 #include <asm/hardware.h>
55 #ifdef CONFIG_ARCH_PXA
56 #include <asm/arch/pxa-regs.h>
59 #include <linux/usb_ch9.h>
60 #include <linux/usb_gadget.h>
62 #include <asm/arch/udc.h>
66 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
67 * series processors. The UDC for the IXP 4xx series is very similar.
68 * There are fifteen endpoints, in addition to ep0.
70 * Such controller drivers work with a gadget driver. The gadget driver
71 * returns descriptors, implements configuration and data protocols used
72 * by the host to interact with this device, and allocates endpoints to
73 * the different protocol interfaces. The controller driver virtualizes
74 * usb hardware so that the gadget drivers will be more portable.
76 * This UDC hardware wants to implement a bit too much USB protocol, so
77 * it constrains the sorts of USB configuration change events that work.
78 * The errata for these chips are misleading; some "fixed" bugs from
79 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
82 #define DRIVER_VERSION "4-May-2005"
83 #define DRIVER_DESC "PXA 25x USB Device Controller driver"
86 static const char driver_name
[] = "pxa2xx_udc";
88 static const char ep0name
[] = "ep0";
92 // #define USE_OUT_DMA
93 // #define DISABLE_TEST_MODE
95 #ifdef CONFIG_ARCH_IXP4XX
98 /* cpu-specific register addresses are compiled in to this code */
99 #ifdef CONFIG_ARCH_PXA
100 #error "Can't configure both IXP and PXA"
105 #include "pxa2xx_udc.h"
109 static int use_dma
= 1;
110 module_param(use_dma
, bool, 0);
111 MODULE_PARM_DESC (use_dma
, "true to use dma");
113 static void dma_nodesc_handler (int dmach
, void *_ep
, struct pt_regs
*r
);
114 static void kick_dma(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
);
117 #define DMASTR " (dma support)"
119 #define DMASTR " (dma in)"
123 #define DMASTR " (pio only)"
127 #ifdef CONFIG_USB_PXA2XX_SMALL
128 #define SIZE_STR " (small)"
133 #ifdef DISABLE_TEST_MODE
134 /* (mode == 0) == no undocumented chip tweaks
135 * (mode & 1) == double buffer bulk IN
136 * (mode & 2) == double buffer bulk OUT
137 * ... so mode = 3 (or 7, 15, etc) does it for both
139 static ushort fifo_mode
= 0;
140 module_param(fifo_mode
, ushort
, 0);
141 MODULE_PARM_DESC (fifo_mode
, "pxa2xx udc fifo mode");
144 /* ---------------------------------------------------------------------------
145 * endpoint related parts of the api to the usb controller hardware,
146 * used by gadget driver; and the inner talker-to-hardware core.
147 * ---------------------------------------------------------------------------
150 static void pxa2xx_ep_fifo_flush (struct usb_ep
*ep
);
151 static void nuke (struct pxa2xx_ep
*, int status
);
153 static void pio_irq_enable(int bEndpointAddress
)
155 bEndpointAddress
&= 0xf;
156 if (bEndpointAddress
< 8)
157 UICR0
&= ~(1 << bEndpointAddress
);
159 bEndpointAddress
-= 8;
160 UICR1
&= ~(1 << bEndpointAddress
);
164 static void pio_irq_disable(int bEndpointAddress
)
166 bEndpointAddress
&= 0xf;
167 if (bEndpointAddress
< 8)
168 UICR0
|= 1 << bEndpointAddress
;
170 bEndpointAddress
-= 8;
171 UICR1
|= 1 << bEndpointAddress
;
175 /* The UDCCR reg contains mask and interrupt status bits,
176 * so using '|=' isn't safe as it may ack an interrupt.
178 #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
180 static inline void udc_set_mask_UDCCR(int mask
)
182 UDCCR
= (UDCCR
& UDCCR_MASK_BITS
) | (mask
& UDCCR_MASK_BITS
);
185 static inline void udc_clear_mask_UDCCR(int mask
)
187 UDCCR
= (UDCCR
& UDCCR_MASK_BITS
) & ~(mask
& UDCCR_MASK_BITS
);
190 static inline void udc_ack_int_UDCCR(int mask
)
192 /* udccr contains the bits we dont want to change */
193 __u32 udccr
= UDCCR
& UDCCR_MASK_BITS
;
195 UDCCR
= udccr
| (mask
& ~UDCCR_MASK_BITS
);
199 * endpoint enable/disable
201 * we need to verify the descriptors used to enable endpoints. since pxa2xx
202 * endpoint configurations are fixed, and are pretty much always enabled,
203 * there's not a lot to manage here.
205 * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
206 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
207 * for a single interface (with only the default altsetting) and for gadget
208 * drivers that don't halt endpoints (not reset by set_interface). that also
209 * means that if you use ISO, you must violate the USB spec rule that all
210 * iso endpoints must be in non-default altsettings.
212 static int pxa2xx_ep_enable (struct usb_ep
*_ep
,
213 const struct usb_endpoint_descriptor
*desc
)
215 struct pxa2xx_ep
*ep
;
216 struct pxa2xx_udc
*dev
;
218 ep
= container_of (_ep
, struct pxa2xx_ep
, ep
);
219 if (!_ep
|| !desc
|| ep
->desc
|| _ep
->name
== ep0name
220 || desc
->bDescriptorType
!= USB_DT_ENDPOINT
221 || ep
->bEndpointAddress
!= desc
->bEndpointAddress
222 || ep
->fifo_size
< le16_to_cpu
223 (desc
->wMaxPacketSize
)) {
224 DMSG("%s, bad ep or descriptor\n", __FUNCTION__
);
228 /* xfer types must match, except that interrupt ~= bulk */
229 if (ep
->bmAttributes
!= desc
->bmAttributes
230 && ep
->bmAttributes
!= USB_ENDPOINT_XFER_BULK
231 && desc
->bmAttributes
!= USB_ENDPOINT_XFER_INT
) {
232 DMSG("%s, %s type mismatch\n", __FUNCTION__
, _ep
->name
);
236 /* hardware _could_ do smaller, but driver doesn't */
237 if ((desc
->bmAttributes
== USB_ENDPOINT_XFER_BULK
238 && le16_to_cpu (desc
->wMaxPacketSize
)
240 || !desc
->wMaxPacketSize
) {
241 DMSG("%s, bad %s maxpacket\n", __FUNCTION__
, _ep
->name
);
246 if (!dev
->driver
|| dev
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
247 DMSG("%s, bogus device state\n", __FUNCTION__
);
254 ep
->pio_irqs
= ep
->dma_irqs
= 0;
255 ep
->ep
.maxpacket
= le16_to_cpu (desc
->wMaxPacketSize
);
257 /* flush fifo (mostly for OUT buffers) */
258 pxa2xx_ep_fifo_flush (_ep
);
260 /* ... reset halt state too, if we could ... */
263 /* for (some) bulk and ISO endpoints, try to get a DMA channel and
264 * bind it to the endpoint. otherwise use PIO.
266 switch (ep
->bmAttributes
) {
267 case USB_ENDPOINT_XFER_ISOC
:
268 if (le16_to_cpu(desc
->wMaxPacketSize
) % 32)
271 case USB_ENDPOINT_XFER_BULK
:
272 if (!use_dma
|| !ep
->reg_drcmr
)
274 ep
->dma
= pxa_request_dma ((char *)_ep
->name
,
275 (le16_to_cpu (desc
->wMaxPacketSize
) > 64)
276 ? DMA_PRIO_MEDIUM
/* some iso */
278 dma_nodesc_handler
, ep
);
280 *ep
->reg_drcmr
= DRCMR_MAPVLD
| ep
->dma
;
281 DMSG("%s using dma%d\n", _ep
->name
, ep
->dma
);
286 DBG(DBG_VERBOSE
, "enabled %s\n", _ep
->name
);
290 static int pxa2xx_ep_disable (struct usb_ep
*_ep
)
292 struct pxa2xx_ep
*ep
;
295 ep
= container_of (_ep
, struct pxa2xx_ep
, ep
);
296 if (!_ep
|| !ep
->desc
) {
297 DMSG("%s, %s not enabled\n", __FUNCTION__
,
298 _ep
? ep
->ep
.name
: NULL
);
301 local_irq_save(flags
);
303 nuke (ep
, -ESHUTDOWN
);
308 pxa_free_dma (ep
->dma
);
313 /* flush fifo (mostly for IN buffers) */
314 pxa2xx_ep_fifo_flush (_ep
);
319 local_irq_restore(flags
);
320 DBG(DBG_VERBOSE
, "%s disabled\n", _ep
->name
);
324 /*-------------------------------------------------------------------------*/
326 /* for the pxa2xx, these can just wrap kmalloc/kfree. gadget drivers
327 * must still pass correctly initialized endpoints, since other controller
328 * drivers may care about how it's currently set up (dma issues etc).
332 * pxa2xx_ep_alloc_request - allocate a request data structure
334 static struct usb_request
*
335 pxa2xx_ep_alloc_request (struct usb_ep
*_ep
, gfp_t gfp_flags
)
337 struct pxa2xx_request
*req
;
339 req
= kzalloc(sizeof(*req
), gfp_flags
);
343 INIT_LIST_HEAD (&req
->queue
);
349 * pxa2xx_ep_free_request - deallocate a request data structure
352 pxa2xx_ep_free_request (struct usb_ep
*_ep
, struct usb_request
*_req
)
354 struct pxa2xx_request
*req
;
356 req
= container_of (_req
, struct pxa2xx_request
, req
);
357 WARN_ON (!list_empty (&req
->queue
));
362 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
363 * no device-affinity and the heap works perfectly well for i/o buffers.
364 * It wastes much less memory than dma_alloc_coherent() would, and even
365 * prevents cacheline (32 bytes wide) sharing problems.
368 pxa2xx_ep_alloc_buffer(struct usb_ep
*_ep
, unsigned bytes
,
369 dma_addr_t
*dma
, gfp_t gfp_flags
)
373 retval
= kmalloc (bytes
, gfp_flags
& ~(__GFP_DMA
|__GFP_HIGHMEM
));
376 *dma
= virt_to_bus (retval
);
378 *dma
= (dma_addr_t
)~0;
384 pxa2xx_ep_free_buffer(struct usb_ep
*_ep
, void *buf
, dma_addr_t dma
,
390 /*-------------------------------------------------------------------------*/
393 * done - retire a request; caller blocked irqs
395 static void done(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
, int status
)
397 unsigned stopped
= ep
->stopped
;
399 list_del_init(&req
->queue
);
401 if (likely (req
->req
.status
== -EINPROGRESS
))
402 req
->req
.status
= status
;
404 status
= req
->req
.status
;
406 if (status
&& status
!= -ESHUTDOWN
)
407 DBG(DBG_VERBOSE
, "complete %s req %p stat %d len %u/%u\n",
408 ep
->ep
.name
, &req
->req
, status
,
409 req
->req
.actual
, req
->req
.length
);
411 /* don't modify queue heads during completion callback */
413 req
->req
.complete(&ep
->ep
, &req
->req
);
414 ep
->stopped
= stopped
;
418 static inline void ep0_idle (struct pxa2xx_udc
*dev
)
420 dev
->ep0state
= EP0_IDLE
;
424 write_packet(volatile u32
*uddr
, struct pxa2xx_request
*req
, unsigned max
)
427 unsigned length
, count
;
429 buf
= req
->req
.buf
+ req
->req
.actual
;
432 /* how big will this packet be? */
433 length
= min(req
->req
.length
- req
->req
.actual
, max
);
434 req
->req
.actual
+= length
;
437 while (likely(count
--))
444 * write to an IN endpoint fifo, as many packets as possible.
445 * irqs will use this to write the rest later.
446 * caller guarantees at least one packet buffer is ready (or a zlp).
449 write_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
453 max
= le16_to_cpu(ep
->desc
->wMaxPacketSize
);
456 int is_last
, is_short
;
458 count
= write_packet(ep
->reg_uddr
, req
, max
);
460 /* last packet is usually short (or a zlp) */
461 if (unlikely (count
!= max
))
462 is_last
= is_short
= 1;
464 if (likely(req
->req
.length
!= req
->req
.actual
)
469 /* interrupt/iso maxpacket may not fill the fifo */
470 is_short
= unlikely (max
< ep
->fifo_size
);
473 DBG(DBG_VERY_NOISY
, "wrote %s %d bytes%s%s %d left %p\n",
475 is_last
? "/L" : "", is_short
? "/S" : "",
476 req
->req
.length
- req
->req
.actual
, req
);
478 /* let loose that packet. maybe try writing another one,
479 * double buffering might work. TSP, TPC, and TFS
480 * bit values are the same for all normal IN endpoints.
482 *ep
->reg_udccs
= UDCCS_BI_TPC
;
484 *ep
->reg_udccs
= UDCCS_BI_TSP
;
486 /* requests complete when all IN data is in the FIFO */
489 if (list_empty(&ep
->queue
) || unlikely(ep
->dma
>= 0)) {
490 pio_irq_disable (ep
->bEndpointAddress
);
492 /* unaligned data and zlps couldn't use dma */
493 if (unlikely(!list_empty(&ep
->queue
))) {
494 req
= list_entry(ep
->queue
.next
,
495 struct pxa2xx_request
, queue
);
504 // TODO experiment: how robust can fifo mode tweaking be?
505 // double buffering is off in the default fifo mode, which
506 // prevents TFS from being set here.
508 } while (*ep
->reg_udccs
& UDCCS_BI_TFS
);
512 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
513 * ep0 data stage. these chips want very simple state transitions.
516 void ep0start(struct pxa2xx_udc
*dev
, u32 flags
, const char *tag
)
518 UDCCS0
= flags
|UDCCS0_SA
|UDCCS0_OPR
;
520 dev
->req_pending
= 0;
521 DBG(DBG_VERY_NOISY
, "%s %s, %02x/%02x\n",
522 __FUNCTION__
, tag
, UDCCS0
, flags
);
526 write_ep0_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
531 count
= write_packet(&UDDR0
, req
, EP0_FIFO_SIZE
);
532 ep
->dev
->stats
.write
.bytes
+= count
;
534 /* last packet "must be" short (or a zlp) */
535 is_short
= (count
!= EP0_FIFO_SIZE
);
537 DBG(DBG_VERY_NOISY
, "ep0in %d bytes %d left %p\n", count
,
538 req
->req
.length
- req
->req
.actual
, req
);
540 if (unlikely (is_short
)) {
541 if (ep
->dev
->req_pending
)
542 ep0start(ep
->dev
, UDCCS0_IPR
, "short IN");
546 count
= req
->req
.length
;
549 #ifndef CONFIG_ARCH_IXP4XX
551 /* This seems to get rid of lost status irqs in some cases:
552 * host responds quickly, or next request involves config
553 * change automagic, or should have been hidden, or ...
555 * FIXME get rid of all udelays possible...
557 if (count
>= EP0_FIFO_SIZE
) {
560 if ((UDCCS0
& UDCCS0_OPR
) != 0) {
561 /* clear OPR, generate ack */
571 } else if (ep
->dev
->req_pending
)
572 ep0start(ep
->dev
, 0, "IN");
578 * read_fifo - unload packet(s) from the fifo we use for usb OUT
579 * transfers and put them into the request. caller should have made
580 * sure there's at least one packet ready.
582 * returns true if the request completed because of short packet or the
583 * request buffer having filled (and maybe overran till end-of-packet).
586 read_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
591 unsigned bufferspace
, count
, is_short
;
593 /* make sure there's a packet in the FIFO.
594 * UDCCS_{BO,IO}_RPC are all the same bit value.
595 * UDCCS_{BO,IO}_RNE are all the same bit value.
597 udccs
= *ep
->reg_udccs
;
598 if (unlikely ((udccs
& UDCCS_BO_RPC
) == 0))
600 buf
= req
->req
.buf
+ req
->req
.actual
;
602 bufferspace
= req
->req
.length
- req
->req
.actual
;
604 /* read all bytes from this packet */
605 if (likely (udccs
& UDCCS_BO_RNE
)) {
606 count
= 1 + (0x0ff & *ep
->reg_ubcr
);
607 req
->req
.actual
+= min (count
, bufferspace
);
610 is_short
= (count
< ep
->ep
.maxpacket
);
611 DBG(DBG_VERY_NOISY
, "read %s %02x, %d bytes%s req %p %d/%d\n",
612 ep
->ep
.name
, udccs
, count
,
613 is_short
? "/S" : "",
614 req
, req
->req
.actual
, req
->req
.length
);
615 while (likely (count
-- != 0)) {
616 u8 byte
= (u8
) *ep
->reg_uddr
;
618 if (unlikely (bufferspace
== 0)) {
619 /* this happens when the driver's buffer
620 * is smaller than what the host sent.
621 * discard the extra data.
623 if (req
->req
.status
!= -EOVERFLOW
)
624 DMSG("%s overflow %d\n",
626 req
->req
.status
= -EOVERFLOW
;
632 *ep
->reg_udccs
= UDCCS_BO_RPC
;
633 /* RPC/RSP/RNE could now reflect the other packet buffer */
635 /* iso is one request per packet */
636 if (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
637 if (udccs
& UDCCS_IO_ROF
)
638 req
->req
.status
= -EHOSTUNREACH
;
639 /* more like "is_done" */
644 if (is_short
|| req
->req
.actual
== req
->req
.length
) {
646 if (list_empty(&ep
->queue
))
647 pio_irq_disable (ep
->bEndpointAddress
);
651 /* finished that packet. the next one may be waiting... */
657 * special ep0 version of the above. no UBCR0 or double buffering; status
658 * handshaking is magic. most device protocols don't need control-OUT.
659 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
660 * protocols do use them.
663 read_ep0_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
666 unsigned bufferspace
;
668 buf
= req
->req
.buf
+ req
->req
.actual
;
669 bufferspace
= req
->req
.length
- req
->req
.actual
;
671 while (UDCCS0
& UDCCS0_RNE
) {
674 if (unlikely (bufferspace
== 0)) {
675 /* this happens when the driver's buffer
676 * is smaller than what the host sent.
677 * discard the extra data.
679 if (req
->req
.status
!= -EOVERFLOW
)
680 DMSG("%s overflow\n", ep
->ep
.name
);
681 req
->req
.status
= -EOVERFLOW
;
689 UDCCS0
= UDCCS0_OPR
| UDCCS0_IPR
;
692 if (req
->req
.actual
>= req
->req
.length
)
695 /* finished that packet. the next one may be waiting... */
701 #define MAX_IN_DMA ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
704 start_dma_nodesc(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
, int is_in
)
706 u32 dcmd
= req
->req
.length
;
707 u32 buf
= req
->req
.dma
;
708 u32 fifo
= io_v2p ((u32
)ep
->reg_uddr
);
710 /* caller guarantees there's a packet or more remaining
711 * - IN may end with a short packet (TSP set separately),
712 * - OUT is always full length
714 buf
+= req
->req
.actual
;
715 dcmd
-= req
->req
.actual
;
718 /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
719 DCSR(ep
->dma
) = DCSR_NODESC
;
721 DSADR(ep
->dma
) = buf
;
722 DTADR(ep
->dma
) = fifo
;
723 if (dcmd
> MAX_IN_DMA
)
726 ep
->dma_fixup
= (dcmd
% ep
->ep
.maxpacket
) != 0;
727 dcmd
|= DCMD_BURST32
| DCMD_WIDTH1
728 | DCMD_FLOWTRG
| DCMD_INCSRCADDR
;
731 DSADR(ep
->dma
) = fifo
;
732 DTADR(ep
->dma
) = buf
;
733 if (ep
->bmAttributes
!= USB_ENDPOINT_XFER_ISOC
)
734 dcmd
= ep
->ep
.maxpacket
;
735 dcmd
|= DCMD_BURST32
| DCMD_WIDTH1
736 | DCMD_FLOWSRC
| DCMD_INCTRGADDR
;
739 DCMD(ep
->dma
) = dcmd
;
740 DCSR(ep
->dma
) = DCSR_RUN
| DCSR_NODESC
742 ? DCSR_STOPIRQEN
/* use dma_nodesc_handler() */
743 : 0); /* use handle_ep() */
746 static void kick_dma(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
748 int is_in
= ep
->bEndpointAddress
& USB_DIR_IN
;
751 /* unaligned tx buffers and zlps only work with PIO */
752 if ((req
->req
.dma
& 0x0f) != 0
753 || unlikely((req
->req
.length
- req
->req
.actual
)
755 pio_irq_enable(ep
->bEndpointAddress
);
756 if ((*ep
->reg_udccs
& UDCCS_BI_TFS
) != 0)
757 (void) write_fifo(ep
, req
);
759 start_dma_nodesc(ep
, req
, USB_DIR_IN
);
762 if ((req
->req
.length
- req
->req
.actual
) < ep
->ep
.maxpacket
) {
763 DMSG("%s short dma read...\n", ep
->ep
.name
);
764 /* we're always set up for pio out */
767 *ep
->reg_udccs
= UDCCS_BO_DME
768 | (*ep
->reg_udccs
& UDCCS_BO_FST
);
769 start_dma_nodesc(ep
, req
, USB_DIR_OUT
);
774 static void cancel_dma(struct pxa2xx_ep
*ep
)
776 struct pxa2xx_request
*req
;
779 if (DCSR(ep
->dma
) == 0 || list_empty(&ep
->queue
))
783 while ((DCSR(ep
->dma
) & DCSR_STOPSTATE
) == 0)
786 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
787 tmp
= DCMD(ep
->dma
) & DCMD_LENGTH
;
788 req
->req
.actual
= req
->req
.length
- (tmp
& DCMD_LENGTH
);
790 /* the last tx packet may be incomplete, so flush the fifo.
791 * FIXME correct req.actual if we can
793 if (ep
->bEndpointAddress
& USB_DIR_IN
)
794 *ep
->reg_udccs
= UDCCS_BI_FTF
;
797 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
798 static void dma_nodesc_handler(int dmach
, void *_ep
, struct pt_regs
*r
)
800 struct pxa2xx_ep
*ep
= _ep
;
801 struct pxa2xx_request
*req
;
806 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
809 ep
->dev
->stats
.irqs
++;
810 HEX_DISPLAY(ep
->dev
->stats
.irqs
);
815 if ((tmp
& DCSR_STOPSTATE
) == 0
816 || (DDADR(ep
->dma
) & DDADR_STOP
) != 0) {
817 DBG(DBG_VERBOSE
, "%s, dcsr %08x ddadr %08x\n",
818 ep
->ep
.name
, DCSR(ep
->dma
), DDADR(ep
->dma
));
821 DCSR(ep
->dma
) = 0; /* clear DCSR_STOPSTATE */
823 /* update transfer status */
824 completed
= tmp
& DCSR_BUSERR
;
825 if (ep
->bEndpointAddress
& USB_DIR_IN
)
826 tmp
= DSADR(ep
->dma
);
828 tmp
= DTADR(ep
->dma
);
829 req
->req
.actual
= tmp
- req
->req
.dma
;
831 /* FIXME seems we sometimes see partial transfers... */
833 if (unlikely(completed
!= 0))
834 req
->req
.status
= -EIO
;
835 else if (req
->req
.actual
) {
836 /* these registers have zeroes in low bits; they miscount
837 * some (end-of-transfer) short packets: tx 14 as tx 12
840 req
->req
.actual
= min(req
->req
.actual
+ 3,
843 tmp
= (req
->req
.length
- req
->req
.actual
);
844 completed
= (tmp
== 0);
845 if (completed
&& (ep
->bEndpointAddress
& USB_DIR_IN
)) {
847 /* maybe validate final short packet ... */
848 if ((req
->req
.actual
% ep
->ep
.maxpacket
) != 0)
849 *ep
->reg_udccs
= UDCCS_BI_TSP
/*|UDCCS_BI_TPC*/;
851 /* ... or zlp, using pio fallback */
852 else if (ep
->bmAttributes
== USB_ENDPOINT_XFER_BULK
854 DMSG("%s zlp terminate ...\n", ep
->ep
.name
);
860 if (likely(completed
)) {
863 /* maybe re-activate after completion */
864 if (ep
->stopped
|| list_empty(&ep
->queue
))
866 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
875 /*-------------------------------------------------------------------------*/
878 pxa2xx_ep_queue(struct usb_ep
*_ep
, struct usb_request
*_req
, gfp_t gfp_flags
)
880 struct pxa2xx_request
*req
;
881 struct pxa2xx_ep
*ep
;
882 struct pxa2xx_udc
*dev
;
885 req
= container_of(_req
, struct pxa2xx_request
, req
);
886 if (unlikely (!_req
|| !_req
->complete
|| !_req
->buf
887 || !list_empty(&req
->queue
))) {
888 DMSG("%s, bad params\n", __FUNCTION__
);
892 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
893 if (unlikely (!_ep
|| (!ep
->desc
&& ep
->ep
.name
!= ep0name
))) {
894 DMSG("%s, bad ep\n", __FUNCTION__
);
899 if (unlikely (!dev
->driver
900 || dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)) {
901 DMSG("%s, bogus device state\n", __FUNCTION__
);
905 /* iso is always one packet per request, that's the only way
906 * we can report per-packet status. that also helps with dma.
908 if (unlikely (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
909 && req
->req
.length
> le16_to_cpu
910 (ep
->desc
->wMaxPacketSize
)))
914 // FIXME caller may already have done the dma mapping
916 _req
->dma
= dma_map_single(dev
->dev
,
917 _req
->buf
, _req
->length
,
918 ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0)
924 DBG(DBG_NOISY
, "%s queue req %p, len %d buf %p\n",
925 _ep
->name
, _req
, _req
->length
, _req
->buf
);
927 local_irq_save(flags
);
929 _req
->status
= -EINPROGRESS
;
932 /* kickstart this i/o queue? */
933 if (list_empty(&ep
->queue
) && !ep
->stopped
) {
934 if (ep
->desc
== 0 /* ep0 */) {
935 unsigned length
= _req
->length
;
937 switch (dev
->ep0state
) {
938 case EP0_IN_DATA_PHASE
:
939 dev
->stats
.write
.ops
++;
940 if (write_ep0_fifo(ep
, req
))
944 case EP0_OUT_DATA_PHASE
:
945 dev
->stats
.read
.ops
++;
947 if (dev
->req_config
) {
948 DBG(DBG_VERBOSE
, "ep0 config ack%s\n",
949 dev
->has_cfr
? "" : " raced");
951 UDCCFR
= UDCCFR_AREN
|UDCCFR_ACM
954 dev
->ep0state
= EP0_END_XFER
;
955 local_irq_restore (flags
);
958 if (dev
->req_pending
)
959 ep0start(dev
, UDCCS0_IPR
, "OUT");
960 if (length
== 0 || ((UDCCS0
& UDCCS0_RNE
) != 0
961 && read_ep0_fifo(ep
, req
))) {
969 DMSG("ep0 i/o, odd state %d\n", dev
->ep0state
);
970 local_irq_restore (flags
);
974 /* either start dma or prime pio pump */
975 } else if (ep
->dma
>= 0) {
978 /* can the FIFO can satisfy the request immediately? */
979 } else if ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0) {
980 if ((*ep
->reg_udccs
& UDCCS_BI_TFS
) != 0
981 && write_fifo(ep
, req
))
983 } else if ((*ep
->reg_udccs
& UDCCS_BO_RFS
) != 0
984 && read_fifo(ep
, req
)) {
988 if (likely (req
&& ep
->desc
) && ep
->dma
< 0)
989 pio_irq_enable(ep
->bEndpointAddress
);
992 /* pio or dma irq handler advances the queue. */
993 if (likely (req
!= 0))
994 list_add_tail(&req
->queue
, &ep
->queue
);
995 local_irq_restore(flags
);
1002 * nuke - dequeue ALL requests
1004 static void nuke(struct pxa2xx_ep
*ep
, int status
)
1006 struct pxa2xx_request
*req
;
1008 /* called with irqs blocked */
1010 if (ep
->dma
>= 0 && !ep
->stopped
)
1013 while (!list_empty(&ep
->queue
)) {
1014 req
= list_entry(ep
->queue
.next
,
1015 struct pxa2xx_request
,
1017 done(ep
, req
, status
);
1020 pio_irq_disable (ep
->bEndpointAddress
);
1024 /* dequeue JUST ONE request */
1025 static int pxa2xx_ep_dequeue(struct usb_ep
*_ep
, struct usb_request
*_req
)
1027 struct pxa2xx_ep
*ep
;
1028 struct pxa2xx_request
*req
;
1029 unsigned long flags
;
1031 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1032 if (!_ep
|| ep
->ep
.name
== ep0name
)
1035 local_irq_save(flags
);
1037 /* make sure it's actually queued on this endpoint */
1038 list_for_each_entry (req
, &ep
->queue
, queue
) {
1039 if (&req
->req
== _req
)
1042 if (&req
->req
!= _req
) {
1043 local_irq_restore(flags
);
1048 if (ep
->dma
>= 0 && ep
->queue
.next
== &req
->queue
&& !ep
->stopped
) {
1050 done(ep
, req
, -ECONNRESET
);
1052 if (!list_empty(&ep
->queue
)) {
1053 req
= list_entry(ep
->queue
.next
,
1054 struct pxa2xx_request
, queue
);
1059 done(ep
, req
, -ECONNRESET
);
1061 local_irq_restore(flags
);
1065 /*-------------------------------------------------------------------------*/
1067 static int pxa2xx_ep_set_halt(struct usb_ep
*_ep
, int value
)
1069 struct pxa2xx_ep
*ep
;
1070 unsigned long flags
;
1072 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1074 || (!ep
->desc
&& ep
->ep
.name
!= ep0name
))
1075 || ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
1076 DMSG("%s, bad ep\n", __FUNCTION__
);
1080 /* this path (reset toggle+halt) is needed to implement
1081 * SET_INTERFACE on normal hardware. but it can't be
1082 * done from software on the PXA UDC, and the hardware
1083 * forgets to do it as part of SET_INTERFACE automagic.
1085 DMSG("only host can clear %s halt\n", _ep
->name
);
1089 local_irq_save(flags
);
1091 if ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0
1092 && ((*ep
->reg_udccs
& UDCCS_BI_TFS
) == 0
1093 || !list_empty(&ep
->queue
))) {
1094 local_irq_restore(flags
);
1098 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1099 *ep
->reg_udccs
= UDCCS_BI_FST
|UDCCS_BI_FTF
;
1101 /* ep0 needs special care */
1103 start_watchdog(ep
->dev
);
1104 ep
->dev
->req_pending
= 0;
1105 ep
->dev
->ep0state
= EP0_STALL
;
1107 /* and bulk/intr endpoints like dropping stalls too */
1110 for (i
= 0; i
< 1000; i
+= 20) {
1111 if (*ep
->reg_udccs
& UDCCS_BI_SST
)
1116 local_irq_restore(flags
);
1118 DBG(DBG_VERBOSE
, "%s halt\n", _ep
->name
);
1122 static int pxa2xx_ep_fifo_status(struct usb_ep
*_ep
)
1124 struct pxa2xx_ep
*ep
;
1126 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1128 DMSG("%s, bad ep\n", __FUNCTION__
);
1131 /* pxa can't report unclaimed bytes from IN fifos */
1132 if ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0)
1134 if (ep
->dev
->gadget
.speed
== USB_SPEED_UNKNOWN
1135 || (*ep
->reg_udccs
& UDCCS_BO_RFS
) == 0)
1138 return (*ep
->reg_ubcr
& 0xfff) + 1;
1141 static void pxa2xx_ep_fifo_flush(struct usb_ep
*_ep
)
1143 struct pxa2xx_ep
*ep
;
1145 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1146 if (!_ep
|| ep
->ep
.name
== ep0name
|| !list_empty(&ep
->queue
)) {
1147 DMSG("%s, bad ep\n", __FUNCTION__
);
1151 /* toggle and halt bits stay unchanged */
1153 /* for OUT, just read and discard the FIFO contents. */
1154 if ((ep
->bEndpointAddress
& USB_DIR_IN
) == 0) {
1155 while (((*ep
->reg_udccs
) & UDCCS_BO_RNE
) != 0)
1156 (void) *ep
->reg_uddr
;
1160 /* most IN status is the same, but ISO can't stall */
1161 *ep
->reg_udccs
= UDCCS_BI_TPC
|UDCCS_BI_FTF
|UDCCS_BI_TUR
1162 | (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
)
1167 static struct usb_ep_ops pxa2xx_ep_ops
= {
1168 .enable
= pxa2xx_ep_enable
,
1169 .disable
= pxa2xx_ep_disable
,
1171 .alloc_request
= pxa2xx_ep_alloc_request
,
1172 .free_request
= pxa2xx_ep_free_request
,
1174 .alloc_buffer
= pxa2xx_ep_alloc_buffer
,
1175 .free_buffer
= pxa2xx_ep_free_buffer
,
1177 .queue
= pxa2xx_ep_queue
,
1178 .dequeue
= pxa2xx_ep_dequeue
,
1180 .set_halt
= pxa2xx_ep_set_halt
,
1181 .fifo_status
= pxa2xx_ep_fifo_status
,
1182 .fifo_flush
= pxa2xx_ep_fifo_flush
,
1186 /* ---------------------------------------------------------------------------
1187 * device-scoped parts of the api to the usb controller hardware
1188 * ---------------------------------------------------------------------------
1191 static int pxa2xx_udc_get_frame(struct usb_gadget
*_gadget
)
1193 return ((UFNRH
& 0x07) << 8) | (UFNRL
& 0xff);
1196 static int pxa2xx_udc_wakeup(struct usb_gadget
*_gadget
)
1198 /* host may not have enabled remote wakeup */
1199 if ((UDCCS0
& UDCCS0_DRWF
) == 0)
1200 return -EHOSTUNREACH
;
1201 udc_set_mask_UDCCR(UDCCR_RSM
);
1205 static void stop_activity(struct pxa2xx_udc
*, struct usb_gadget_driver
*);
1206 static void udc_enable (struct pxa2xx_udc
*);
1207 static void udc_disable(struct pxa2xx_udc
*);
1209 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
1212 static int pullup(struct pxa2xx_udc
*udc
, int is_active
)
1214 is_active
= is_active
&& udc
->vbus
&& udc
->pullup
;
1215 DMSG("%s\n", is_active
? "active" : "inactive");
1219 if (udc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
1220 DMSG("disconnect %s\n", udc
->driver
1221 ? udc
->driver
->driver
.name
1223 stop_activity(udc
, udc
->driver
);
1230 /* VBUS reporting logically comes from a transceiver */
1231 static int pxa2xx_udc_vbus_session(struct usb_gadget
*_gadget
, int is_active
)
1233 struct pxa2xx_udc
*udc
;
1235 udc
= container_of(_gadget
, struct pxa2xx_udc
, gadget
);
1236 udc
->vbus
= is_active
= (is_active
!= 0);
1237 DMSG("vbus %s\n", is_active
? "supplied" : "inactive");
1238 pullup(udc
, is_active
);
1242 /* drivers may have software control over D+ pullup */
1243 static int pxa2xx_udc_pullup(struct usb_gadget
*_gadget
, int is_active
)
1245 struct pxa2xx_udc
*udc
;
1247 udc
= container_of(_gadget
, struct pxa2xx_udc
, gadget
);
1249 /* not all boards support pullup control */
1250 if (!udc
->mach
->udc_command
)
1253 is_active
= (is_active
!= 0);
1254 udc
->pullup
= is_active
;
1255 pullup(udc
, is_active
);
1259 static const struct usb_gadget_ops pxa2xx_udc_ops
= {
1260 .get_frame
= pxa2xx_udc_get_frame
,
1261 .wakeup
= pxa2xx_udc_wakeup
,
1262 .vbus_session
= pxa2xx_udc_vbus_session
,
1263 .pullup
= pxa2xx_udc_pullup
,
1265 // .vbus_draw ... boards may consume current from VBUS, up to
1266 // 100-500mA based on config. the 500uA suspend ceiling means
1267 // that exclusively vbus-powered PXA designs violate USB specs.
1270 /*-------------------------------------------------------------------------*/
1272 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1274 static const char proc_node_name
[] = "driver/udc";
1277 udc_proc_read(char *page
, char **start
, off_t off
, int count
,
1278 int *eof
, void *_dev
)
1281 struct pxa2xx_udc
*dev
= _dev
;
1283 unsigned size
= count
;
1284 unsigned long flags
;
1291 local_irq_save(flags
);
1293 /* basic device status */
1294 t
= scnprintf(next
, size
, DRIVER_DESC
"\n"
1295 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1296 driver_name
, DRIVER_VERSION SIZE_STR DMASTR
,
1297 dev
->driver
? dev
->driver
->driver
.name
: "(none)",
1298 is_vbus_present() ? "full speed" : "disconnected");
1302 /* registers for device and ep0 */
1303 t
= scnprintf(next
, size
,
1304 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1305 UICR1
, UICR0
, USIR1
, USIR0
, UFNRH
, UFNRL
);
1310 t
= scnprintf(next
, size
,
1311 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp
,
1312 (tmp
& UDCCR_REM
) ? " rem" : "",
1313 (tmp
& UDCCR_RSTIR
) ? " rstir" : "",
1314 (tmp
& UDCCR_SRM
) ? " srm" : "",
1315 (tmp
& UDCCR_SUSIR
) ? " susir" : "",
1316 (tmp
& UDCCR_RESIR
) ? " resir" : "",
1317 (tmp
& UDCCR_RSM
) ? " rsm" : "",
1318 (tmp
& UDCCR_UDA
) ? " uda" : "",
1319 (tmp
& UDCCR_UDE
) ? " ude" : "");
1324 t
= scnprintf(next
, size
,
1325 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp
,
1326 (tmp
& UDCCS0_SA
) ? " sa" : "",
1327 (tmp
& UDCCS0_RNE
) ? " rne" : "",
1328 (tmp
& UDCCS0_FST
) ? " fst" : "",
1329 (tmp
& UDCCS0_SST
) ? " sst" : "",
1330 (tmp
& UDCCS0_DRWF
) ? " dwrf" : "",
1331 (tmp
& UDCCS0_FTF
) ? " ftf" : "",
1332 (tmp
& UDCCS0_IPR
) ? " ipr" : "",
1333 (tmp
& UDCCS0_OPR
) ? " opr" : "");
1339 t
= scnprintf(next
, size
,
1340 "udccfr %02X =%s%s\n", tmp
,
1341 (tmp
& UDCCFR_AREN
) ? " aren" : "",
1342 (tmp
& UDCCFR_ACM
) ? " acm" : "");
1347 if (!is_vbus_present() || !dev
->driver
)
1350 t
= scnprintf(next
, size
, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1351 dev
->stats
.write
.bytes
, dev
->stats
.write
.ops
,
1352 dev
->stats
.read
.bytes
, dev
->stats
.read
.ops
,
1357 /* dump endpoint queues */
1358 for (i
= 0; i
< PXA_UDC_NUM_ENDPOINTS
; i
++) {
1359 struct pxa2xx_ep
*ep
= &dev
->ep
[i
];
1360 struct pxa2xx_request
*req
;
1364 const struct usb_endpoint_descriptor
*d
;
1369 tmp
= *dev
->ep
[i
].reg_udccs
;
1370 t
= scnprintf(next
, size
,
1371 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1372 ep
->ep
.name
, le16_to_cpu (d
->wMaxPacketSize
),
1373 (ep
->dma
>= 0) ? "dma" : "pio", tmp
,
1374 ep
->pio_irqs
, ep
->dma_irqs
);
1375 /* TODO translate all five groups of udccs bits! */
1377 } else /* ep0 should only have one transfer queued */
1378 t
= scnprintf(next
, size
, "ep0 max 16 pio irqs %lu\n",
1380 if (t
<= 0 || t
> size
)
1385 if (list_empty(&ep
->queue
)) {
1386 t
= scnprintf(next
, size
, "\t(nothing queued)\n");
1387 if (t
<= 0 || t
> size
)
1393 list_for_each_entry(req
, &ep
->queue
, queue
) {
1395 if (ep
->dma
>= 0 && req
->queue
.prev
== &ep
->queue
)
1396 t
= scnprintf(next
, size
,
1397 "\treq %p len %d/%d "
1398 "buf %p (dma%d dcmd %08x)\n",
1399 &req
->req
, req
->req
.actual
,
1400 req
->req
.length
, req
->req
.buf
,
1401 ep
->dma
, DCMD(ep
->dma
)
1402 // low 13 bits == bytes-to-go
1406 t
= scnprintf(next
, size
,
1407 "\treq %p len %d/%d buf %p\n",
1408 &req
->req
, req
->req
.actual
,
1409 req
->req
.length
, req
->req
.buf
);
1410 if (t
<= 0 || t
> size
)
1418 local_irq_restore(flags
);
1420 return count
- size
;
1423 #define create_proc_files() \
1424 create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1425 #define remove_proc_files() \
1426 remove_proc_entry(proc_node_name, NULL)
1428 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
1430 #define create_proc_files() do {} while (0)
1431 #define remove_proc_files() do {} while (0)
1433 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
1435 /* "function" sysfs attribute */
1437 show_function (struct device
*_dev
, struct device_attribute
*attr
, char *buf
)
1439 struct pxa2xx_udc
*dev
= dev_get_drvdata (_dev
);
1442 || !dev
->driver
->function
1443 || strlen (dev
->driver
->function
) > PAGE_SIZE
)
1445 return scnprintf (buf
, PAGE_SIZE
, "%s\n", dev
->driver
->function
);
1447 static DEVICE_ATTR (function
, S_IRUGO
, show_function
, NULL
);
1449 /*-------------------------------------------------------------------------*/
1452 * udc_disable - disable USB device controller
1454 static void udc_disable(struct pxa2xx_udc
*dev
)
1456 /* block all irqs */
1457 udc_set_mask_UDCCR(UDCCR_SRM
|UDCCR_REM
);
1458 UICR0
= UICR1
= 0xff;
1461 /* if hardware supports it, disconnect from usb */
1464 udc_clear_mask_UDCCR(UDCCR_UDE
);
1466 #ifdef CONFIG_ARCH_PXA
1467 /* Disable clock for USB device */
1468 pxa_set_cken(CKEN11_USB
, 0);
1472 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1478 * udc_reinit - initialize software state
1480 static void udc_reinit(struct pxa2xx_udc
*dev
)
1484 /* device/ep0 records init */
1485 INIT_LIST_HEAD (&dev
->gadget
.ep_list
);
1486 INIT_LIST_HEAD (&dev
->gadget
.ep0
->ep_list
);
1487 dev
->ep0state
= EP0_IDLE
;
1489 /* basic endpoint records init */
1490 for (i
= 0; i
< PXA_UDC_NUM_ENDPOINTS
; i
++) {
1491 struct pxa2xx_ep
*ep
= &dev
->ep
[i
];
1494 list_add_tail (&ep
->ep
.ep_list
, &dev
->gadget
.ep_list
);
1498 INIT_LIST_HEAD (&ep
->queue
);
1499 ep
->pio_irqs
= ep
->dma_irqs
= 0;
1502 /* the rest was statically initialized, and is read-only */
1505 /* until it's enabled, this UDC should be completely invisible
1508 static void udc_enable (struct pxa2xx_udc
*dev
)
1510 udc_clear_mask_UDCCR(UDCCR_UDE
);
1512 #ifdef CONFIG_ARCH_PXA
1513 /* Enable clock for USB device */
1514 pxa_set_cken(CKEN11_USB
, 1);
1518 /* try to clear these bits before we enable the udc */
1519 udc_ack_int_UDCCR(UDCCR_SUSIR
|/*UDCCR_RSTIR|*/UDCCR_RESIR
);
1522 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1523 dev
->stats
.irqs
= 0;
1526 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1528 * - if RESET is already in progress, ack interrupt
1529 * - unmask reset interrupt
1531 udc_set_mask_UDCCR(UDCCR_UDE
);
1532 if (!(UDCCR
& UDCCR_UDA
))
1533 udc_ack_int_UDCCR(UDCCR_RSTIR
);
1535 if (dev
->has_cfr
/* UDC_RES2 is defined */) {
1536 /* pxa255 (a0+) can avoid a set_config race that could
1537 * prevent gadget drivers from configuring correctly
1539 UDCCFR
= UDCCFR_ACM
| UDCCFR_MB1
;
1541 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1542 * which could result in missing packets and interrupts.
1543 * supposedly one bit per endpoint, controlling whether it
1544 * double buffers or not; ACM/AREN bits fit into the holes.
1545 * zero bits (like USIR0_IRx) disable double buffering.
1551 #ifdef DISABLE_TEST_MODE
1552 /* "test mode" seems to have become the default in later chip
1553 * revs, preventing double buffering (and invalidating docs).
1554 * this EXPERIMENT enables it for bulk endpoints by tweaking
1555 * undefined/reserved register bits (that other drivers clear).
1556 * Belcarra code comments noted this usage.
1558 if (fifo_mode
& 1) { /* IN endpoints */
1559 UDC_RES1
|= USIR0_IR1
|USIR0_IR6
;
1560 UDC_RES2
|= USIR1_IR11
;
1562 if (fifo_mode
& 2) { /* OUT endpoints */
1563 UDC_RES1
|= USIR0_IR2
|USIR0_IR7
;
1564 UDC_RES2
|= USIR1_IR12
;
1568 /* enable suspend/resume and reset irqs */
1569 udc_clear_mask_UDCCR(UDCCR_SRM
| UDCCR_REM
);
1571 /* enable ep0 irqs */
1572 UICR0
&= ~UICR0_IM0
;
1574 /* if hardware supports it, pullup D+ and wait for reset */
1579 /* when a driver is successfully registered, it will receive
1580 * control requests including set_configuration(), which enables
1581 * non-control requests. then usb traffic follows until a
1582 * disconnect is reported. then a host may connect again, or
1583 * the driver might get unbound.
1585 int usb_gadget_register_driver(struct usb_gadget_driver
*driver
)
1587 struct pxa2xx_udc
*dev
= the_controller
;
1591 || driver
->speed
< USB_SPEED_FULL
1594 || !driver
->disconnect
1602 /* first hook up the driver ... */
1603 dev
->driver
= driver
;
1604 dev
->gadget
.dev
.driver
= &driver
->driver
;
1607 device_add (&dev
->gadget
.dev
);
1608 retval
= driver
->bind(&dev
->gadget
);
1610 DMSG("bind to driver %s --> error %d\n",
1611 driver
->driver
.name
, retval
);
1612 device_del (&dev
->gadget
.dev
);
1615 dev
->gadget
.dev
.driver
= NULL
;
1618 device_create_file(dev
->dev
, &dev_attr_function
);
1620 /* ... then enable host detection and ep0; and we're ready
1621 * for set_configuration as well as eventual disconnect.
1623 DMSG("registered gadget driver '%s'\n", driver
->driver
.name
);
1628 EXPORT_SYMBOL(usb_gadget_register_driver
);
1631 stop_activity(struct pxa2xx_udc
*dev
, struct usb_gadget_driver
*driver
)
1635 /* don't disconnect drivers more than once */
1636 if (dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)
1638 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1640 /* prevent new request submissions, kill any outstanding requests */
1641 for (i
= 0; i
< PXA_UDC_NUM_ENDPOINTS
; i
++) {
1642 struct pxa2xx_ep
*ep
= &dev
->ep
[i
];
1645 nuke(ep
, -ESHUTDOWN
);
1647 del_timer_sync(&dev
->timer
);
1649 /* report disconnect; the driver is already quiesced */
1652 driver
->disconnect(&dev
->gadget
);
1654 /* re-init driver-visible data structures */
1658 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
1660 struct pxa2xx_udc
*dev
= the_controller
;
1664 if (!driver
|| driver
!= dev
->driver
)
1667 local_irq_disable();
1669 stop_activity(dev
, driver
);
1672 driver
->unbind(&dev
->gadget
);
1675 device_del (&dev
->gadget
.dev
);
1676 device_remove_file(dev
->dev
, &dev_attr_function
);
1678 DMSG("unregistered gadget driver '%s'\n", driver
->driver
.name
);
1682 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
1685 /*-------------------------------------------------------------------------*/
1687 #ifdef CONFIG_ARCH_LUBBOCK
1689 /* Lubbock has separate connect and disconnect irqs. More typical designs
1690 * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1694 lubbock_vbus_irq(int irq
, void *_dev
, struct pt_regs
*r
)
1696 struct pxa2xx_udc
*dev
= _dev
;
1700 HEX_DISPLAY(dev
->stats
.irqs
);
1702 case LUBBOCK_USB_IRQ
:
1705 disable_irq(LUBBOCK_USB_IRQ
);
1706 enable_irq(LUBBOCK_USB_DISC_IRQ
);
1708 case LUBBOCK_USB_DISC_IRQ
:
1711 disable_irq(LUBBOCK_USB_DISC_IRQ
);
1712 enable_irq(LUBBOCK_USB_IRQ
);
1718 pxa2xx_udc_vbus_session(&dev
->gadget
, vbus
);
1725 /*-------------------------------------------------------------------------*/
1727 static inline void clear_ep_state (struct pxa2xx_udc
*dev
)
1731 /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1732 * fifos, and pending transactions mustn't be continued in any case.
1734 for (i
= 1; i
< PXA_UDC_NUM_ENDPOINTS
; i
++)
1735 nuke(&dev
->ep
[i
], -ECONNABORTED
);
1738 static void udc_watchdog(unsigned long _dev
)
1740 struct pxa2xx_udc
*dev
= (void *)_dev
;
1742 local_irq_disable();
1743 if (dev
->ep0state
== EP0_STALL
1744 && (UDCCS0
& UDCCS0_FST
) == 0
1745 && (UDCCS0
& UDCCS0_SST
) == 0) {
1746 UDCCS0
= UDCCS0_FST
|UDCCS0_FTF
;
1747 DBG(DBG_VERBOSE
, "ep0 re-stall\n");
1748 start_watchdog(dev
);
1753 static void handle_ep0 (struct pxa2xx_udc
*dev
)
1755 u32 udccs0
= UDCCS0
;
1756 struct pxa2xx_ep
*ep
= &dev
->ep
[0];
1757 struct pxa2xx_request
*req
;
1759 struct usb_ctrlrequest r
;
1764 if (list_empty(&ep
->queue
))
1767 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
1769 /* clear stall status */
1770 if (udccs0
& UDCCS0_SST
) {
1772 UDCCS0
= UDCCS0_SST
;
1773 del_timer(&dev
->timer
);
1777 /* previous request unfinished? non-error iff back-to-back ... */
1778 if ((udccs0
& UDCCS0_SA
) != 0 && dev
->ep0state
!= EP0_IDLE
) {
1780 del_timer(&dev
->timer
);
1784 switch (dev
->ep0state
) {
1786 /* late-breaking status? */
1789 /* start control request? */
1790 if (likely((udccs0
& (UDCCS0_OPR
|UDCCS0_SA
|UDCCS0_RNE
))
1791 == (UDCCS0_OPR
|UDCCS0_SA
|UDCCS0_RNE
))) {
1796 /* read SETUP packet */
1797 for (i
= 0; i
< 8; i
++) {
1798 if (unlikely(!(UDCCS0
& UDCCS0_RNE
))) {
1800 DMSG("SETUP %d!\n", i
);
1803 u
.raw
[i
] = (u8
) UDDR0
;
1805 if (unlikely((UDCCS0
& UDCCS0_RNE
) != 0))
1809 DBG(DBG_VERBOSE
, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1810 u
.r
.bRequestType
, u
.r
.bRequest
,
1811 le16_to_cpu(u
.r
.wValue
),
1812 le16_to_cpu(u
.r
.wIndex
),
1813 le16_to_cpu(u
.r
.wLength
));
1815 /* cope with automagic for some standard requests. */
1816 dev
->req_std
= (u
.r
.bRequestType
& USB_TYPE_MASK
)
1817 == USB_TYPE_STANDARD
;
1818 dev
->req_config
= 0;
1819 dev
->req_pending
= 1;
1820 switch (u
.r
.bRequest
) {
1821 /* hardware restricts gadget drivers here! */
1822 case USB_REQ_SET_CONFIGURATION
:
1823 if (u
.r
.bRequestType
== USB_RECIP_DEVICE
) {
1824 /* reflect hardware's automagic
1825 * up to the gadget driver.
1828 dev
->req_config
= 1;
1829 clear_ep_state(dev
);
1830 /* if !has_cfr, there's no synch
1831 * else use AREN (later) not SA|OPR
1832 * USIR0_IR0 acts edge sensitive
1836 /* ... and here, even more ... */
1837 case USB_REQ_SET_INTERFACE
:
1838 if (u
.r
.bRequestType
== USB_RECIP_INTERFACE
) {
1839 /* udc hardware is broken by design:
1840 * - altsetting may only be zero;
1841 * - hw resets all interfaces' eps;
1842 * - ep reset doesn't include halt(?).
1844 DMSG("broken set_interface (%d/%d)\n",
1845 le16_to_cpu(u
.r
.wIndex
),
1846 le16_to_cpu(u
.r
.wValue
));
1850 /* hardware was supposed to hide this */
1851 case USB_REQ_SET_ADDRESS
:
1852 if (u
.r
.bRequestType
== USB_RECIP_DEVICE
) {
1853 ep0start(dev
, 0, "address");
1859 if (u
.r
.bRequestType
& USB_DIR_IN
)
1860 dev
->ep0state
= EP0_IN_DATA_PHASE
;
1862 dev
->ep0state
= EP0_OUT_DATA_PHASE
;
1864 i
= dev
->driver
->setup(&dev
->gadget
, &u
.r
);
1866 /* hardware automagic preventing STALL... */
1867 if (dev
->req_config
) {
1868 /* hardware sometimes neglects to tell
1869 * tell us about config change events,
1870 * so later ones may fail...
1872 WARN("config change %02x fail %d?\n",
1875 /* TODO experiment: if has_cfr,
1876 * hardware didn't ACK; maybe we
1877 * could actually STALL!
1880 DBG(DBG_VERBOSE
, "protocol STALL, "
1881 "%02x err %d\n", UDCCS0
, i
);
1883 /* the watchdog timer helps deal with cases
1884 * where udc seems to clear FST wrongly, and
1885 * then NAKs instead of STALLing.
1887 ep0start(dev
, UDCCS0_FST
|UDCCS0_FTF
, "stall");
1888 start_watchdog(dev
);
1889 dev
->ep0state
= EP0_STALL
;
1891 /* deferred i/o == no response yet */
1892 } else if (dev
->req_pending
) {
1893 if (likely(dev
->ep0state
== EP0_IN_DATA_PHASE
1894 || dev
->req_std
|| u
.r
.wLength
))
1895 ep0start(dev
, 0, "defer");
1897 ep0start(dev
, UDCCS0_IPR
, "defer/IPR");
1900 /* expect at least one data or status stage irq */
1903 } else if (likely((udccs0
& (UDCCS0_OPR
|UDCCS0_SA
))
1904 == (UDCCS0_OPR
|UDCCS0_SA
))) {
1907 /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1908 * still observed on a pxa255 a0.
1910 DBG(DBG_VERBOSE
, "e131\n");
1913 /* read SETUP data, but don't trust it too much */
1914 for (i
= 0; i
< 8; i
++)
1915 u
.raw
[i
] = (u8
) UDDR0
;
1916 if ((u
.r
.bRequestType
& USB_RECIP_MASK
)
1919 if (u
.word
[0] == 0 && u
.word
[1] == 0)
1923 /* some random early IRQ:
1926 * - OPR got set, without SA (likely status stage)
1928 UDCCS0
= udccs0
& (UDCCS0_SA
|UDCCS0_OPR
);
1931 case EP0_IN_DATA_PHASE
: /* GET_DESCRIPTOR etc */
1932 if (udccs0
& UDCCS0_OPR
) {
1933 UDCCS0
= UDCCS0_OPR
|UDCCS0_FTF
;
1934 DBG(DBG_VERBOSE
, "ep0in premature status\n");
1938 } else /* irq was IPR clearing */ {
1940 /* this IN packet might finish the request */
1941 (void) write_ep0_fifo(ep
, req
);
1942 } /* else IN token before response was written */
1945 case EP0_OUT_DATA_PHASE
: /* SET_DESCRIPTOR etc */
1946 if (udccs0
& UDCCS0_OPR
) {
1948 /* this OUT packet might finish the request */
1949 if (read_ep0_fifo(ep
, req
))
1951 /* else more OUT packets expected */
1952 } /* else OUT token before read was issued */
1953 } else /* irq was IPR clearing */ {
1954 DBG(DBG_VERBOSE
, "ep0out premature status\n");
1963 /* ack control-IN status (maybe in-zlp was skipped)
1964 * also appears after some config change events.
1966 if (udccs0
& UDCCS0_OPR
)
1967 UDCCS0
= UDCCS0_OPR
;
1971 UDCCS0
= UDCCS0_FST
;
1977 static void handle_ep(struct pxa2xx_ep
*ep
)
1979 struct pxa2xx_request
*req
;
1980 int is_in
= ep
->bEndpointAddress
& USB_DIR_IN
;
1986 if (likely (!list_empty(&ep
->queue
)))
1987 req
= list_entry(ep
->queue
.next
,
1988 struct pxa2xx_request
, queue
);
1992 // TODO check FST handling
1994 udccs
= *ep
->reg_udccs
;
1995 if (unlikely(is_in
)) { /* irq from TPC, SST, or (ISO) TUR */
1997 if (likely(ep
->bmAttributes
== USB_ENDPOINT_XFER_BULK
))
1998 tmp
|= UDCCS_BI_SST
;
2001 *ep
->reg_udccs
= tmp
;
2002 if (req
&& likely ((udccs
& UDCCS_BI_TFS
) != 0))
2003 completed
= write_fifo(ep
, req
);
2005 } else { /* irq from RPC (or for ISO, ROF) */
2006 if (likely(ep
->bmAttributes
== USB_ENDPOINT_XFER_BULK
))
2007 tmp
= UDCCS_BO_SST
| UDCCS_BO_DME
;
2009 tmp
= UDCCS_IO_ROF
| UDCCS_IO_DME
;
2012 *ep
->reg_udccs
= tmp
;
2014 /* fifos can hold packets, ready for reading... */
2017 // TODO didn't yet debug out-dma. this approach assumes
2018 // the worst about short packets and RPC; it might be better.
2020 if (likely(ep
->dma
>= 0)) {
2021 if (!(udccs
& UDCCS_BO_RSP
)) {
2022 *ep
->reg_udccs
= UDCCS_BO_RPC
;
2028 completed
= read_fifo(ep
, req
);
2030 pio_irq_disable (ep
->bEndpointAddress
);
2033 } while (completed
);
2037 * pxa2xx_udc_irq - interrupt handler
2039 * avoid delays in ep0 processing. the control handshaking isn't always
2040 * under software control (pxa250c0 and the pxa255 are better), and delays
2041 * could cause usb protocol errors.
2044 pxa2xx_udc_irq(int irq
, void *_dev
, struct pt_regs
*r
)
2046 struct pxa2xx_udc
*dev
= _dev
;
2050 HEX_DISPLAY(dev
->stats
.irqs
);
2056 /* SUSpend Interrupt Request */
2057 if (unlikely(udccr
& UDCCR_SUSIR
)) {
2058 udc_ack_int_UDCCR(UDCCR_SUSIR
);
2060 DBG(DBG_VERBOSE
, "USB suspend%s\n", is_vbus_present()
2061 ? "" : "+disconnect");
2063 if (!is_vbus_present())
2064 stop_activity(dev
, dev
->driver
);
2065 else if (dev
->gadget
.speed
!= USB_SPEED_UNKNOWN
2067 && dev
->driver
->suspend
)
2068 dev
->driver
->suspend(&dev
->gadget
);
2072 /* RESume Interrupt Request */
2073 if (unlikely(udccr
& UDCCR_RESIR
)) {
2074 udc_ack_int_UDCCR(UDCCR_RESIR
);
2076 DBG(DBG_VERBOSE
, "USB resume\n");
2078 if (dev
->gadget
.speed
!= USB_SPEED_UNKNOWN
2080 && dev
->driver
->resume
2081 && is_vbus_present())
2082 dev
->driver
->resume(&dev
->gadget
);
2085 /* ReSeT Interrupt Request - USB reset */
2086 if (unlikely(udccr
& UDCCR_RSTIR
)) {
2087 udc_ack_int_UDCCR(UDCCR_RSTIR
);
2090 if ((UDCCR
& UDCCR_UDA
) == 0) {
2091 DBG(DBG_VERBOSE
, "USB reset start\n");
2093 /* reset driver and endpoints,
2094 * in case that's not yet done
2096 stop_activity (dev
, dev
->driver
);
2099 DBG(DBG_VERBOSE
, "USB reset end\n");
2100 dev
->gadget
.speed
= USB_SPEED_FULL
;
2102 memset(&dev
->stats
, 0, sizeof dev
->stats
);
2103 /* driver and endpoints are still reset */
2107 u32 usir0
= USIR0
& ~UICR0
;
2108 u32 usir1
= USIR1
& ~UICR1
;
2111 if (unlikely (!usir0
&& !usir1
))
2114 DBG(DBG_VERY_NOISY
, "irq %02x.%02x\n", usir1
, usir0
);
2116 /* control traffic */
2117 if (usir0
& USIR0_IR0
) {
2118 dev
->ep
[0].pio_irqs
++;
2123 /* endpoint data transfers */
2124 for (i
= 0; i
< 8; i
++) {
2127 if (i
&& (usir0
& tmp
)) {
2128 handle_ep(&dev
->ep
[i
]);
2133 handle_ep(&dev
->ep
[i
+8]);
2140 /* we could also ask for 1 msec SOF (SIR) interrupts */
2146 /*-------------------------------------------------------------------------*/
2148 static void nop_release (struct device
*dev
)
2150 DMSG("%s %s\n", __FUNCTION__
, dev
->bus_id
);
2153 /* this uses load-time allocation and initialization (instead of
2154 * doing it at run-time) to save code, eliminate fault paths, and
2155 * be more obviously correct.
2157 static struct pxa2xx_udc memory
= {
2159 .ops
= &pxa2xx_udc_ops
,
2160 .ep0
= &memory
.ep
[0].ep
,
2161 .name
= driver_name
,
2164 .release
= nop_release
,
2168 /* control endpoint */
2172 .ops
= &pxa2xx_ep_ops
,
2173 .maxpacket
= EP0_FIFO_SIZE
,
2176 .reg_udccs
= &UDCCS0
,
2180 /* first group of endpoints */
2183 .name
= "ep1in-bulk",
2184 .ops
= &pxa2xx_ep_ops
,
2185 .maxpacket
= BULK_FIFO_SIZE
,
2188 .fifo_size
= BULK_FIFO_SIZE
,
2189 .bEndpointAddress
= USB_DIR_IN
| 1,
2190 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2191 .reg_udccs
= &UDCCS1
,
2197 .name
= "ep2out-bulk",
2198 .ops
= &pxa2xx_ep_ops
,
2199 .maxpacket
= BULK_FIFO_SIZE
,
2202 .fifo_size
= BULK_FIFO_SIZE
,
2203 .bEndpointAddress
= 2,
2204 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2205 .reg_udccs
= &UDCCS2
,
2210 #ifndef CONFIG_USB_PXA2XX_SMALL
2213 .name
= "ep3in-iso",
2214 .ops
= &pxa2xx_ep_ops
,
2215 .maxpacket
= ISO_FIFO_SIZE
,
2218 .fifo_size
= ISO_FIFO_SIZE
,
2219 .bEndpointAddress
= USB_DIR_IN
| 3,
2220 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2221 .reg_udccs
= &UDCCS3
,
2227 .name
= "ep4out-iso",
2228 .ops
= &pxa2xx_ep_ops
,
2229 .maxpacket
= ISO_FIFO_SIZE
,
2232 .fifo_size
= ISO_FIFO_SIZE
,
2233 .bEndpointAddress
= 4,
2234 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2235 .reg_udccs
= &UDCCS4
,
2242 .name
= "ep5in-int",
2243 .ops
= &pxa2xx_ep_ops
,
2244 .maxpacket
= INT_FIFO_SIZE
,
2247 .fifo_size
= INT_FIFO_SIZE
,
2248 .bEndpointAddress
= USB_DIR_IN
| 5,
2249 .bmAttributes
= USB_ENDPOINT_XFER_INT
,
2250 .reg_udccs
= &UDCCS5
,
2254 /* second group of endpoints */
2257 .name
= "ep6in-bulk",
2258 .ops
= &pxa2xx_ep_ops
,
2259 .maxpacket
= BULK_FIFO_SIZE
,
2262 .fifo_size
= BULK_FIFO_SIZE
,
2263 .bEndpointAddress
= USB_DIR_IN
| 6,
2264 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2265 .reg_udccs
= &UDCCS6
,
2271 .name
= "ep7out-bulk",
2272 .ops
= &pxa2xx_ep_ops
,
2273 .maxpacket
= BULK_FIFO_SIZE
,
2276 .fifo_size
= BULK_FIFO_SIZE
,
2277 .bEndpointAddress
= 7,
2278 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2279 .reg_udccs
= &UDCCS7
,
2286 .name
= "ep8in-iso",
2287 .ops
= &pxa2xx_ep_ops
,
2288 .maxpacket
= ISO_FIFO_SIZE
,
2291 .fifo_size
= ISO_FIFO_SIZE
,
2292 .bEndpointAddress
= USB_DIR_IN
| 8,
2293 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2294 .reg_udccs
= &UDCCS8
,
2300 .name
= "ep9out-iso",
2301 .ops
= &pxa2xx_ep_ops
,
2302 .maxpacket
= ISO_FIFO_SIZE
,
2305 .fifo_size
= ISO_FIFO_SIZE
,
2306 .bEndpointAddress
= 9,
2307 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2308 .reg_udccs
= &UDCCS9
,
2315 .name
= "ep10in-int",
2316 .ops
= &pxa2xx_ep_ops
,
2317 .maxpacket
= INT_FIFO_SIZE
,
2320 .fifo_size
= INT_FIFO_SIZE
,
2321 .bEndpointAddress
= USB_DIR_IN
| 10,
2322 .bmAttributes
= USB_ENDPOINT_XFER_INT
,
2323 .reg_udccs
= &UDCCS10
,
2324 .reg_uddr
= &UDDR10
,
2327 /* third group of endpoints */
2330 .name
= "ep11in-bulk",
2331 .ops
= &pxa2xx_ep_ops
,
2332 .maxpacket
= BULK_FIFO_SIZE
,
2335 .fifo_size
= BULK_FIFO_SIZE
,
2336 .bEndpointAddress
= USB_DIR_IN
| 11,
2337 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2338 .reg_udccs
= &UDCCS11
,
2339 .reg_uddr
= &UDDR11
,
2344 .name
= "ep12out-bulk",
2345 .ops
= &pxa2xx_ep_ops
,
2346 .maxpacket
= BULK_FIFO_SIZE
,
2349 .fifo_size
= BULK_FIFO_SIZE
,
2350 .bEndpointAddress
= 12,
2351 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2352 .reg_udccs
= &UDCCS12
,
2353 .reg_ubcr
= &UBCR12
,
2354 .reg_uddr
= &UDDR12
,
2359 .name
= "ep13in-iso",
2360 .ops
= &pxa2xx_ep_ops
,
2361 .maxpacket
= ISO_FIFO_SIZE
,
2364 .fifo_size
= ISO_FIFO_SIZE
,
2365 .bEndpointAddress
= USB_DIR_IN
| 13,
2366 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2367 .reg_udccs
= &UDCCS13
,
2368 .reg_uddr
= &UDDR13
,
2373 .name
= "ep14out-iso",
2374 .ops
= &pxa2xx_ep_ops
,
2375 .maxpacket
= ISO_FIFO_SIZE
,
2378 .fifo_size
= ISO_FIFO_SIZE
,
2379 .bEndpointAddress
= 14,
2380 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2381 .reg_udccs
= &UDCCS14
,
2382 .reg_ubcr
= &UBCR14
,
2383 .reg_uddr
= &UDDR14
,
2388 .name
= "ep15in-int",
2389 .ops
= &pxa2xx_ep_ops
,
2390 .maxpacket
= INT_FIFO_SIZE
,
2393 .fifo_size
= INT_FIFO_SIZE
,
2394 .bEndpointAddress
= USB_DIR_IN
| 15,
2395 .bmAttributes
= USB_ENDPOINT_XFER_INT
,
2396 .reg_udccs
= &UDCCS15
,
2397 .reg_uddr
= &UDDR15
,
2399 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2402 #define CP15R0_VENDOR_MASK 0xffffe000
2404 #if defined(CONFIG_ARCH_PXA)
2405 #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */
2407 #elif defined(CONFIG_ARCH_IXP4XX)
2408 #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */
2412 #define CP15R0_PROD_MASK 0x000003f0
2413 #define PXA25x 0x00000100 /* and PXA26x */
2414 #define PXA210 0x00000120
2416 #define CP15R0_REV_MASK 0x0000000f
2418 #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2420 #define PXA255_A0 0x00000106 /* or PXA260_B1 */
2421 #define PXA250_C0 0x00000105 /* or PXA26x_B0 */
2422 #define PXA250_B2 0x00000104
2423 #define PXA250_B1 0x00000103 /* or PXA260_A0 */
2424 #define PXA250_B0 0x00000102
2425 #define PXA250_A1 0x00000101
2426 #define PXA250_A0 0x00000100
2428 #define PXA210_C0 0x00000125
2429 #define PXA210_B2 0x00000124
2430 #define PXA210_B1 0x00000123
2431 #define PXA210_B0 0x00000122
2432 #define IXP425_A0 0x000001c1
2433 #define IXP465_AD 0x00000200
2436 * probe - binds to the platform device
2438 static int __init
pxa2xx_udc_probe(struct platform_device
*pdev
)
2440 struct pxa2xx_udc
*dev
= &memory
;
2441 int retval
, out_dma
= 1;
2444 /* insist on Intel/ARM/XScale */
2445 asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev
));
2446 if ((chiprev
& CP15R0_VENDOR_MASK
) != CP15R0_XSCALE_VALUE
) {
2447 printk(KERN_ERR
"%s: not XScale!\n", driver_name
);
2451 /* trigger chiprev-specific logic */
2452 switch (chiprev
& CP15R0_PRODREV_MASK
) {
2453 #if defined(CONFIG_ARCH_PXA)
2459 /* A0/A1 "not released"; ep 13, 15 unusable */
2461 case PXA250_B2
: case PXA210_B2
:
2462 case PXA250_B1
: case PXA210_B1
:
2463 case PXA250_B0
: case PXA210_B0
:
2466 case PXA250_C0
: case PXA210_C0
:
2468 #elif defined(CONFIG_ARCH_IXP4XX)
2477 printk(KERN_ERR
"%s: unrecognized processor: %08x\n",
2478 driver_name
, chiprev
);
2479 /* iop3xx, ixp4xx, ... */
2483 pr_debug("%s: IRQ %d%s%s%s\n", driver_name
, IRQ_USB
,
2484 dev
->has_cfr
? "" : " (!cfr)",
2485 out_dma
? "" : " (broken dma-out)",
2493 /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2495 DMSG("disabled OUT dma\n");
2496 dev
->ep
[ 2].reg_drcmr
= dev
->ep
[ 4].reg_drcmr
= 0;
2497 dev
->ep
[ 7].reg_drcmr
= dev
->ep
[ 9].reg_drcmr
= 0;
2498 dev
->ep
[12].reg_drcmr
= dev
->ep
[14].reg_drcmr
= 0;
2502 /* other non-static parts of init */
2503 dev
->dev
= &pdev
->dev
;
2504 dev
->mach
= pdev
->dev
.platform_data
;
2506 init_timer(&dev
->timer
);
2507 dev
->timer
.function
= udc_watchdog
;
2508 dev
->timer
.data
= (unsigned long) dev
;
2510 device_initialize(&dev
->gadget
.dev
);
2511 dev
->gadget
.dev
.parent
= &pdev
->dev
;
2512 dev
->gadget
.dev
.dma_mask
= pdev
->dev
.dma_mask
;
2514 the_controller
= dev
;
2515 platform_set_drvdata(pdev
, dev
);
2520 dev
->vbus
= is_vbus_present();
2522 /* irq setup after old hardware state is cleaned up */
2523 retval
= request_irq(IRQ_USB
, pxa2xx_udc_irq
,
2524 IRQF_DISABLED
, driver_name
, dev
);
2526 printk(KERN_ERR
"%s: can't get irq %i, err %d\n",
2527 driver_name
, IRQ_USB
, retval
);
2532 #ifdef CONFIG_ARCH_LUBBOCK
2533 if (machine_is_lubbock()) {
2534 retval
= request_irq(LUBBOCK_USB_DISC_IRQ
,
2536 IRQF_DISABLED
| IRQF_SAMPLE_RANDOM
,
2539 printk(KERN_ERR
"%s: can't get irq %i, err %d\n",
2540 driver_name
, LUBBOCK_USB_DISC_IRQ
, retval
);
2542 free_irq(IRQ_USB
, dev
);
2545 retval
= request_irq(LUBBOCK_USB_IRQ
,
2547 IRQF_DISABLED
| IRQF_SAMPLE_RANDOM
,
2550 printk(KERN_ERR
"%s: can't get irq %i, err %d\n",
2551 driver_name
, LUBBOCK_USB_IRQ
, retval
);
2552 free_irq(LUBBOCK_USB_DISC_IRQ
, dev
);
2556 /* with U-Boot (but not BLOB), hex is off by default */
2557 HEX_DISPLAY(dev
->stats
.irqs
);
2558 LUB_DISC_BLNK_LED
&= 0xff;
2562 create_proc_files();
2567 static void pxa2xx_udc_shutdown(struct platform_device
*_dev
)
2572 static int __exit
pxa2xx_udc_remove(struct platform_device
*pdev
)
2574 struct pxa2xx_udc
*dev
= platform_get_drvdata(pdev
);
2577 remove_proc_files();
2578 usb_gadget_unregister_driver(dev
->driver
);
2581 free_irq(IRQ_USB
, dev
);
2584 #ifdef CONFIG_ARCH_LUBBOCK
2585 if (machine_is_lubbock()) {
2586 free_irq(LUBBOCK_USB_DISC_IRQ
, dev
);
2587 free_irq(LUBBOCK_USB_IRQ
, dev
);
2590 platform_set_drvdata(pdev
, NULL
);
2591 the_controller
= NULL
;
2595 /*-------------------------------------------------------------------------*/
2599 /* USB suspend (controlled by the host) and system suspend (controlled
2600 * by the PXA) don't necessarily work well together. If USB is active,
2601 * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2602 * mode, or any deeper PM saving state.
2604 * For now, we punt and forcibly disconnect from the USB host when PXA
2605 * enters any suspend state. While we're disconnected, we always disable
2606 * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2607 * Boards without software pullup control shouldn't use those states.
2608 * VBUS IRQs should probably be ignored so that the PXA device just acts
2609 * "dead" to USB hosts until system resume.
2611 static int pxa2xx_udc_suspend(struct platform_device
*dev
, pm_message_t state
)
2613 struct pxa2xx_udc
*udc
= platform_get_drvdata(dev
);
2615 if (!udc
->mach
->udc_command
)
2616 WARN("USB host won't detect disconnect!\n");
2622 static int pxa2xx_udc_resume(struct platform_device
*dev
)
2624 struct pxa2xx_udc
*udc
= platform_get_drvdata(dev
);
2632 #define pxa2xx_udc_suspend NULL
2633 #define pxa2xx_udc_resume NULL
2636 /*-------------------------------------------------------------------------*/
2638 static struct platform_driver udc_driver
= {
2639 .probe
= pxa2xx_udc_probe
,
2640 .shutdown
= pxa2xx_udc_shutdown
,
2641 .remove
= __exit_p(pxa2xx_udc_remove
),
2642 .suspend
= pxa2xx_udc_suspend
,
2643 .resume
= pxa2xx_udc_resume
,
2645 .owner
= THIS_MODULE
,
2646 .name
= "pxa2xx-udc",
2650 static int __init
udc_init(void)
2652 printk(KERN_INFO
"%s: version %s\n", driver_name
, DRIVER_VERSION
);
2653 return platform_driver_register(&udc_driver
);
2655 module_init(udc_init
);
2657 static void __exit
udc_exit(void)
2659 platform_driver_unregister(&udc_driver
);
2661 module_exit(udc_exit
);
2663 MODULE_DESCRIPTION(DRIVER_DESC
);
2664 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2665 MODULE_LICENSE("GPL");