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[linux-2.6/linux-mips.git] / drivers / serial / sunzilog.c
blob8a5bcd6e19b3121dcae1d46b327f4cf757ef718b
1 /*
2 * sunzilog.c
3 *
4 * Driver for Zilog serial chips found on Sun workstations and
5 * servers. This driver could actually be made more generic.
6 *
7 * This is based on the old drivers/sbus/char/zs.c code. A lot
8 * of code has been simply moved over directly from there but
9 * much has been rewritten. Credits therefore go out to Eddie
10 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
11 * work there.
12 *
13 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
14 */
15
16 #include <linux/config.h>
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/tty.h>
23 #include <linux/tty_flip.h>
24 #include <linux/major.h>
25 #include <linux/string.h>
26 #include <linux/ptrace.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/circ_buf.h>
30 #include <linux/serial.h>
31 #include <linux/console.h>
32 #include <linux/spinlock.h>
33 #ifdef CONFIG_SERIO
34 #include <linux/serio.h>
35 #endif
36 #include <linux/init.h>
37
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #ifdef CONFIG_SPARC64
41 #include <asm/fhc.h>
42 #endif
43 #include <asm/sbus.h>
44
45 #include <linux/serial_core.h>
46
47 #include "suncore.h"
48 #include "sunzilog.h"
49
50 /* On 32-bit sparcs we need to delay after register accesses
51 * to accommodate sun4 systems, but we do not need to flush writes.
52 * On 64-bit sparc we only need to flush single writes to ensure
53 * completion.
54 */
55 #ifndef CONFIG_SPARC64
56 #define ZSDELAY() udelay(5)
57 #define ZSDELAY_LONG() udelay(20)
58 #define ZS_WSYNC(channel) do { } while (0)
59 #else
60 #define ZSDELAY()
61 #define ZSDELAY_LONG()
62 #define ZS_WSYNC(__channel) \
63 sbus_readb(&((__channel)->control))
64 #endif
65
66 static int num_sunzilog;
67 #define NUM_SUNZILOG num_sunzilog
68 #define NUM_CHANNELS (NUM_SUNZILOG * 2)
69
70 #define KEYBOARD_LINE 0x2
71 #define MOUSE_LINE 0x3
72
73 #define ZS_CLOCK 4915200 /* Zilog input clock rate. */
74 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
75
76 /*
77 * We wrap our port structure around the generic uart_port.
78 */
79 struct uart_sunzilog_port {
80 struct uart_port port;
81
82 /* IRQ servicing chain. */
83 struct uart_sunzilog_port *next;
84
85 /* Current values of Zilog write registers. */
86 unsigned char curregs[NUM_ZSREGS];
87
88 unsigned int flags;
89 #define SUNZILOG_FLAG_CONS_KEYB 0x00000001
90 #define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
91 #define SUNZILOG_FLAG_IS_CONS 0x00000004
92 #define SUNZILOG_FLAG_IS_KGDB 0x00000008
93 #define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
94 #define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
95 #define SUNZILOG_FLAG_REGS_HELD 0x00000040
96 #define SUNZILOG_FLAG_TX_STOPPED 0x00000080
97 #define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
98
99 unsigned int cflag;
100
101 /* L1-A keyboard break state. */
102 int kbd_id;
103 int l1_down;
104
105 unsigned char parity_mask;
106 unsigned char prev_status;
107
108 #ifdef CONFIG_SERIO
109 struct serio serio;
110 #endif
111 };
112
113 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
114 #define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
115
116 #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
117 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
118 #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
119 #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
120 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
121 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
122 #define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
123 #define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
124 #define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
125
126 /* Reading and writing Zilog8530 registers. The delays are to make this
127 * driver work on the Sun4 which needs a settling delay after each chip
128 * register access, other machines handle this in hardware via auxiliary
129 * flip-flops which implement the settle time we do in software.
130 *
131 * The port lock must be held and local IRQs must be disabled
132 * when {read,write}_zsreg is invoked.
133 */
134 static unsigned char read_zsreg(struct zilog_channel *channel,
135 unsigned char reg)
136 {
137 unsigned char retval;
138
139 sbus_writeb(reg, &channel->control);
140 ZSDELAY();
141 retval = sbus_readb(&channel->control);
142 ZSDELAY();
143
144 return retval;
145 }
146
147 static void write_zsreg(struct zilog_channel *channel,
148 unsigned char reg, unsigned char value)
149 {
150 sbus_writeb(reg, &channel->control);
151 ZSDELAY();
152 sbus_writeb(value, &channel->control);
153 ZSDELAY();
154 }
155
156 static void sunzilog_clear_fifo(struct zilog_channel *channel)
157 {
158 int i;
159
160 for (i = 0; i < 32; i++) {
161 unsigned char regval;
162
163 regval = sbus_readb(&channel->control);
164 ZSDELAY();
165 if (regval & Rx_CH_AV)
166 break;
167
168 regval = read_zsreg(channel, R1);
169 sbus_readb(&channel->data);
170 ZSDELAY();
171
172 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
173 sbus_writeb(ERR_RES, &channel->control);
174 ZSDELAY();
175 ZS_WSYNC(channel);
176 }
177 }
178 }
179
180 /* This function must only be called when the TX is not busy. The UART
181 * port lock must be held and local interrupts disabled.
182 */
183 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
184 {
185 int i;
186
187 /* Let pending transmits finish. */
188 for (i = 0; i < 1000; i++) {
189 unsigned char stat = read_zsreg(channel, R1);
190 if (stat & ALL_SNT)
191 break;
192 udelay(100);
193 }
194
195 sbus_writeb(ERR_RES, &channel->control);
196 ZSDELAY();
197 ZS_WSYNC(channel);
198
199 sunzilog_clear_fifo(channel);
200
201 /* Disable all interrupts. */
202 write_zsreg(channel, R1,
203 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
204
205 /* Set parity, sync config, stop bits, and clock divisor. */
206 write_zsreg(channel, R4, regs[R4]);
207
208 /* Set misc. TX/RX control bits. */
209 write_zsreg(channel, R10, regs[R10]);
210
211 /* Set TX/RX controls sans the enable bits. */
212 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
213 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
214
215 /* Synchronous mode config. */
216 write_zsreg(channel, R6, regs[R6]);
217 write_zsreg(channel, R7, regs[R7]);
218
219 /* Don't mess with the interrupt vector (R2, unused by us) and
220 * master interrupt control (R9). We make sure this is setup
221 * properly at probe time then never touch it again.
222 */
223
224 /* Disable baud generator. */
225 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
226
227 /* Clock mode control. */
228 write_zsreg(channel, R11, regs[R11]);
229
230 /* Lower and upper byte of baud rate generator divisor. */
231 write_zsreg(channel, R12, regs[R12]);
232 write_zsreg(channel, R13, regs[R13]);
233
234 /* Now rewrite R14, with BRENAB (if set). */
235 write_zsreg(channel, R14, regs[R14]);
236
237 /* External status interrupt control. */
238 write_zsreg(channel, R15, regs[R15]);
239
240 /* Reset external status interrupts. */
241 write_zsreg(channel, R0, RES_EXT_INT);
242 write_zsreg(channel, R0, RES_EXT_INT);
243
244 /* Rewrite R3/R5, this time without enables masked. */
245 write_zsreg(channel, R3, regs[R3]);
246 write_zsreg(channel, R5, regs[R5]);
247
248 /* Rewrite R1, this time without IRQ enabled masked. */
249 write_zsreg(channel, R1, regs[R1]);
250 }
251
252 /* Reprogram the Zilog channel HW registers with the copies found in the
253 * software state struct. If the transmitter is busy, we defer this update
254 * until the next TX complete interrupt. Else, we do it right now.
255 *
256 * The UART port lock must be held and local interrupts disabled.
257 */
258 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
259 struct zilog_channel *channel)
260 {
261 if (!ZS_REGS_HELD(up)) {
262 if (ZS_TX_ACTIVE(up)) {
263 up->flags |= SUNZILOG_FLAG_REGS_HELD;
264 } else {
265 __load_zsregs(channel, up->curregs);
266 }
267 }
268 }
269
270 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
271 {
272 unsigned int cur_cflag = up->cflag;
273 int brg, new_baud;
274
275 up->cflag &= ~CBAUD;
276 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
277
278 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
279 up->curregs[R12] = (brg & 0xff);
280 up->curregs[R13] = (brg >> 8) & 0xff;
281 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
282 }
283
284 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
285 unsigned char ch, int is_break,
286 struct pt_regs *regs)
287 {
288 if (ZS_IS_KEYB(up)) {
289 if (ch == SUNKBD_RESET) {
290 up->kbd_id = 1;
291 up->l1_down = 0;
292 } else if (up->kbd_id) {
293 up->kbd_id = 0;
294 } else if (ch == SUNKBD_L1) {
295 up->l1_down = 1;
296 } else if (ch == (SUNKBD_L1 | SUNKBD_UP)) {
297 up->l1_down = 0;
298 } else if (ch == SUNKBD_A && up->l1_down) {
299 sun_do_break();
300 up->l1_down = 0;
301 up->kbd_id = 0;
302 return;
303 }
304 #ifdef CONFIG_SERIO
305 serio_interrupt(&up->serio, ch, 0, regs);
306 #endif
307 } else if (ZS_IS_MOUSE(up)) {
308 int ret = suncore_mouse_baud_detection(ch, is_break);
309
310 switch (ret) {
311 case 2:
312 sunzilog_change_mouse_baud(up);
313 /* fallthru */
314 case 1:
315 break;
316
317 case 0:
318 #ifdef CONFIG_SERIO
319 serio_interrupt(&up->serio, ch, 0, regs);
320 #endif
321 break;
322 };
323 }
324 }
325
326 static void sunzilog_receive_chars(struct uart_sunzilog_port *up,
327 struct zilog_channel *channel,
328 struct pt_regs *regs)
329 {
330 struct tty_struct *tty = up->port.info->tty; /* XXX info==NULL? */
331
332 while (1) {
333 unsigned char ch, r1;
334
335 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
336 tty->flip.work.func((void *)tty);
337 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
338 return; /* XXX Ignores SysRq when we need it most. Fix. */
339 }
340
341 r1 = read_zsreg(channel, R1);
342 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
343 sbus_writeb(ERR_RES, &channel->control);
344 ZSDELAY();
345 ZS_WSYNC(channel);
346 }
347
348 ch = sbus_readb(&channel->control);
349 ZSDELAY();
350
351 /* This funny hack depends upon BRK_ABRT not interfering
352 * with the other bits we care about in R1.
353 */
354 if (ch & BRK_ABRT)
355 r1 |= BRK_ABRT;
356
357 ch = sbus_readb(&channel->data);
358 ZSDELAY();
359
360 ch &= up->parity_mask;
361
362 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
363 sunzilog_kbdms_receive_chars(up, ch, 0, regs);
364 goto next_char;
365 }
366
367 if (ZS_IS_CONS(up) && (r1 & BRK_ABRT)) {
368 /* Wait for BREAK to deassert to avoid potentially
369 * confusing the PROM.
370 */
371 while (1) {
372 ch = sbus_readb(&channel->control);
373 ZSDELAY();
374 if (!(ch & BRK_ABRT))
375 break;
376 }
377 sun_do_break();
378 return;
379 }
380
381 /* A real serial line, record the character and status. */
382 *tty->flip.char_buf_ptr = ch;
383 *tty->flip.flag_buf_ptr = TTY_NORMAL;
384 up->port.icount.rx++;
385 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
386 if (r1 & BRK_ABRT) {
387 r1 &= ~(PAR_ERR | CRC_ERR);
388 up->port.icount.brk++;
389 if (uart_handle_break(&up->port))
390 goto next_char;
391 }
392 else if (r1 & PAR_ERR)
393 up->port.icount.parity++;
394 else if (r1 & CRC_ERR)
395 up->port.icount.frame++;
396 if (r1 & Rx_OVR)
397 up->port.icount.overrun++;
398 r1 &= up->port.read_status_mask;
399 if (r1 & BRK_ABRT)
400 *tty->flip.flag_buf_ptr = TTY_BREAK;
401 else if (r1 & PAR_ERR)
402 *tty->flip.flag_buf_ptr = TTY_PARITY;
403 else if (r1 & CRC_ERR)
404 *tty->flip.flag_buf_ptr = TTY_FRAME;
405 }
406 if (uart_handle_sysrq_char(&up->port, ch, regs))
407 goto next_char;
408
409 if (up->port.ignore_status_mask == 0xff ||
410 (r1 & up->port.ignore_status_mask) == 0) {
411 tty->flip.flag_buf_ptr++;
412 tty->flip.char_buf_ptr++;
413 tty->flip.count++;
414 }
415 if ((r1 & Rx_OVR) &&
416 tty->flip.count < TTY_FLIPBUF_SIZE) {
417 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
418 tty->flip.flag_buf_ptr++;
419 tty->flip.char_buf_ptr++;
420 tty->flip.count++;
421 }
422 next_char:
423 ch = sbus_readb(&channel->control);
424 ZSDELAY();
425 if (!(ch & Rx_CH_AV))
426 break;
427 }
428
429 tty_flip_buffer_push(tty);
430 }
431
432 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
433 struct zilog_channel *channel,
434 struct pt_regs *regs)
435 {
436 unsigned char status;
437
438 status = sbus_readb(&channel->control);
439 ZSDELAY();
440
441 sbus_writeb(RES_EXT_INT, &channel->control);
442 ZSDELAY();
443 ZS_WSYNC(channel);
444
445 if ((status & BRK_ABRT) && ZS_IS_MOUSE(up))
446 sunzilog_kbdms_receive_chars(up, 0, 1, regs);
447
448 if (ZS_WANTS_MODEM_STATUS(up)) {
449 if (status & SYNC)
450 up->port.icount.dsr++;
451
452 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
453 * But it does not tell us which bit has changed, we have to keep
454 * track of this ourselves.
455 */
456 if ((status & DCD) ^ up->prev_status)
457 uart_handle_dcd_change(&up->port,
458 (status & DCD));
459 if ((status & CTS) ^ up->prev_status)
460 uart_handle_cts_change(&up->port,
461 (status & CTS));
462
463 wake_up_interruptible(&up->port.info->delta_msr_wait);
464 }
465
466 up->prev_status = status;
467 }
468
469 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
470 struct zilog_channel *channel)
471 {
472 struct circ_buf *xmit;
473
474 if (ZS_IS_CONS(up)) {
475 unsigned char status = sbus_readb(&channel->control);
476 ZSDELAY();
477
478 /* TX still busy? Just wait for the next TX done interrupt.
479 *
480 * It can occur because of how we do serial console writes. It would
481 * be nice to transmit console writes just like we normally would for
482 * a TTY line. (ie. buffered and TX interrupt driven). That is not
483 * easy because console writes cannot sleep. One solution might be
484 * to poll on enough port->xmit space becomming free. -DaveM
485 */
486 if (!(status & Tx_BUF_EMP))
487 return;
488 }
489
490 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
491
492 if (ZS_REGS_HELD(up)) {
493 __load_zsregs(channel, up->curregs);
494 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
495 }
496
497 if (ZS_TX_STOPPED(up)) {
498 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
499 goto ack_tx_int;
500 }
501
502 if (up->port.x_char) {
503 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
504 sbus_writeb(up->port.x_char, &channel->data);
505 ZSDELAY();
506 ZS_WSYNC(channel);
507
508 up->port.icount.tx++;
509 up->port.x_char = 0;
510 return;
511 }
512
513 if (up->port.info == NULL)
514 goto ack_tx_int;
515 xmit = &up->port.info->xmit;
516 if (uart_circ_empty(xmit)) {
517 uart_write_wakeup(&up->port);
518 goto ack_tx_int;
519 }
520 if (uart_tx_stopped(&up->port))
521 goto ack_tx_int;
522
523 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
524 sbus_writeb(xmit->buf[xmit->tail], &channel->data);
525 ZSDELAY();
526 ZS_WSYNC(channel);
527
528 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
529 up->port.icount.tx++;
530
531 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
532 uart_write_wakeup(&up->port);
533
534 return;
535
536 ack_tx_int:
537 sbus_writeb(RES_Tx_P, &channel->control);
538 ZSDELAY();
539 ZS_WSYNC(channel);
540 }
541
542 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
543 {
544 struct uart_sunzilog_port *up = dev_id;
545
546 while (up) {
547 struct zilog_channel *channel
548 = ZILOG_CHANNEL_FROM_PORT(&up->port);
549 unsigned char r3;
550
551 spin_lock(&up->port.lock);
552 r3 = read_zsreg(channel, R3);
553
554 /* Channel A */
555 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
556 sbus_writeb(RES_H_IUS, &channel->control);
557 ZSDELAY();
558 ZS_WSYNC(channel);
559
560 if (r3 & CHARxIP)
561 sunzilog_receive_chars(up, channel, regs);
562 if (r3 & CHAEXT)
563 sunzilog_status_handle(up, channel, regs);
564 if (r3 & CHATxIP)
565 sunzilog_transmit_chars(up, channel);
566 }
567 spin_unlock(&up->port.lock);
568
569 /* Channel B */
570 up = up->next;
571 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
572
573 spin_lock(&up->port.lock);
574 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
575 sbus_writeb(RES_H_IUS, &channel->control);
576 ZSDELAY();
577 ZS_WSYNC(channel);
578
579 if (r3 & CHBRxIP)
580 sunzilog_receive_chars(up, channel, regs);
581 if (r3 & CHBEXT)
582 sunzilog_status_handle(up, channel, regs);
583 if (r3 & CHBTxIP)
584 sunzilog_transmit_chars(up, channel);
585 }
586 spin_unlock(&up->port.lock);
587
588 up = up->next;
589 }
590
591 return IRQ_HANDLED;
592 }
593
594 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
595 * port lock, it is acquired here.
596 */
597 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
598 {
599 struct zilog_channel *channel;
600 unsigned long flags;
601 unsigned char status;
602
603 spin_lock_irqsave(&port->lock, flags);
604
605 channel = ZILOG_CHANNEL_FROM_PORT(port);
606 status = sbus_readb(&channel->control);
607 ZSDELAY();
608
609 spin_unlock_irqrestore(&port->lock, flags);
610
611 return status;
612 }
613
614 /* The port lock is not held. */
615 static unsigned int sunzilog_tx_empty(struct uart_port *port)
616 {
617 unsigned char status;
618 unsigned int ret;
619
620 status = sunzilog_read_channel_status(port);
621 if (status & Tx_BUF_EMP)
622 ret = TIOCSER_TEMT;
623 else
624 ret = 0;
625
626 return ret;
627 }
628
629 /* The port lock is not held. */
630 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
631 {
632 unsigned char status;
633 unsigned int ret;
634
635 status = sunzilog_read_channel_status(port);
636
637 ret = 0;
638 if (status & DCD)
639 ret |= TIOCM_CAR;
640 if (status & SYNC)
641 ret |= TIOCM_DSR;
642 if (status & CTS)
643 ret |= TIOCM_CTS;
644
645 return ret;
646 }
647
648 /* The port lock is held and interrupts are disabled. */
649 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
650 {
651 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
652 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
653 unsigned char set_bits, clear_bits;
654
655 set_bits = clear_bits = 0;
656
657 if (mctrl & TIOCM_RTS)
658 set_bits |= RTS;
659 else
660 clear_bits |= RTS;
661 if (mctrl & TIOCM_DTR)
662 set_bits |= DTR;
663 else
664 clear_bits |= DTR;
665
666 /* NOTE: Not subject to 'transmitter active' rule. */
667 up->curregs[R5] |= set_bits;
668 up->curregs[R5] &= ~clear_bits;
669 write_zsreg(channel, R5, up->curregs[R5]);
670 }
671
672 /* The port lock is held and interrupts are disabled. */
673 static void sunzilog_stop_tx(struct uart_port *port, unsigned int tty_stop)
674 {
675 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
676
677 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
678 }
679
680 /* The port lock is held and interrupts are disabled. */
681 static void sunzilog_start_tx(struct uart_port *port, unsigned int tty_start)
682 {
683 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
684 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
685 unsigned char status;
686
687 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
688 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
689
690 status = sbus_readb(&channel->control);
691 ZSDELAY();
692
693 /* TX busy? Just wait for the TX done interrupt. */
694 if (!(status & Tx_BUF_EMP))
695 return;
696
697 /* Send the first character to jump-start the TX done
698 * IRQ sending engine.
699 */
700 if (port->x_char) {
701 sbus_writeb(port->x_char, &channel->data);
702 ZSDELAY();
703 ZS_WSYNC(channel);
704
705 port->icount.tx++;
706 port->x_char = 0;
707 } else {
708 struct circ_buf *xmit = &port->info->xmit;
709
710 sbus_writeb(xmit->buf[xmit->tail], &channel->data);
711 ZSDELAY();
712 ZS_WSYNC(channel);
713
714 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
715 port->icount.tx++;
716
717 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
718 uart_write_wakeup(&up->port);
719 }
720 }
721
722 /* The port lock is not held. */
723 static void sunzilog_stop_rx(struct uart_port *port)
724 {
725 struct uart_sunzilog_port *up = UART_ZILOG(port);
726 struct zilog_channel *channel;
727 unsigned long flags;
728
729 if (ZS_IS_CONS(up))
730 return;
731
732 spin_lock_irqsave(&port->lock, flags);
733
734 channel = ZILOG_CHANNEL_FROM_PORT(port);
735
736 /* Disable all RX interrupts. */
737 up->curregs[R1] &= ~RxINT_MASK;
738 sunzilog_maybe_update_regs(up, channel);
739
740 spin_unlock_irqrestore(&port->lock, flags);
741 }
742
743 /* The port lock is not held. */
744 static void sunzilog_enable_ms(struct uart_port *port)
745 {
746 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
747 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
748 unsigned char new_reg;
749 unsigned long flags;
750
751 spin_lock_irqsave(&port->lock, flags);
752
753 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
754 if (new_reg != up->curregs[R15]) {
755 up->curregs[R15] = new_reg;
756
757 /* NOTE: Not subject to 'transmitter active' rule. */
758 write_zsreg(channel, R15, up->curregs[R15]);
759 }
760
761 spin_unlock_irqrestore(&port->lock, flags);
762 }
763
764 /* The port lock is not held. */
765 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
766 {
767 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
768 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
769 unsigned char set_bits, clear_bits, new_reg;
770 unsigned long flags;
771
772 set_bits = clear_bits = 0;
773
774 if (break_state)
775 set_bits |= SND_BRK;
776 else
777 clear_bits |= SND_BRK;
778
779 spin_lock_irqsave(&port->lock, flags);
780
781 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
782 if (new_reg != up->curregs[R5]) {
783 up->curregs[R5] = new_reg;
784
785 /* NOTE: Not subject to 'transmitter active' rule. */
786 write_zsreg(channel, R5, up->curregs[R5]);
787 }
788
789 spin_unlock_irqrestore(&port->lock, flags);
790 }
791
792 static void __sunzilog_startup(struct uart_sunzilog_port *up)
793 {
794 struct zilog_channel *channel;
795
796 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
797 up->prev_status = sbus_readb(&channel->control);
798
799 /* Enable receiver and transmitter. */
800 up->curregs[R3] |= RxENAB;
801 up->curregs[R5] |= TxENAB;
802
803 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
804 sunzilog_maybe_update_regs(up, channel);
805 }
806
807 static int sunzilog_startup(struct uart_port *port)
808 {
809 struct uart_sunzilog_port *up = UART_ZILOG(port);
810 unsigned long flags;
811
812 if (ZS_IS_CONS(up))
813 return 0;
814
815 spin_lock_irqsave(&port->lock, flags);
816 __sunzilog_startup(up);
817 spin_unlock_irqrestore(&port->lock, flags);
818 return 0;
819 }
820
821 /*
822 * The test for ZS_IS_CONS is explained by the following e-mail:
823 *****
824 * From: Russell King <rmk@arm.linux.org.uk>
825 * Date: Sun, 8 Dec 2002 10:18:38 +0000
826 *
827 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
828 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
829 * > and I noticed that something is not right with reference
830 * > counting in this case. It seems that when the console
831 * > is open by kernel initially, this is not accounted
832 * > as an open, and uart_startup is not called.
833 *
834 * That is correct. We are unable to call uart_startup when the serial
835 * console is initialised because it may need to allocate memory (as
836 * request_irq does) and the memory allocators may not have been
837 * initialised.
838 *
839 * 1. initialise the port into a state where it can send characters in the
840 * console write method.
841 *
842 * 2. don't do the actual hardware shutdown in your shutdown() method (but
843 * do the normal software shutdown - ie, free irqs etc)
844 *****
845 */
846 static void sunzilog_shutdown(struct uart_port *port)
847 {
848 struct uart_sunzilog_port *up = UART_ZILOG(port);
849 struct zilog_channel *channel;
850 unsigned long flags;
851
852 if (ZS_IS_CONS(up))
853 return;
854
855 spin_lock_irqsave(&port->lock, flags);
856
857 channel = ZILOG_CHANNEL_FROM_PORT(port);
858
859 /* Disable receiver and transmitter. */
860 up->curregs[R3] &= ~RxENAB;
861 up->curregs[R5] &= ~TxENAB;
862
863 /* Disable all interrupts and BRK assertion. */
864 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
865 up->curregs[R5] &= ~SND_BRK;
866 sunzilog_maybe_update_regs(up, channel);
867
868 spin_unlock_irqrestore(&port->lock, flags);
869 }
870
871 /* Shared by TTY driver and serial console setup. The port lock is held
872 * and local interrupts are disabled.
873 */
874 static void
875 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
876 unsigned int iflag, int brg)
877 {
878
879 up->curregs[R10] = NRZ;
880 up->curregs[R11] = TCBR | RCBR;
881
882 /* Program BAUD and clock source. */
883 up->curregs[R4] &= ~XCLK_MASK;
884 up->curregs[R4] |= X16CLK;
885 up->curregs[R12] = brg & 0xff;
886 up->curregs[R13] = (brg >> 8) & 0xff;
887 up->curregs[R14] = BRSRC | BRENAB;
888
889 /* Character size, stop bits, and parity. */
890 up->curregs[3] &= ~RxN_MASK;
891 up->curregs[5] &= ~TxN_MASK;
892 switch (cflag & CSIZE) {
893 case CS5:
894 up->curregs[3] |= Rx5;
895 up->curregs[5] |= Tx5;
896 up->parity_mask = 0x1f;
897 break;
898 case CS6:
899 up->curregs[3] |= Rx6;
900 up->curregs[5] |= Tx6;
901 up->parity_mask = 0x3f;
902 break;
903 case CS7:
904 up->curregs[3] |= Rx7;
905 up->curregs[5] |= Tx7;
906 up->parity_mask = 0x7f;
907 break;
908 case CS8:
909 default:
910 up->curregs[3] |= Rx8;
911 up->curregs[5] |= Tx8;
912 up->parity_mask = 0xff;
913 break;
914 };
915 up->curregs[4] &= ~0x0c;
916 if (cflag & CSTOPB)
917 up->curregs[4] |= SB2;
918 else
919 up->curregs[4] |= SB1;
920 if (cflag & PARENB)
921 up->curregs[4] |= PAR_ENAB;
922 else
923 up->curregs[4] &= ~PAR_ENAB;
924 if (!(cflag & PARODD))
925 up->curregs[4] |= PAR_EVEN;
926 else
927 up->curregs[4] &= ~PAR_EVEN;
928
929 up->port.read_status_mask = Rx_OVR;
930 if (iflag & INPCK)
931 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
932 if (iflag & (BRKINT | PARMRK))
933 up->port.read_status_mask |= BRK_ABRT;
934
935 up->port.ignore_status_mask = 0;
936 if (iflag & IGNPAR)
937 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
938 if (iflag & IGNBRK) {
939 up->port.ignore_status_mask |= BRK_ABRT;
940 if (iflag & IGNPAR)
941 up->port.ignore_status_mask |= Rx_OVR;
942 }
943
944 if ((cflag & CREAD) == 0)
945 up->port.ignore_status_mask = 0xff;
946 }
947
948 /* The port lock is not held. */
949 static void
950 sunzilog_set_termios(struct uart_port *port, struct termios *termios,
951 struct termios *old)
952 {
953 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
954 unsigned long flags;
955 int baud, brg;
956
957 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
958
959 spin_lock_irqsave(&up->port.lock, flags);
960
961 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
962
963 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
964
965 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
966 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
967 else
968 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
969
970 up->cflag = termios->c_cflag;
971
972 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
973
974 spin_unlock_irqrestore(&up->port.lock, flags);
975 }
976
977 static const char *sunzilog_type(struct uart_port *port)
978 {
979 return "SunZilog";
980 }
981
982 /* We do not request/release mappings of the registers here, this
983 * happens at early serial probe time.
984 */
985 static void sunzilog_release_port(struct uart_port *port)
986 {
987 }
988
989 static int sunzilog_request_port(struct uart_port *port)
990 {
991 return 0;
992 }
993
994 /* These do not need to do anything interesting either. */
995 static void sunzilog_config_port(struct uart_port *port, int flags)
996 {
997 }
998
999 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1000 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
1001 {
1002 return -EINVAL;
1003 }
1004
1005 static struct uart_ops sunzilog_pops = {
1006 .tx_empty = sunzilog_tx_empty,
1007 .set_mctrl = sunzilog_set_mctrl,
1008 .get_mctrl = sunzilog_get_mctrl,
1009 .stop_tx = sunzilog_stop_tx,
1010 .start_tx = sunzilog_start_tx,
1011 .stop_rx = sunzilog_stop_rx,
1012 .enable_ms = sunzilog_enable_ms,
1013 .break_ctl = sunzilog_break_ctl,
1014 .startup = sunzilog_startup,
1015 .shutdown = sunzilog_shutdown,
1016 .set_termios = sunzilog_set_termios,
1017 .type = sunzilog_type,
1018 .release_port = sunzilog_release_port,
1019 .request_port = sunzilog_request_port,
1020 .config_port = sunzilog_config_port,
1021 .verify_port = sunzilog_verify_port,
1022 };
1023
1024 static struct uart_sunzilog_port *sunzilog_port_table;
1025 static struct zilog_layout **sunzilog_chip_regs;
1026
1027 static struct uart_sunzilog_port *sunzilog_irq_chain;
1028 static int zilog_irq = -1;
1029
1030 static struct uart_driver sunzilog_reg = {
1031 .owner = THIS_MODULE,
1032 .driver_name = "ttyS",
1033 .devfs_name = "tts/",
1034 .dev_name = "ttyS",
1035 .major = TTY_MAJOR,
1036 };
1037
1038 static void * __init alloc_one_table(unsigned long size)
1039 {
1040 void *ret;
1041
1042 ret = kmalloc(size, GFP_KERNEL);
1043 if (ret != NULL)
1044 memset(ret, 0, size);
1045
1046 return ret;
1047 }
1048
1049 static void __init sunzilog_alloc_tables(void)
1050 {
1051 sunzilog_port_table = (struct uart_sunzilog_port *)
1052 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_sunzilog_port));
1053 sunzilog_chip_regs = (struct zilog_layout **)
1054 alloc_one_table(NUM_SUNZILOG * sizeof(struct zilog_layout *));
1055
1056 if (sunzilog_port_table == NULL || sunzilog_chip_regs == NULL) {
1057 prom_printf("SunZilog: Cannot allocate tables.\n");
1058 prom_halt();
1059 }
1060 }
1061
1062 #ifdef CONFIG_SPARC64
1063
1064 /* We used to attempt to use the address property of the Zilog device node
1065 * but that totally is not necessary on sparc64.
1066 */
1067 static struct zilog_layout * __init get_zs_sun4u(int chip, int zsnode)
1068 {
1069 unsigned long mapped_addr;
1070 unsigned int sun4u_ino;
1071 struct sbus_bus *sbus = NULL;
1072 struct sbus_dev *sdev = NULL;
1073 int err;
1074
1075 if (central_bus == NULL) {
1076 for_each_sbus(sbus) {
1077 for_each_sbusdev(sdev, sbus) {
1078 if (sdev->prom_node == zsnode)
1079 goto found;
1080 }
1081 }
1082 }
1083 found:
1084 if (sdev == NULL && central_bus == NULL) {
1085 prom_printf("SunZilog: sdev&&central == NULL for "
1086 "Zilog %d in get_zs_sun4u.\n", chip);
1087 prom_halt();
1088 }
1089 if (central_bus == NULL) {
1090 mapped_addr =
1091 sbus_ioremap(&sdev->resource[0], 0,
1092 PAGE_SIZE,
1093 "Zilog Registers");
1094 } else {
1095 struct linux_prom_registers zsregs[1];
1096
1097 err = prom_getproperty(zsnode, "reg",
1098 (char *) &zsregs[0],
1099 sizeof(zsregs));
1100 if (err == -1) {
1101 prom_printf("SunZilog: Cannot map "
1102 "Zilog %d regs on "
1103 "central bus.\n", chip);
1104 prom_halt();
1105 }
1106 apply_fhc_ranges(central_bus->child,
1107 &zsregs[0], 1);
1108 apply_central_ranges(central_bus, &zsregs[0], 1);
1109 mapped_addr =
1110 (((u64)zsregs[0].which_io)<<32UL) |
1111 ((u64)zsregs[0].phys_addr);
1112 }
1113
1114 if (zilog_irq == -1) {
1115 if (central_bus) {
1116 unsigned long iclr, imap;
1117
1118 iclr = central_bus->child->fhc_regs.uregs
1119 + FHC_UREGS_ICLR;
1120 imap = central_bus->child->fhc_regs.uregs
1121 + FHC_UREGS_IMAP;
1122 zilog_irq = build_irq(12, 0, iclr, imap);
1123 } else {
1124 err = prom_getproperty(zsnode, "interrupts",
1125 (char *) &sun4u_ino,
1126 sizeof(sun4u_ino));
1127 zilog_irq = sbus_build_irq(sbus_root, sun4u_ino);
1128 }
1129 }
1130
1131 return (struct zilog_layout *) mapped_addr;
1132 }
1133 #else /* CONFIG_SPARC64 */
1134
1135 /*
1136 * XXX The sun4d case is utterly screwed: it tries to re-walk the tree
1137 * (for the 3rd time) in order to find bootbus and cpu. Streamline it.
1138 */
1139 static struct zilog_layout * __init get_zs_sun4cmd(int chip, int node)
1140 {
1141 struct linux_prom_irqs irq_info[2];
1142 unsigned long mapped_addr = 0;
1143 int zsnode, cpunode, bbnode;
1144 struct linux_prom_registers zsreg[4];
1145 struct resource res;
1146
1147 if (sparc_cpu_model == sun4d) {
1148 int walk;
1149
1150 zsnode = 0;
1151 bbnode = 0;
1152 cpunode = 0;
1153 for (walk = prom_getchild(prom_root_node);
1154 (walk = prom_searchsiblings(walk, "cpu-unit")) != 0;
1155 walk = prom_getsibling(walk)) {
1156 bbnode = prom_getchild(walk);
1157 if (bbnode &&
1158 (bbnode = prom_searchsiblings(bbnode, "bootbus"))) {
1159 if ((zsnode = prom_getchild(bbnode)) == node) {
1160 cpunode = walk;
1161 break;
1162 }
1163 }
1164 }
1165 if (!walk) {
1166 prom_printf("SunZilog: Cannot find the %d'th bootbus on sun4d.\n",
1167 (chip / 2));
1168 prom_halt();
1169 }
1170
1171 if (prom_getproperty(zsnode, "reg",
1172 (char *) zsreg, sizeof(zsreg)) == -1) {
1173 prom_printf("SunZilog: Cannot map Zilog %d\n", chip);
1174 prom_halt();
1175 }
1176 /* XXX Looks like an off by one? */
1177 prom_apply_generic_ranges(bbnode, cpunode, zsreg, 1);
1178 res.start = zsreg[0].phys_addr;
1179 res.end = res.start + (8 - 1);
1180 res.flags = zsreg[0].which_io | IORESOURCE_IO;
1181 mapped_addr = sbus_ioremap(&res, 0, 8, "Zilog Serial");
1182
1183 } else {
1184 zsnode = node;
1185
1186 #if 0 /* XXX When was this used? */
1187 if (prom_getintdefault(zsnode, "slave", -1) != chipid) {
1188 zsnode = prom_getsibling(zsnode);
1189 continue;
1190 }
1191 #endif
1192
1193 /*
1194 * "address" is only present on ports that OBP opened
1195 * (from Mitch Bradley's "Hitchhiker's Guide to OBP").
1196 * We do not use it.
1197 */
1198
1199 if (prom_getproperty(zsnode, "reg",
1200 (char *) zsreg, sizeof(zsreg)) == -1) {
1201 prom_printf("SunZilog: Cannot map Zilog %d\n", chip);
1202 prom_halt();
1203 }
1204 if (sparc_cpu_model == sun4m) /* Crude. Pass parent. XXX */
1205 prom_apply_obio_ranges(zsreg, 1);
1206 res.start = zsreg[0].phys_addr;
1207 res.end = res.start + (8 - 1);
1208 res.flags = zsreg[0].which_io | IORESOURCE_IO;
1209 mapped_addr = sbus_ioremap(&res, 0, 8, "Zilog Serial");
1210 }
1211
1212 if (prom_getproperty(zsnode, "intr",
1213 (char *) irq_info, sizeof(irq_info))
1214 % sizeof(struct linux_prom_irqs)) {
1215 prom_printf("SunZilog: Cannot get IRQ property for Zilog %d.\n",
1216 chip);
1217 prom_halt();
1218 }
1219 if (zilog_irq == -1) {
1220 zilog_irq = irq_info[0].pri;
1221 } else if (zilog_irq != irq_info[0].pri) {
1222 /* XXX. Dumb. Should handle per-chip IRQ, for add-ons. */
1223 prom_printf("SunZilog: Inconsistent IRQ layout for Zilog %d.\n",
1224 chip);
1225 prom_halt();
1226 }
1227
1228 return (struct zilog_layout *) mapped_addr;
1229 }
1230 #endif /* !(CONFIG_SPARC64) */
1231
1232 /* Get the address of the registers for SunZilog instance CHIP. */
1233 static struct zilog_layout * __init get_zs(int chip, int node)
1234 {
1235 if (chip < 0 || chip >= NUM_SUNZILOG) {
1236 prom_printf("SunZilog: Illegal chip number %d in get_zs.\n", chip);
1237 prom_halt();
1238 }
1239
1240 #ifdef CONFIG_SPARC64
1241 return get_zs_sun4u(chip, node);
1242 #else
1243
1244 if (sparc_cpu_model == sun4) {
1245 struct resource res;
1246
1247 /* Not probe-able, hard code it. */
1248 switch (chip) {
1249 case 0:
1250 res.start = 0xf1000000;
1251 break;
1252 case 1:
1253 res.start = 0xf0000000;
1254 break;
1255 };
1256 zilog_irq = 12;
1257 res.end = (res.start + (8 - 1));
1258 res.flags = IORESOURCE_IO;
1259 return (struct zilog_layout *) sbus_ioremap(&res, 0, 8, "SunZilog");
1260 }
1261
1262 return get_zs_sun4cmd(chip, node);
1263 #endif
1264 }
1265
1266 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
1267
1268 static void sunzilog_put_char(struct zilog_channel *channel, unsigned char ch)
1269 {
1270 int loops = ZS_PUT_CHAR_MAX_DELAY;
1271
1272 /* This is a timed polling loop so do not switch the explicit
1273 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1274 */
1275 do {
1276 unsigned char val = sbus_readb(&channel->control);
1277 if (val & Tx_BUF_EMP) {
1278 ZSDELAY();
1279 break;
1280 }
1281 udelay(5);
1282 } while (--loops);
1283
1284 sbus_writeb(ch, &channel->data);
1285 ZSDELAY();
1286 ZS_WSYNC(channel);
1287 }
1288
1289 #ifdef CONFIG_SERIO
1290
1291 static spinlock_t sunzilog_serio_lock = SPIN_LOCK_UNLOCKED;
1292
1293 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1294 {
1295 struct uart_sunzilog_port *up = serio->driver;
1296 unsigned long flags;
1297
1298 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1299
1300 sunzilog_put_char(ZILOG_CHANNEL_FROM_PORT(&up->port), ch);
1301
1302 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1303
1304 return 0;
1305 }
1306
1307 static int sunzilog_serio_open(struct serio *serio)
1308 {
1309 unsigned long flags;
1310 int ret;
1311
1312 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1313 if (serio->private == NULL) {
1314 serio->private = (void *) -1L;
1315 ret = 0;
1316 } else
1317 ret = -EBUSY;
1318 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1319
1320 return ret;
1321 }
1322
1323 static void sunzilog_serio_close(struct serio *serio)
1324 {
1325 unsigned long flags;
1326
1327 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1328 serio->private = NULL;
1329 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1330 }
1331
1332 #endif /* CONFIG_SERIO */
1333
1334 static void
1335 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1336 {
1337 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1338 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1339 unsigned long flags;
1340 int i;
1341
1342 spin_lock_irqsave(&up->port.lock, flags);
1343 for (i = 0; i < count; i++, s++) {
1344 sunzilog_put_char(channel, *s);
1345 if (*s == 10)
1346 sunzilog_put_char(channel, 13);
1347 }
1348 udelay(2);
1349 spin_unlock_irqrestore(&up->port.lock, flags);
1350 }
1351
1352 static int __init sunzilog_console_setup(struct console *con, char *options)
1353 {
1354 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1355 unsigned long flags;
1356 int baud, brg;
1357
1358 printk("Console: ttyS%d (SunZilog)\n",
1359 (sunzilog_reg.minor - 64) + con->index);
1360
1361 /* Get firmware console settings. */
1362 sunserial_console_termios(con);
1363
1364 /* Firmware console speed is limited to 150-->38400 baud so
1365 * this hackish cflag thing is OK.
1366 */
1367 switch (con->cflag & CBAUD) {
1368 case B150: baud = 150; break;
1369 case B300: baud = 300; break;
1370 case B600: baud = 600; break;
1371 case B1200: baud = 1200; break;
1372 case B2400: baud = 2400; break;
1373 case B4800: baud = 4800; break;
1374 default: case B9600: baud = 9600; break;
1375 case B19200: baud = 19200; break;
1376 case B38400: baud = 38400; break;
1377 };
1378
1379 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1380
1381 spin_lock_irqsave(&up->port.lock, flags);
1382
1383 up->curregs[R15] = BRKIE;
1384 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1385
1386 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1387 __sunzilog_startup(up);
1388
1389 spin_unlock_irqrestore(&up->port.lock, flags);
1390
1391 return 0;
1392 }
1393
1394 static struct console sunzilog_console = {
1395 .name = "ttyS",
1396 .write = sunzilog_console_write,
1397 .device = uart_console_device,
1398 .setup = sunzilog_console_setup,
1399 .flags = CON_PRINTBUFFER,
1400 .index = -1,
1401 .data = &sunzilog_reg,
1402 };
1403
1404 static int __init sunzilog_console_init(void)
1405 {
1406 int i;
1407
1408 if (con_is_present())
1409 return 0;
1410
1411 for (i = 0; i < NUM_CHANNELS; i++) {
1412 int this_minor = sunzilog_reg.minor + i;
1413
1414 if ((this_minor - 64) == (serial_console - 1))
1415 break;
1416 }
1417 if (i == NUM_CHANNELS)
1418 return 0;
1419
1420 sunzilog_console.index = i;
1421 sunzilog_port_table[i].flags |= SUNZILOG_FLAG_IS_CONS;
1422 register_console(&sunzilog_console);
1423 return 0;
1424 }
1425
1426 /*
1427 * We scan the PROM tree recursively. This is the most reliable way
1428 * to find Zilog nodes on various platforms. However, we face an extreme
1429 * shortage of kernel stack, so we must be very careful. To that end,
1430 * we scan only to a certain depth, and we use a common property buffer
1431 * in the scan structure.
1432 */
1433 #define ZS_PROPSIZE 128
1434 #define ZS_SCAN_DEPTH 5
1435
1436 struct zs_probe_scan {
1437 int depth;
1438 void (*scanner)(struct zs_probe_scan *t, int node);
1439
1440 int devices;
1441 char prop[ZS_PROPSIZE];
1442 };
1443
1444 static int __inline__ sunzilog_node_ok(int node, const char *name, int len)
1445 {
1446 if (strncmp(name, "zs", len) == 0)
1447 return 1;
1448 /* Don't fold this procedure just yet. Compare to su_node_ok(). */
1449 return 0;
1450 }
1451
1452 static void __init sunzilog_scan(struct zs_probe_scan *t, int node)
1453 {
1454 int len;
1455
1456 for (; node != 0; node = prom_getsibling(node)) {
1457 len = prom_getproperty(node, "name", t->prop, ZS_PROPSIZE);
1458 if (len <= 1)
1459 continue; /* Broken PROM node */
1460 if (sunzilog_node_ok(node, t->prop, len)) {
1461 (*t->scanner)(t, node);
1462 } else {
1463 if (t->depth < ZS_SCAN_DEPTH) {
1464 t->depth++;
1465 sunzilog_scan(t, prom_getchild(node));
1466 --t->depth;
1467 }
1468 }
1469 }
1470 }
1471
1472 static void __init sunzilog_prepare(void)
1473 {
1474 struct uart_sunzilog_port *up;
1475 struct zilog_layout *rp;
1476 int channel, chip;
1477
1478 /*
1479 * Temporary fix.
1480 */
1481 for (channel = 0; channel < NUM_CHANNELS; channel++)
1482 spin_lock_init(&sunzilog_port_table[channel].port.lock);
1483
1484 sunzilog_irq_chain = up = &sunzilog_port_table[0];
1485 for (channel = 0; channel < NUM_CHANNELS - 1; channel++)
1486 up[channel].next = &up[channel + 1];
1487 up[channel].next = NULL;
1488
1489 for (chip = 0; chip < NUM_SUNZILOG; chip++) {
1490 rp = sunzilog_chip_regs[chip];
1491 up[(chip * 2) + 0].port.membase = (char *) &rp->channelA;
1492 up[(chip * 2) + 1].port.membase = (char *) &rp->channelB;
1493
1494 /* Channel A */
1495 up[(chip * 2) + 0].port.iotype = SERIAL_IO_MEM;
1496 up[(chip * 2) + 0].port.irq = zilog_irq;
1497 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1498 up[(chip * 2) + 0].port.fifosize = 1;
1499 up[(chip * 2) + 0].port.ops = &sunzilog_pops;
1500 up[(chip * 2) + 0].port.type = PORT_SUNZILOG;
1501 up[(chip * 2) + 0].port.flags = 0;
1502 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1503 up[(chip * 2) + 0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1504
1505 /* Channel B */
1506 up[(chip * 2) + 1].port.iotype = SERIAL_IO_MEM;
1507 up[(chip * 2) + 1].port.irq = zilog_irq;
1508 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1509 up[(chip * 2) + 1].port.fifosize = 1;
1510 up[(chip * 2) + 1].port.ops = &sunzilog_pops;
1511 up[(chip * 2) + 1].port.type = PORT_SUNZILOG;
1512 up[(chip * 2) + 1].port.flags = 0;
1513 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1514 up[(chip * 2) + 1].flags |= 0;
1515 }
1516 }
1517
1518 static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channel)
1519 {
1520 int baud, brg;
1521
1522 if (channel == KEYBOARD_LINE) {
1523 up->flags |= SUNZILOG_FLAG_CONS_KEYB;
1524 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1525 baud = 1200;
1526 } else {
1527 up->flags |= SUNZILOG_FLAG_CONS_MOUSE;
1528 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1529 baud = 4800;
1530 }
1531 printk(KERN_INFO "zs%d at 0x%p (irq = %s) is a SunZilog\n",
1532 channel, up->port.membase, __irq_itoa(zilog_irq));
1533
1534 up->curregs[R15] = BRKIE;
1535 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1536 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1537
1538 #ifdef CONFIG_SERIO
1539 memset(&up->serio, 0, sizeof(up->serio));
1540
1541 up->serio.driver = up;
1542
1543 up->serio.type = SERIO_RS232;
1544 if (channel == KEYBOARD_LINE) {
1545 up->serio.type |= SERIO_SUNKBD;
1546 up->serio.name = "zskbd";
1547 } else {
1548 up->serio.type |= SERIO_SUN;
1549 up->serio.name = "zsms";
1550 }
1551 up->serio.phys = (channel == KEYBOARD_LINE ?
1552 "zs/serio0" : "zs/serio1");
1553
1554 up->serio.write = sunzilog_serio_write;
1555 up->serio.open = sunzilog_serio_open;
1556 up->serio.close = sunzilog_serio_close;
1557
1558 serio_register_port(&up->serio);
1559 #endif
1560
1561 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1562 __sunzilog_startup(up);
1563 }
1564
1565 static void __init sunzilog_init_hw(void)
1566 {
1567 int i;
1568
1569 for (i = 0; i < NUM_CHANNELS; i++) {
1570 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1571 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1572 unsigned long flags;
1573 int baud, brg;
1574
1575 spin_lock_irqsave(&up->port.lock, flags);
1576
1577 if (ZS_IS_CHANNEL_A(up)) {
1578 write_zsreg(channel, R9, FHWRES);
1579 ZSDELAY_LONG();
1580 (void) read_zsreg(channel, R0);
1581 }
1582
1583 if (i == KEYBOARD_LINE || i == MOUSE_LINE) {
1584 sunzilog_init_kbdms(up, i);
1585 } else {
1586 /* Normal serial TTY. */
1587 up->parity_mask = 0xff;
1588 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1589 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1590 up->curregs[R3] = RxENAB | Rx8;
1591 up->curregs[R5] = TxENAB | Tx8;
1592 up->curregs[R9] = NV | MIE;
1593 up->curregs[R10] = NRZ;
1594 up->curregs[R11] = TCBR | RCBR;
1595 baud = 9600;
1596 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1597 up->curregs[R12] = (brg & 0xff);
1598 up->curregs[R13] = (brg >> 8) & 0xff;
1599 up->curregs[R14] = BRSRC | BRENAB;
1600 __load_zsregs(channel, up->curregs);
1601 write_zsreg(channel, R9, up->curregs[R9]);
1602 }
1603
1604 spin_unlock_irqrestore(&up->port.lock, flags);
1605 }
1606 }
1607
1608 static struct zilog_layout * __init get_zs(int chip, int node);
1609
1610 static void __init sunzilog_scan_probe(struct zs_probe_scan *t, int node)
1611 {
1612 sunzilog_chip_regs[t->devices] = get_zs(t->devices, node);
1613 t->devices++;
1614 }
1615
1616 static int __init sunzilog_ports_init(void)
1617 {
1618 struct zs_probe_scan scan;
1619 int ret;
1620
1621 printk(KERN_INFO "Serial: Sun Zilog driver (%d chips).\n", NUM_SUNZILOG);
1622
1623 scan.scanner = sunzilog_scan_probe;
1624 scan.depth = 0;
1625 scan.devices = 0;
1626 sunzilog_scan(&scan, prom_getchild(prom_root_node));
1627
1628 sunzilog_prepare();
1629
1630 if (request_irq(zilog_irq, sunzilog_interrupt, SA_SHIRQ,
1631 "SunZilog", sunzilog_irq_chain)) {
1632 prom_printf("SunZilog: Unable to register zs interrupt handler.\n");
1633 prom_halt();
1634 }
1635
1636 sunzilog_init_hw();
1637
1638 /* We can only init this once we have probed the Zilogs
1639 * in the system.
1640 */
1641 sunzilog_reg.nr = NUM_CHANNELS;
1642 sunzilog_reg.cons = &sunzilog_console;
1643
1644 sunzilog_reg.minor = sunserial_current_minor;
1645 sunserial_current_minor += NUM_CHANNELS;
1646
1647 ret = uart_register_driver(&sunzilog_reg);
1648 if (ret == 0) {
1649 int i;
1650
1651 for (i = 0; i < NUM_CHANNELS; i++) {
1652 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1653
1654 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up))
1655 continue;
1656
1657 uart_add_one_port(&sunzilog_reg, &up->port);
1658 }
1659 }
1660
1661 return ret;
1662 }
1663
1664 static void __init sunzilog_scan_count(struct zs_probe_scan *t, int node)
1665 {
1666 t->devices++;
1667 }
1668
1669 static int __init sunzilog_ports_count(void)
1670 {
1671 struct zs_probe_scan scan;
1672
1673 /* Sun4 Zilog setup is hard coded, no probing to do. */
1674 if (sparc_cpu_model == sun4)
1675 return 2;
1676
1677 scan.scanner = sunzilog_scan_count;
1678 scan.depth = 0;
1679 scan.devices = 0;
1680
1681 sunzilog_scan(&scan, prom_getchild(prom_root_node));
1682
1683 return scan.devices;
1684 }
1685
1686 static int __init sunzilog_init(void)
1687 {
1688
1689 NUM_SUNZILOG = sunzilog_ports_count();
1690 if (NUM_SUNZILOG == 0)
1691 return -ENODEV;
1692
1693 sunzilog_alloc_tables();
1694
1695 sunzilog_ports_init();
1696 sunzilog_console_init();
1697
1698 return 0;
1699 }
1700
1701 static void __exit sunzilog_exit(void)
1702 {
1703 int i;
1704
1705 for (i = 0; i < NUM_CHANNELS; i++) {
1706 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1707
1708 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up))
1709 continue;
1710
1711 uart_remove_one_port(&sunzilog_reg, &up->port);
1712 }
1713
1714 uart_unregister_driver(&sunzilog_reg);
1715 }
1716
1717 module_init(sunzilog_init);
1718 module_exit(sunzilog_exit);
1719
1720 MODULE_AUTHOR("David S. Miller");
1721 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1722 MODULE_LICENSE("GPL");
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