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[linux-2.6/linux-mips.git] / drivers / serial / sunsab.c
blobf69dccdfc530efb17d5ef29c038c8844c42f5a29
1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@redhat.com>
16 */
17
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/major.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/ioport.h>
29 #include <linux/circ_buf.h>
30 #include <linux/serial.h>
31 #include <linux/console.h>
32 #include <linux/spinlock.h>
33 #include <linux/slab.h>
34 #include <linux/init.h>
35
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <asm/oplib.h>
39 #include <asm/ebus.h>
40
41 #include <linux/serial_core.h>
42
43 #include "suncore.h"
44 #include "sunsab.h"
45
46 struct uart_sunsab_port {
47 struct uart_port port; /* Generic UART port */
48 union sab82532_async_regs *regs; /* Chip registers */
49 unsigned long irqflags; /* IRQ state flags */
50 int dsr; /* Current DSR state */
51 unsigned int cec_timeout; /* Chip poll timeout... */
52 unsigned int tec_timeout; /* likewise */
53 unsigned char interrupt_mask0;/* ISR0 masking */
54 unsigned char interrupt_mask1;/* ISR1 masking */
55 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
56 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
57 int type; /* SAB82532 version */
58 };
59
60 /*
61 * This assumes you have a 29.4912 MHz clock for your UART.
62 */
63 #define SAB_BASE_BAUD ( 29491200 / 16 )
64
65 static char *sab82532_version[16] = {
66 "V1.0", "V2.0", "V3.2", "V(0x03)",
67 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
68 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
69 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
70 };
71
72 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
73 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
74
75 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
76 #define SAB82532_XMIT_FIFO_SIZE 32
77
78 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
79 {
80 int timeout = up->tec_timeout;
81
82 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
83 udelay(1);
84 }
85
86 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
87 {
88 int timeout = up->cec_timeout;
89
90 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
91 udelay(1);
92 }
93
94 static void receive_chars(struct uart_sunsab_port *up,
95 union sab82532_irq_status *stat,
96 struct pt_regs *regs)
97 {
98 struct tty_struct *tty = up->port.info->tty;
99 unsigned char buf[32];
100 int saw_console_brk = 0;
101 int free_fifo = 0;
102 int count = 0;
103 int i;
104
105 /* Read number of BYTES (Character + Status) available. */
106 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
107 count = SAB82532_RECV_FIFO_SIZE;
108 free_fifo++;
109 }
110
111 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
112 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
113 free_fifo++;
114 }
115
116 /* Issue a FIFO read command in case we where idle. */
117 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
118 sunsab_cec_wait(up);
119 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
120 return;
121 }
122
123 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
124 free_fifo++;
125
126 /* Read the FIFO. */
127 for (i = 0; i < count; i++)
128 buf[i] = readb(&up->regs->r.rfifo[i]);
129
130 /* Issue Receive Message Complete command. */
131 if (free_fifo) {
132 sunsab_cec_wait(up);
133 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
134 }
135
136 for (i = 0; i < count; i++) {
137 unsigned char ch = buf[i];
138
139 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
140 tty->flip.work.func((void *)tty);
141 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
142 return; // if TTY_DONT_FLIP is set
143 }
144
145 *tty->flip.char_buf_ptr = ch;
146 *tty->flip.flag_buf_ptr = TTY_NORMAL;
147 up->port.icount.rx++;
148
149 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
150 SAB82532_ISR0_FERR |
151 SAB82532_ISR0_RFO)) ||
152 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
153 /*
154 * For statistics only
155 */
156 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
157 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
158 SAB82532_ISR0_FERR);
159 up->port.icount.brk++;
160 if (up->port.line == up->port.cons->index)
161 saw_console_brk = 1;
162 /*
163 * We do the SysRQ and SAK checking
164 * here because otherwise the break
165 * may get masked by ignore_status_mask
166 * or read_status_mask.
167 */
168 if (uart_handle_break(&up->port))
169 continue;
170 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
171 up->port.icount.parity++;
172 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
173 up->port.icount.frame++;
174 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
175 up->port.icount.overrun++;
176
177 /*
178 * Mask off conditions which should be ingored.
179 */
180 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
181 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
182
183 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
184 *tty->flip.flag_buf_ptr = TTY_BREAK;
185 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
186 *tty->flip.flag_buf_ptr = TTY_PARITY;
187 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
188 *tty->flip.flag_buf_ptr = TTY_FRAME;
189 }
190
191 if (uart_handle_sysrq_char(&up->port, ch, regs))
192 continue;
193
194 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
195 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0){
196 tty->flip.flag_buf_ptr++;
197 tty->flip.char_buf_ptr++;
198 tty->flip.count++;
199 }
200 if ((stat->sreg.isr0 & SAB82532_ISR0_RFO) &&
201 tty->flip.count < TTY_FLIPBUF_SIZE) {
202 /*
203 * Overrun is special, since it's reported
204 * immediately, and doesn't affect the current
205 * character.
206 */
207 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
208 tty->flip.flag_buf_ptr++;
209 tty->flip.char_buf_ptr++;
210 tty->flip.count++;
211 }
212 }
213
214 tty_flip_buffer_push(tty);
215
216 if (saw_console_brk)
217 sun_do_break();
218 }
219
220 static void sunsab_stop_tx(struct uart_port *, unsigned int);
221
222 static void transmit_chars(struct uart_sunsab_port *up,
223 union sab82532_irq_status *stat)
224 {
225 struct circ_buf *xmit = &up->port.info->xmit;
226 int i;
227
228 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
229 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
230 writeb(up->interrupt_mask1, &up->regs->w.imr1);
231 set_bit(SAB82532_ALLS, &up->irqflags);
232 }
233
234 #if 0 /* bde@nwlink.com says this check causes problems */
235 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
236 return;
237 #endif
238
239 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
240 return;
241
242 set_bit(SAB82532_XPR, &up->irqflags);
243
244 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
245 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
246 writeb(up->interrupt_mask1, &up->regs->w.imr1);
247 uart_write_wakeup(&up->port);
248 return;
249 }
250
251 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
252 writeb(up->interrupt_mask1, &up->regs->w.imr1);
253 clear_bit(SAB82532_ALLS, &up->irqflags);
254
255 /* Stuff 32 bytes into Transmit FIFO. */
256 clear_bit(SAB82532_XPR, &up->irqflags);
257 for (i = 0; i < up->port.fifosize; i++) {
258 writeb(xmit->buf[xmit->tail],
259 &up->regs->w.xfifo[i]);
260 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
261 up->port.icount.tx++;
262 if (uart_circ_empty(xmit))
263 break;
264 }
265
266 /* Issue a Transmit Frame command. */
267 sunsab_cec_wait(up);
268 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
269
270 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
271 uart_write_wakeup(&up->port);
272
273 if (uart_circ_empty(xmit))
274 sunsab_stop_tx(&up->port, 0);
275 }
276
277 static void check_status(struct uart_sunsab_port *up,
278 union sab82532_irq_status *stat)
279 {
280 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
281 uart_handle_dcd_change(&up->port,
282 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
283
284 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
285 uart_handle_cts_change(&up->port,
286 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
287
288 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
289 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
290 up->port.icount.dsr++;
291 }
292
293 wake_up_interruptible(&up->port.info->delta_msr_wait);
294 }
295
296 static irqreturn_t sunsab_interrupt(int irq, void *dev_id, struct pt_regs *regs)
297 {
298 struct uart_sunsab_port *up = dev_id;
299 union sab82532_irq_status status;
300 unsigned long flags;
301
302 spin_lock_irqsave(&up->port.lock, flags);
303
304 status.stat = 0;
305 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
306 status.sreg.isr0 = readb(&up->regs->r.isr0);
307 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
308 status.sreg.isr1 = readb(&up->regs->r.isr1);
309
310 if (status.stat) {
311 if (status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
312 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF))
313 receive_chars(up, &status, regs);
314 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
315 (status.sreg.isr1 & SAB82532_ISR1_CSC))
316 check_status(up, &status);
317 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
318 transmit_chars(up, &status);
319 }
320
321 spin_unlock(&up->port.lock);
322
323 up++;
324
325 spin_lock(&up->port.lock);
326
327 status.stat = 0;
328 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
329 status.sreg.isr0 = readb(&up->regs->r.isr0);
330 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
331 status.sreg.isr1 = readb(&up->regs->r.isr1);
332
333 if (status.stat) {
334 if (status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
335 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF))
336 receive_chars(up, &status, regs);
337 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
338 (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
339 check_status(up, &status);
340 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
341 transmit_chars(up, &status);
342 }
343
344 spin_unlock_irqrestore(&up->port.lock, flags);
345
346 return IRQ_HANDLED;
347 }
348
349 /* port->lock is not held. */
350 static unsigned int sunsab_tx_empty(struct uart_port *port)
351 {
352 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
353 int ret;
354
355 /* Do not need a lock for a state test like this. */
356 if (test_bit(SAB82532_ALLS, &up->irqflags))
357 ret = TIOCSER_TEMT;
358 else
359 ret = 0;
360
361 return ret;
362 }
363
364 /* port->lock held by caller. */
365 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
366 {
367 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
368
369 if (mctrl & TIOCM_RTS) {
370 writeb(readb(&up->regs->rw.mode) & ~SAB82532_MODE_FRTS,
371 &up->regs->rw.mode);
372 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
373 &up->regs->rw.mode);
374 } else {
375 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FRTS,
376 &up->regs->rw.mode);
377 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
378 &up->regs->rw.mode);
379 }
380 if (mctrl & TIOCM_DTR) {
381 writeb(readb(&up->regs->rw.pvr) & ~(up->pvr_dtr_bit), &up->regs->rw.pvr);
382 } else {
383 writeb(readb(&up->regs->rw.pvr) | up->pvr_dtr_bit, &up->regs->rw.pvr);
384 }
385 }
386
387 /* port->lock is not held. */
388 static unsigned int sunsab_get_mctrl(struct uart_port *port)
389 {
390 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
391 unsigned long flags;
392 unsigned char val;
393 unsigned int result;
394
395 result = 0;
396
397 spin_lock_irqsave(&up->port.lock, flags);
398
399 val = readb(&up->regs->r.pvr);
400 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
401
402 val = readb(&up->regs->r.vstr);
403 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
404
405 val = readb(&up->regs->r.star);
406 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
407
408 spin_unlock_irqrestore(&up->port.lock, flags);
409
410 return result;
411 }
412
413 /* port->lock held by caller. */
414 static void sunsab_stop_tx(struct uart_port *port, unsigned int tty_stop)
415 {
416 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
417
418 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
419 writeb(up->interrupt_mask1, &up->regs->w.imr1);
420 }
421
422 /* port->lock held by caller. */
423 static void sunsab_start_tx(struct uart_port *port, unsigned int tty_start)
424 {
425 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
426 struct circ_buf *xmit = &up->port.info->xmit;
427 int i;
428
429 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
430 writeb(up->interrupt_mask1, &up->regs->w.imr1);
431
432 if (!test_bit(SAB82532_XPR, &up->irqflags))
433 return;
434
435 clear_bit(SAB82532_ALLS, &up->irqflags);
436 clear_bit(SAB82532_XPR, &up->irqflags);
437
438 for (i = 0; i < up->port.fifosize; i++) {
439 writeb(xmit->buf[xmit->tail],
440 &up->regs->w.xfifo[i]);
441 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
442 up->port.icount.tx++;
443 if (uart_circ_empty(xmit))
444 break;
445 }
446
447 /* Issue a Transmit Frame command. */
448 sunsab_cec_wait(up);
449 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
450 }
451
452 /* port->lock is not held. */
453 static void sunsab_send_xchar(struct uart_port *port, char ch)
454 {
455 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
456 unsigned long flags;
457
458 spin_lock_irqsave(&up->port.lock, flags);
459
460 sunsab_tec_wait(up);
461 writeb(ch, &up->regs->w.tic);
462
463 spin_unlock_irqrestore(&up->port.lock, flags);
464 }
465
466 /* port->lock held by caller. */
467 static void sunsab_stop_rx(struct uart_port *port)
468 {
469 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
470
471 up->interrupt_mask0 |= SAB82532_ISR0_TCD;
472 writeb(up->interrupt_mask1, &up->regs->w.imr0);
473 }
474
475 /* port->lock held by caller. */
476 static void sunsab_enable_ms(struct uart_port *port)
477 {
478 /* For now we always receive these interrupts. */
479 }
480
481 /* port->lock is not held. */
482 static void sunsab_break_ctl(struct uart_port *port, int break_state)
483 {
484 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
485 unsigned long flags;
486 unsigned char val;
487
488 spin_lock_irqsave(&up->port.lock, flags);
489
490 val = readb(&up->regs->rw.dafo);
491 if (break_state)
492 val |= SAB82532_DAFO_XBRK;
493 else
494 val &= ~SAB82532_DAFO_XBRK;
495 writeb(val, &up->regs->rw.dafo);
496
497 spin_unlock_irqrestore(&up->port.lock, flags);
498 }
499
500 /* port->lock is not held. */
501 static int sunsab_startup(struct uart_port *port)
502 {
503 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
504 unsigned long flags;
505 unsigned char tmp;
506
507 spin_lock_irqsave(&up->port.lock, flags);
508
509 /*
510 * Wait for any commands or immediate characters
511 */
512 sunsab_cec_wait(up);
513 sunsab_tec_wait(up);
514
515 /*
516 * Clear the FIFO buffers.
517 */
518 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
519 sunsab_cec_wait(up);
520 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
521
522 /*
523 * Clear the interrupt registers.
524 */
525 (void) readb(&up->regs->r.isr0);
526 (void) readb(&up->regs->r.isr1);
527
528 /*
529 * Now, initialize the UART
530 */
531 writeb(0, &up->regs->w.ccr0); /* power-down */
532 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
533 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
534 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
535 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
536 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
537 writeb(0, &up->regs->w.ccr3);
538 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
539 writeb(SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
540 SAB82532_MODE_RAC, &up->regs->w.mode);
541 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
542
543 tmp = readb(&up->regs->rw.ccr0);
544 tmp |= SAB82532_CCR0_PU; /* power-up */
545 writeb(tmp, &up->regs->rw.ccr0);
546
547 /*
548 * Finally, enable interrupts
549 */
550 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
551 SAB82532_IMR0_PLLA);
552 writeb(up->interrupt_mask0, &up->regs->w.imr0);
553 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
554 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
555 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
556 SAB82532_IMR1_XPR);
557 writeb(up->interrupt_mask1, &up->regs->w.imr1);
558 set_bit(SAB82532_ALLS, &up->irqflags);
559 set_bit(SAB82532_XPR, &up->irqflags);
560
561 spin_unlock_irqrestore(&up->port.lock, flags);
562
563 return 0;
564 }
565
566 /* port->lock is not held. */
567 static void sunsab_shutdown(struct uart_port *port)
568 {
569 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
570 unsigned long flags;
571 unsigned char tmp;
572
573 spin_lock_irqsave(&up->port.lock, flags);
574
575 /* Disable Interrupts */
576 up->interrupt_mask0 = 0xff;
577 writeb(up->interrupt_mask0, &up->regs->w.imr0);
578 up->interrupt_mask1 = 0xff;
579 writeb(up->interrupt_mask1, &up->regs->w.imr1);
580
581 /* Disable break condition */
582 tmp = readb(&up->regs->rw.dafo);
583 tmp &= ~SAB82532_DAFO_XBRK;
584 writeb(tmp, &up->regs->rw.dafo);
585
586 /* Disable Receiver */
587 tmp = readb(&up->regs->rw.mode);
588 tmp &= ~SAB82532_MODE_RAC;
589 writeb(tmp, &up->regs->rw.mode);
590
591 /*
592 * XXX FIXME
593 *
594 * If the chip is powered down here the system hangs/crashes during
595 * reboot or shutdown. This needs to be investigated further,
596 * similar behaviour occurs in 2.4 when the driver is configured
597 * as a module only. One hint may be that data is sometimes
598 * transmitted at 9600 baud during shutdown (regardless of the
599 * speed the chip was configured for when the port was open).
600 */
601 #if 0
602 /* Power Down */
603 tmp = readb(&up->regs->rw.ccr0);
604 tmp &= ~SAB82532_CCR0_PU;
605 writeb(tmp, &up->regs->rw.ccr0);
606 #endif
607
608 spin_unlock_irqrestore(&up->port.lock, flags);
609 }
610
611 /*
612 * This is used to figure out the divisor speeds.
613 *
614 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
615 *
616 * with 0 <= N < 64 and 0 <= M < 16
617 */
618
619 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
620 {
621 int n, m;
622
623 if (baud == 0) {
624 *n_ret = 0;
625 *m_ret = 0;
626 return;
627 }
628
629 /*
630 * We scale numbers by 10 so that we get better accuracy
631 * without having to use floating point. Here we increment m
632 * until n is within the valid range.
633 */
634 n = (SAB_BASE_BAUD * 10) / baud;
635 m = 0;
636 while (n >= 640) {
637 n = n / 2;
638 m++;
639 }
640 n = (n+5) / 10;
641 /*
642 * We try very hard to avoid speeds with M == 0 since they may
643 * not work correctly for XTAL frequences above 10 MHz.
644 */
645 if ((m == 0) && ((n & 1) == 0)) {
646 n = n / 2;
647 m++;
648 }
649 *n_ret = n - 1;
650 *m_ret = m;
651 }
652
653 /* Internal routine, port->lock is held and local interrupts are disabled. */
654 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
655 unsigned int iflag, int baud)
656 {
657 unsigned int ebrg;
658 unsigned char dafo;
659 int bits, n, m;
660
661 /* Byte size and parity */
662 switch (cflag & CSIZE) {
663 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
664 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
665 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
666 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
667 /* Never happens, but GCC is too dumb to figure it out */
668 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
669 }
670
671 if (cflag & CSTOPB) {
672 dafo |= SAB82532_DAFO_STOP;
673 bits++;
674 }
675
676 if (cflag & PARENB) {
677 dafo |= SAB82532_DAFO_PARE;
678 bits++;
679 }
680
681 if (cflag & PARODD) {
682 dafo |= SAB82532_DAFO_PAR_ODD;
683 } else {
684 dafo |= SAB82532_DAFO_PAR_EVEN;
685 }
686
687 calc_ebrg(baud, &n, &m);
688
689 ebrg = n | (m << 6);
690
691 up->tec_timeout = (10 * 1000000) / baud;
692 up->cec_timeout = up->tec_timeout >> 2;
693
694 /* CTS flow control flags */
695 /* We encode read_status_mask and ignore_status_mask like so:
696 *
697 * ---------------------
698 * | ... | ISR1 | ISR0 |
699 * ---------------------
700 * .. 15 8 7 0
701 */
702
703 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
704 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
705 SAB82532_ISR0_CDSC);
706 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
707 SAB82532_ISR1_ALLS |
708 SAB82532_ISR1_XPR) << 8;
709 if (iflag & INPCK)
710 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
711 SAB82532_ISR0_FERR);
712 if (iflag & (BRKINT | PARMRK))
713 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
714
715 /*
716 * Characteres to ignore
717 */
718 up->port.ignore_status_mask = 0;
719 if (iflag & IGNPAR)
720 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
721 SAB82532_ISR0_FERR);
722 if (iflag & IGNBRK) {
723 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
724 /*
725 * If we're ignoring parity and break indicators,
726 * ignore overruns too (for real raw support).
727 */
728 if (iflag & IGNPAR)
729 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
730 }
731
732 /*
733 * ignore all characters if CREAD is not set
734 */
735 if ((cflag & CREAD) == 0)
736 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
737 SAB82532_ISR0_TCD);
738
739 /* Now bang the new settings into the chip. */
740 sunsab_cec_wait(up);
741 sunsab_tec_wait(up);
742 writeb(dafo, &up->regs->w.dafo);
743 writeb(ebrg & 0xff, &up->regs->w.bgr);
744 writeb((readb(&up->regs->rw.ccr2) & ~0xc0) | ((ebrg >> 2) & 0xc0),
745 &up->regs->rw.ccr2);
746
747 if (cflag & CRTSCTS) {
748 writeb(readb(&up->regs->rw.mode) & ~SAB82532_MODE_RTS,
749 &up->regs->rw.mode);
750 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FRTS,
751 &up->regs->rw.mode);
752 writeb(readb(&up->regs->rw.mode) & ~SAB82532_MODE_FCTS,
753 &up->regs->rw.mode);
754 up->interrupt_mask1 &= ~SAB82532_IMR1_CSC;
755 writeb(up->interrupt_mask1, &up->regs->w.imr1);
756 } else {
757 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
758 &up->regs->rw.mode);
759 writeb(readb(&up->regs->rw.mode) & ~SAB82532_MODE_FRTS,
760 &up->regs->rw.mode);
761 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FCTS,
762 &up->regs->rw.mode);
763 up->interrupt_mask1 |= SAB82532_IMR1_CSC;
764 writeb(up->interrupt_mask1, &up->regs->w.imr1);
765 }
766 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RAC, &up->regs->rw.mode);
767
768 }
769
770 /* port->lock is not held. */
771 static void sunsab_set_termios(struct uart_port *port, struct termios *termios,
772 struct termios *old)
773 {
774 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
775 unsigned long flags;
776 int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
777
778 spin_lock_irqsave(&up->port.lock, flags);
779 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud);
780 spin_unlock_irqrestore(&up->port.lock, flags);
781 }
782
783 static const char *sunsab_type(struct uart_port *port)
784 {
785 struct uart_sunsab_port *up = (void *)port;
786 static char buf[36];
787
788 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
789 return buf;
790 }
791
792 static void sunsab_release_port(struct uart_port *port)
793 {
794 }
795
796 static int sunsab_request_port(struct uart_port *port)
797 {
798 return 0;
799 }
800
801 static void sunsab_config_port(struct uart_port *port, int flags)
802 {
803 }
804
805 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
806 {
807 return -EINVAL;
808 }
809
810 static struct uart_ops sunsab_pops = {
811 .tx_empty = sunsab_tx_empty,
812 .set_mctrl = sunsab_set_mctrl,
813 .get_mctrl = sunsab_get_mctrl,
814 .stop_tx = sunsab_stop_tx,
815 .start_tx = sunsab_start_tx,
816 .send_xchar = sunsab_send_xchar,
817 .stop_rx = sunsab_stop_rx,
818 .enable_ms = sunsab_enable_ms,
819 .break_ctl = sunsab_break_ctl,
820 .startup = sunsab_startup,
821 .shutdown = sunsab_shutdown,
822 .set_termios = sunsab_set_termios,
823 .type = sunsab_type,
824 .release_port = sunsab_release_port,
825 .request_port = sunsab_request_port,
826 .config_port = sunsab_config_port,
827 .verify_port = sunsab_verify_port,
828 };
829
830 static struct uart_driver sunsab_reg = {
831 .owner = THIS_MODULE,
832 .driver_name = "serial",
833 .devfs_name = "tts/",
834 .dev_name = "ttyS",
835 .major = TTY_MAJOR,
836 };
837
838 static struct uart_sunsab_port *sunsab_ports;
839 static int num_channels;
840
841 static __inline__ void sunsab_console_putchar(struct uart_sunsab_port *up, char c)
842 {
843 unsigned long flags;
844
845 spin_lock_irqsave(&up->port.lock, flags);
846
847 sunsab_tec_wait(up);
848 writeb(c, &up->regs->w.tic);
849
850 spin_unlock_irqrestore(&up->port.lock, flags);
851 }
852
853 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
854 {
855 struct uart_sunsab_port *up = &sunsab_ports[con->index];
856 int i;
857
858 for (i = 0; i < n; i++) {
859 if (*s == '\n')
860 sunsab_console_putchar(up, '\r');
861 sunsab_console_putchar(up, *s++);
862 }
863 sunsab_tec_wait(up);
864 }
865
866 static int sunsab_console_setup(struct console *con, char *options)
867 {
868 struct uart_sunsab_port *up = &sunsab_ports[con->index];
869 unsigned long flags;
870 int baud;
871
872 printk("Console: ttyS%d (SAB82532)\n",
873 (sunsab_reg.minor - 64) + con->index);
874
875 sunserial_console_termios(con);
876
877 /* Firmware console speed is limited to 150-->38400 baud so
878 * this hackish cflag thing is OK.
879 */
880 switch (con->cflag & CBAUD) {
881 case B150: baud = 150; break;
882 case B300: baud = 300; break;
883 case B600: baud = 600; break;
884 case B1200: baud = 1200; break;
885 case B2400: baud = 2400; break;
886 case B4800: baud = 4800; break;
887 default: case B9600: baud = 9600; break;
888 case B19200: baud = 19200; break;
889 case B38400: baud = 38400; break;
890 };
891
892 /*
893 * Temporary fix.
894 */
895 spin_lock_init(&up->port.lock);
896
897 /*
898 * Initialize the hardware
899 */
900 sunsab_startup(&up->port);
901
902 spin_lock_irqsave(&up->port.lock, flags);
903
904 /*
905 * Finally, enable interrupts
906 */
907 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
908 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
909 writeb(up->interrupt_mask0, &up->regs->w.imr0);
910 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
911 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
912 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
913 SAB82532_IMR1_XPR;
914 writeb(up->interrupt_mask1, &up->regs->w.imr1);
915
916 sunsab_convert_to_sab(up, con->cflag, 0, baud);
917
918 spin_unlock_irqrestore(&up->port.lock, flags);
919
920 return 0;
921 }
922
923 static struct console sunsab_console = {
924 .name = "ttyS",
925 .write = sunsab_console_write,
926 .device = uart_console_device,
927 .setup = sunsab_console_setup,
928 .flags = CON_PRINTBUFFER,
929 .index = -1,
930 .data = &sunsab_reg,
931 };
932
933 static void __init sunsab_console_init(void)
934 {
935 int i;
936
937 if (con_is_present())
938 return;
939
940 for (i = 0; i < num_channels; i++) {
941 int this_minor = sunsab_reg.minor + i;
942
943 if ((this_minor - 64) == (serial_console - 1))
944 break;
945 }
946 if (i == num_channels)
947 return;
948
949 sunsab_console.index = i;
950 register_console(&sunsab_console);
951 }
952
953 static void __init for_each_sab_edev(void (*callback)(struct linux_ebus_device *, void *), void *arg)
954 {
955 struct linux_ebus *ebus;
956 struct linux_ebus_device *edev = NULL;
957
958 for_each_ebus(ebus) {
959 for_each_ebusdev(edev, ebus) {
960 if (!strcmp(edev->prom_name, "se")) {
961 callback(edev, arg);
962 continue;
963 } else if (!strcmp(edev->prom_name, "serial")) {
964 char compat[32];
965 int clen;
966
967 /* On RIO this can be an SE, check it. We could
968 * just check ebus->is_rio, but this is more portable.
969 */
970 clen = prom_getproperty(edev->prom_node, "compatible",
971 compat, sizeof(compat));
972 if (clen > 0) {
973 if (strncmp(compat, "sab82532", 8) == 0) {
974 callback(edev, arg);
975 continue;
976 }
977 }
978 }
979 }
980 }
981 }
982
983 static void __init sab_count_callback(struct linux_ebus_device *edev, void *arg)
984 {
985 int *count_p = arg;
986
987 (*count_p)++;
988 }
989
990 static void __init sab_attach_callback(struct linux_ebus_device *edev, void *arg)
991 {
992 int *instance_p = arg;
993 struct uart_sunsab_port *up;
994 unsigned long regs, offset;
995 int i;
996
997 /* Note: ports are located in reverse order */
998 regs = edev->resource[0].start;
999 offset = sizeof(union sab82532_async_regs);
1000 for (i = 0; i < 2; i++) {
1001 up = &sunsab_ports[(*instance_p * 2) + 1 - i];
1002
1003 memset(up, 0, sizeof(*up));
1004 up->regs = ioremap(regs + offset, sizeof(union sab82532_async_regs));
1005 up->port.irq = edev->irqs[0];
1006 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1007 up->port.mapbase = (unsigned long)up->regs;
1008 up->port.iotype = SERIAL_IO_MEM;
1009
1010 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1011
1012 offset -= sizeof(union sab82532_async_regs);
1013 }
1014
1015 (*instance_p)++;
1016 }
1017
1018 static int __init probe_for_sabs(void)
1019 {
1020 int this_sab = 0;
1021
1022 /* Find device instances. */
1023 for_each_sab_edev(&sab_count_callback, &this_sab);
1024 if (!this_sab)
1025 return -ENODEV;
1026
1027 /* Allocate tables. */
1028 sunsab_ports = kmalloc(sizeof(struct uart_sunsab_port) * this_sab * 2,
1029 GFP_KERNEL);
1030 if (!sunsab_ports)
1031 return -ENOMEM;
1032
1033 num_channels = this_sab * 2;
1034
1035 this_sab = 0;
1036 for_each_sab_edev(&sab_attach_callback, &this_sab);
1037 return 0;
1038 }
1039
1040 static void __init sunsab_init_hw(void)
1041 {
1042 int i;
1043
1044 for (i = 0; i < num_channels; i++) {
1045 struct uart_sunsab_port *up = &sunsab_ports[i];
1046
1047 up->port.line = i;
1048 up->port.ops = &sunsab_pops;
1049 up->port.type = PORT_SUNSAB;
1050 up->port.uartclk = SAB_BASE_BAUD;
1051
1052 up->type = readb(&up->regs->r.vstr) & 0x0f;
1053 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1054 writeb(0xff, &up->regs->w.pim);
1055 if (up->port.line == 0) {
1056 up->pvr_dsr_bit = (1 << 0);
1057 up->pvr_dtr_bit = (1 << 1);
1058 } else {
1059 up->pvr_dsr_bit = (1 << 3);
1060 up->pvr_dtr_bit = (1 << 2);
1061 }
1062 writeb((1 << 1) | (1 << 2) | (1 << 4), &up->regs->w.pvr);
1063 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FRTS,
1064 &up->regs->rw.mode);
1065 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
1066 &up->regs->rw.mode);
1067
1068 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1069 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1070
1071 if (!(up->port.line & 0x01)) {
1072 if (request_irq(up->port.irq, sunsab_interrupt,
1073 SA_SHIRQ, "serial(sab82532)", up)) {
1074 printk("sunsab%d: can't get IRQ %x\n",
1075 i, up->port.irq);
1076 continue;
1077 }
1078 }
1079 }
1080 }
1081
1082 static int __init sunsab_init(void)
1083 {
1084 int ret = probe_for_sabs();
1085 int i;
1086
1087 if (ret < 0)
1088 return ret;
1089
1090 sunsab_init_hw();
1091
1092 sunsab_reg.minor = sunserial_current_minor;
1093 sunsab_reg.nr = num_channels;
1094 sunsab_reg.cons = &sunsab_console;
1095
1096 ret = uart_register_driver(&sunsab_reg);
1097 if (ret < 0) {
1098 int i;
1099
1100 for (i = 0; i < num_channels; i++) {
1101 struct uart_sunsab_port *up = &sunsab_ports[i];
1102
1103 if (!(up->port.line & 0x01))
1104 free_irq(up->port.irq, up);
1105 iounmap(up->regs);
1106 }
1107 kfree(sunsab_ports);
1108 sunsab_ports = NULL;
1109
1110 return ret;
1111 }
1112
1113 sunserial_current_minor += num_channels;
1114
1115 for (i = 0; i < num_channels; i++) {
1116 struct uart_sunsab_port *up = &sunsab_ports[i];
1117
1118 uart_add_one_port(&sunsab_reg, &up->port);
1119 }
1120
1121 sunsab_console_init();
1122
1123 return 0;
1124 }
1125
1126 static void __exit sunsab_exit(void)
1127 {
1128 int i;
1129
1130 for (i = 0; i < num_channels; i++) {
1131 struct uart_sunsab_port *up = &sunsab_ports[i];
1132
1133 uart_remove_one_port(&sunsab_reg, &up->port);
1134
1135 if (!(up->port.line & 0x01))
1136 free_irq(up->port.irq, up);
1137 iounmap(up->regs);
1138 }
1139
1140 sunserial_current_minor -= num_channels;
1141 uart_unregister_driver(&sunsab_reg);
1142
1143 kfree(sunsab_ports);
1144 sunsab_ports = NULL;
1145 }
1146
1147 module_init(sunsab_init);
1148 module_exit(sunsab_exit);
1149
1150 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1151 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1152 MODULE_LICENSE("GPL");
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