?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
More meth updates.
[linux-2.6/linux-mips.git] / drivers / serial / ip22zilog.c
blobc7e0c4d3a882ae0f5374f4b47bc8e01b80938e96
1 /*
2 * Driver for Zilog serial chips found on SGI workstations and
3 * servers. This driver could actually be made more generic.
4 *
5 * This is based on the drivers/serial/sunzilog.c code as of 2.5.70 and the
6 * old drivers/sgi/char/sgiserial.c code which itself is based of the original
7 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over
8 * directly from there but much has been rewritten. Credits therefore go out
9 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell
10 * for their work there.
11 *
12 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
14 */
15 #include <linux/config.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/errno.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/major.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/circ_buf.h>
29 #include <linux/serial.h>
30 #include <linux/console.h>
31 #include <linux/spinlock.h>
32 #include <linux/init.h>
33
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/sgialib.h>
37 #include <asm/sgi/ioc.h>
38 #include <asm/sgi/hpc3.h>
39 #include <asm/sgi/ip22.h>
40
41 #include <linux/serial_core.h>
42
43 #include "ip22zilog.h"
44
45 int ip22serial_current_minor = 64;
46
47 void ip22_do_break(void);
48
49 /*
50 * On IP22 we need to delay after register accesses but we do not need to
51 * flush writes.
52 */
53 #define ZSDELAY() udelay(5)
54 #define ZSDELAY_LONG() udelay(20)
55 #define ZS_WSYNC(channel) do { } while (0)
56
57 #define NUM_IP22ZILOG 1
58 #define NUM_CHANNELS (NUM_IP22ZILOG * 2)
59
60 #define ZS_CLOCK 4915200 /* Zilog input clock rate. */
61 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
62
63 /*
64 * We wrap our port structure around the generic uart_port.
65 */
66 struct uart_ip22zilog_port {
67 struct uart_port port;
68
69 /* IRQ servicing chain. */
70 struct uart_ip22zilog_port *next;
71
72 /* Current values of Zilog write registers. */
73 unsigned char curregs[NUM_ZSREGS];
74
75 unsigned int flags;
76 #define IP22ZILOG_FLAG_IS_CONS 0x00000004
77 #define IP22ZILOG_FLAG_IS_KGDB 0x00000008
78 #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010
79 #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020
80 #define IP22ZILOG_FLAG_REGS_HELD 0x00000040
81 #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080
82 #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100
83
84 unsigned int cflag;
85
86 /* L1-A keyboard break state. */
87 int kbd_id;
88 int l1_down;
89
90 unsigned char parity_mask;
91 unsigned char prev_status;
92 };
93
94 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
95 #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))
96 #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \
97 (UART_ZILOG(PORT)->curregs[REGNUM])
98 #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \
99 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
100 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
101 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
102 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
103 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
104 #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
105 #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
106 #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
107
108 /* Reading and writing Zilog8530 registers. The delays are to make this
109 * driver work on the IP22 which needs a settling delay after each chip
110 * register access, other machines handle this in hardware via auxiliary
111 * flip-flops which implement the settle time we do in software.
112 *
113 * The port lock must be held and local IRQs must be disabled
114 * when {read,write}_zsreg is invoked.
115 */
116 static unsigned char read_zsreg(struct zilog_channel *channel,
117 unsigned char reg)
118 {
119 unsigned char retval;
120
121 writeb(reg, &channel->control);
122 ZSDELAY();
123 retval = readb(&channel->control);
124 ZSDELAY();
125
126 return retval;
127 }
128
129 static void write_zsreg(struct zilog_channel *channel,
130 unsigned char reg, unsigned char value)
131 {
132 writeb(reg, &channel->control);
133 ZSDELAY();
134 writeb(value, &channel->control);
135 ZSDELAY();
136 }
137
138 static void ip22zilog_clear_fifo(struct zilog_channel *channel)
139 {
140 int i;
141
142 for (i = 0; i < 32; i++) {
143 unsigned char regval;
144
145 regval = readb(&channel->control);
146 ZSDELAY();
147 if (regval & Rx_CH_AV)
148 break;
149
150 regval = read_zsreg(channel, R1);
151 readb(&channel->data);
152 ZSDELAY();
153
154 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
155 writeb(ERR_RES, &channel->control);
156 ZSDELAY();
157 ZS_WSYNC(channel);
158 }
159 }
160 }
161
162 /* This function must only be called when the TX is not busy. The UART
163 * port lock must be held and local interrupts disabled.
164 */
165 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
166 {
167 int i;
168
169 /* Let pending transmits finish. */
170 for (i = 0; i < 1000; i++) {
171 unsigned char stat = read_zsreg(channel, R1);
172 if (stat & ALL_SNT)
173 break;
174 udelay(100);
175 }
176
177 writeb(ERR_RES, &channel->control);
178 ZSDELAY();
179 ZS_WSYNC(channel);
180
181 ip22zilog_clear_fifo(channel);
182
183 /* Disable all interrupts. */
184 write_zsreg(channel, R1,
185 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
186
187 /* Set parity, sync config, stop bits, and clock divisor. */
188 write_zsreg(channel, R4, regs[R4]);
189
190 /* Set misc. TX/RX control bits. */
191 write_zsreg(channel, R10, regs[R10]);
192
193 /* Set TX/RX controls sans the enable bits. */
194 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
195 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
196
197 /* Synchronous mode config. */
198 write_zsreg(channel, R6, regs[R6]);
199 write_zsreg(channel, R7, regs[R7]);
200
201 /* Don't mess with the interrupt vector (R2, unused by us) and
202 * master interrupt control (R9). We make sure this is setup
203 * properly at probe time then never touch it again.
204 */
205
206 /* Disable baud generator. */
207 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
208
209 /* Clock mode control. */
210 write_zsreg(channel, R11, regs[R11]);
211
212 /* Lower and upper byte of baud rate generator divisor. */
213 write_zsreg(channel, R12, regs[R12]);
214 write_zsreg(channel, R13, regs[R13]);
215
216 /* Now rewrite R14, with BRENAB (if set). */
217 write_zsreg(channel, R14, regs[R14]);
218
219 /* External status interrupt control. */
220 write_zsreg(channel, R15, regs[R15]);
221
222 /* Reset external status interrupts. */
223 write_zsreg(channel, R0, RES_EXT_INT);
224 write_zsreg(channel, R0, RES_EXT_INT);
225
226 /* Rewrite R3/R5, this time without enables masked. */
227 write_zsreg(channel, R3, regs[R3]);
228 write_zsreg(channel, R5, regs[R5]);
229
230 /* Rewrite R1, this time without IRQ enabled masked. */
231 write_zsreg(channel, R1, regs[R1]);
232 }
233
234 /* Reprogram the Zilog channel HW registers with the copies found in the
235 * software state struct. If the transmitter is busy, we defer this update
236 * until the next TX complete interrupt. Else, we do it right now.
237 *
238 * The UART port lock must be held and local interrupts disabled.
239 */
240 static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
241 struct zilog_channel *channel)
242 {
243 if (!ZS_REGS_HELD(up)) {
244 if (ZS_TX_ACTIVE(up)) {
245 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
246 } else {
247 __load_zsregs(channel, up->curregs);
248 }
249 }
250 }
251
252 static void ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
253 struct zilog_channel *channel,
254 struct pt_regs *regs)
255 {
256 struct tty_struct *tty = up->port.info->tty; /* XXX info==NULL? */
257
258 while (1) {
259 unsigned char ch, r1;
260
261 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
262 tty->flip.work.func((void *)tty);
263 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
264 return; /* XXX Ignores SysRq when we need it most. Fix. */
265 }
266
267 r1 = read_zsreg(channel, R1);
268 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
269 writeb(ERR_RES, &channel->control);
270 ZSDELAY();
271 ZS_WSYNC(channel);
272 }
273
274 ch = readb(&channel->control);
275 ZSDELAY();
276
277 /* This funny hack depends upon BRK_ABRT not interfering
278 * with the other bits we care about in R1.
279 */
280 if (ch & BRK_ABRT)
281 r1 |= BRK_ABRT;
282
283 ch = readb(&channel->data);
284 ZSDELAY();
285
286 ch &= up->parity_mask;
287
288 if (ZS_IS_CONS(up) && (r1 & BRK_ABRT)) {
289 /* Wait for BREAK to deassert to avoid potentially
290 * confusing the PROM.
291 */
292 while (1) {
293 ch = readb(&channel->control);
294 ZSDELAY();
295 if (!(ch & BRK_ABRT))
296 break;
297 }
298 ip22_do_break();
299 return;
300 }
301
302 /* A real serial line, record the character and status. */
303 *tty->flip.char_buf_ptr = ch;
304 *tty->flip.flag_buf_ptr = TTY_NORMAL;
305 up->port.icount.rx++;
306 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
307 if (r1 & BRK_ABRT) {
308 r1 &= ~(PAR_ERR | CRC_ERR);
309 up->port.icount.brk++;
310 if (uart_handle_break(&up->port))
311 goto next_char;
312 }
313 else if (r1 & PAR_ERR)
314 up->port.icount.parity++;
315 else if (r1 & CRC_ERR)
316 up->port.icount.frame++;
317 if (r1 & Rx_OVR)
318 up->port.icount.overrun++;
319 r1 &= up->port.read_status_mask;
320 if (r1 & BRK_ABRT)
321 *tty->flip.flag_buf_ptr = TTY_BREAK;
322 else if (r1 & PAR_ERR)
323 *tty->flip.flag_buf_ptr = TTY_PARITY;
324 else if (r1 & CRC_ERR)
325 *tty->flip.flag_buf_ptr = TTY_FRAME;
326 }
327 if (uart_handle_sysrq_char(&up->port, ch, regs))
328 goto next_char;
329
330 if (up->port.ignore_status_mask == 0xff ||
331 (r1 & up->port.ignore_status_mask) == 0) {
332 tty->flip.flag_buf_ptr++;
333 tty->flip.char_buf_ptr++;
334 tty->flip.count++;
335 }
336 if ((r1 & Rx_OVR) &&
337 tty->flip.count < TTY_FLIPBUF_SIZE) {
338 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
339 tty->flip.flag_buf_ptr++;
340 tty->flip.char_buf_ptr++;
341 tty->flip.count++;
342 }
343 next_char:
344 ch = readb(&channel->control);
345 ZSDELAY();
346 if (!(ch & Rx_CH_AV))
347 break;
348 }
349
350 tty_flip_buffer_push(tty);
351 }
352
353 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
354 struct zilog_channel *channel,
355 struct pt_regs *regs)
356 {
357 unsigned char status;
358
359 status = readb(&channel->control);
360 ZSDELAY();
361
362 writeb(RES_EXT_INT, &channel->control);
363 ZSDELAY();
364 ZS_WSYNC(channel);
365
366 if (ZS_WANTS_MODEM_STATUS(up)) {
367 if (status & SYNC)
368 up->port.icount.dsr++;
369
370 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
371 * But it does not tell us which bit has changed, we have to keep
372 * track of this ourselves.
373 */
374 if ((status & DCD) ^ up->prev_status)
375 uart_handle_dcd_change(&up->port,
376 (status & DCD));
377 if ((status & CTS) ^ up->prev_status)
378 uart_handle_cts_change(&up->port,
379 (status & CTS));
380
381 wake_up_interruptible(&up->port.info->delta_msr_wait);
382 }
383
384 up->prev_status = status;
385 }
386
387 static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
388 struct zilog_channel *channel)
389 {
390 struct circ_buf *xmit;
391
392 if (ZS_IS_CONS(up)) {
393 unsigned char status = readb(&channel->control);
394 ZSDELAY();
395
396 /* TX still busy? Just wait for the next TX done interrupt.
397 *
398 * It can occur because of how we do serial console writes. It would
399 * be nice to transmit console writes just like we normally would for
400 * a TTY line. (ie. buffered and TX interrupt driven). That is not
401 * easy because console writes cannot sleep. One solution might be
402 * to poll on enough port->xmit space becomming free. -DaveM
403 */
404 if (!(status & Tx_BUF_EMP))
405 return;
406 }
407
408 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
409
410 if (ZS_REGS_HELD(up)) {
411 __load_zsregs(channel, up->curregs);
412 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
413 }
414
415 if (ZS_TX_STOPPED(up)) {
416 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
417 goto ack_tx_int;
418 }
419
420 if (up->port.x_char) {
421 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
422 writeb(up->port.x_char, &channel->data);
423 ZSDELAY();
424 ZS_WSYNC(channel);
425
426 up->port.icount.tx++;
427 up->port.x_char = 0;
428 return;
429 }
430
431 if (up->port.info == NULL)
432 goto ack_tx_int;
433 xmit = &up->port.info->xmit;
434 if (uart_circ_empty(xmit)) {
435 uart_write_wakeup(&up->port);
436 goto ack_tx_int;
437 }
438 if (uart_tx_stopped(&up->port))
439 goto ack_tx_int;
440
441 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
442 writeb(xmit->buf[xmit->tail], &channel->data);
443 ZSDELAY();
444 ZS_WSYNC(channel);
445
446 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
447 up->port.icount.tx++;
448
449 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
450 uart_write_wakeup(&up->port);
451
452 return;
453
454 ack_tx_int:
455 writeb(RES_Tx_P, &channel->control);
456 ZSDELAY();
457 ZS_WSYNC(channel);
458 }
459
460 static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
461 {
462 struct uart_ip22zilog_port *up = dev_id;
463
464 while (up) {
465 struct zilog_channel *channel
466 = ZILOG_CHANNEL_FROM_PORT(&up->port);
467 unsigned char r3;
468
469 spin_lock(&up->port.lock);
470 r3 = read_zsreg(channel, R3);
471
472 /* Channel A */
473 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
474 writeb(RES_H_IUS, &channel->control);
475 ZSDELAY();
476 ZS_WSYNC(channel);
477
478 if (r3 & CHARxIP)
479 ip22zilog_receive_chars(up, channel, regs);
480 if (r3 & CHAEXT)
481 ip22zilog_status_handle(up, channel, regs);
482 if (r3 & CHATxIP)
483 ip22zilog_transmit_chars(up, channel);
484 }
485 spin_unlock(&up->port.lock);
486
487 /* Channel B */
488 up = up->next;
489 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
490
491 spin_lock(&up->port.lock);
492 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
493 writeb(RES_H_IUS, &channel->control);
494 ZSDELAY();
495 ZS_WSYNC(channel);
496
497 if (r3 & CHBRxIP)
498 ip22zilog_receive_chars(up, channel, regs);
499 if (r3 & CHBEXT)
500 ip22zilog_status_handle(up, channel, regs);
501 if (r3 & CHBTxIP)
502 ip22zilog_transmit_chars(up, channel);
503 }
504 spin_unlock(&up->port.lock);
505
506 up = up->next;
507 }
508
509 return IRQ_HANDLED;
510 }
511
512 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
513 * port lock, it is acquired here.
514 */
515 static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
516 {
517 struct zilog_channel *channel;
518 unsigned long flags;
519 unsigned char status;
520
521 spin_lock_irqsave(&port->lock, flags);
522
523 channel = ZILOG_CHANNEL_FROM_PORT(port);
524 status = readb(&channel->control);
525 ZSDELAY();
526
527 spin_unlock_irqrestore(&port->lock, flags);
528
529 return status;
530 }
531
532 /* The port lock is not held. */
533 static unsigned int ip22zilog_tx_empty(struct uart_port *port)
534 {
535 unsigned char status;
536 unsigned int ret;
537
538 status = ip22zilog_read_channel_status(port);
539 if (status & Tx_BUF_EMP)
540 ret = TIOCSER_TEMT;
541 else
542 ret = 0;
543
544 return ret;
545 }
546
547 /* The port lock is not held. */
548 static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
549 {
550 unsigned char status;
551 unsigned int ret;
552
553 status = ip22zilog_read_channel_status(port);
554
555 ret = 0;
556 if (status & DCD)
557 ret |= TIOCM_CAR;
558 if (status & SYNC)
559 ret |= TIOCM_DSR;
560 if (status & CTS)
561 ret |= TIOCM_CTS;
562
563 return ret;
564 }
565
566 /* The port lock is held and interrupts are disabled. */
567 static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
568 {
569 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
570 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
571 unsigned char set_bits, clear_bits;
572
573 set_bits = clear_bits = 0;
574
575 if (mctrl & TIOCM_RTS)
576 set_bits |= RTS;
577 else
578 clear_bits |= RTS;
579 if (mctrl & TIOCM_DTR)
580 set_bits |= DTR;
581 else
582 clear_bits |= DTR;
583
584 /* NOTE: Not subject to 'transmitter active' rule. */
585 up->curregs[R5] |= set_bits;
586 up->curregs[R5] &= ~clear_bits;
587 write_zsreg(channel, R5, up->curregs[R5]);
588 }
589
590 /* The port lock is held and interrupts are disabled. */
591 static void ip22zilog_stop_tx(struct uart_port *port, unsigned int tty_stop)
592 {
593 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
594
595 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
596 }
597
598 /* The port lock is held and interrupts are disabled. */
599 static void ip22zilog_start_tx(struct uart_port *port, unsigned int tty_start)
600 {
601 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
602 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
603 unsigned char status;
604
605 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
606 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
607
608 status = readb(&channel->control);
609 ZSDELAY();
610
611 /* TX busy? Just wait for the TX done interrupt. */
612 if (!(status & Tx_BUF_EMP))
613 return;
614
615 /* Send the first character to jump-start the TX done
616 * IRQ sending engine.
617 */
618 if (port->x_char) {
619 writeb(port->x_char, &channel->data);
620 ZSDELAY();
621 ZS_WSYNC(channel);
622
623 port->icount.tx++;
624 port->x_char = 0;
625 } else {
626 struct circ_buf *xmit = &port->info->xmit;
627
628 writeb(xmit->buf[xmit->tail], &channel->data);
629 ZSDELAY();
630 ZS_WSYNC(channel);
631
632 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
633 port->icount.tx++;
634
635 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
636 uart_write_wakeup(&up->port);
637 }
638 }
639
640 /* The port lock is not held. */
641 static void ip22zilog_stop_rx(struct uart_port *port)
642 {
643 struct uart_ip22zilog_port *up = UART_ZILOG(port);
644 struct zilog_channel *channel;
645 unsigned long flags;
646
647 if (ZS_IS_CONS(up))
648 return;
649
650 spin_lock_irqsave(&port->lock, flags);
651
652 channel = ZILOG_CHANNEL_FROM_PORT(port);
653
654 /* Disable all RX interrupts. */
655 up->curregs[R1] &= ~RxINT_MASK;
656 ip22zilog_maybe_update_regs(up, channel);
657
658 spin_unlock_irqrestore(&port->lock, flags);
659 }
660
661 /* The port lock is not held. */
662 static void ip22zilog_enable_ms(struct uart_port *port)
663 {
664 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
665 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
666 unsigned char new_reg;
667 unsigned long flags;
668
669 spin_lock_irqsave(&port->lock, flags);
670
671 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
672 if (new_reg != up->curregs[R15]) {
673 up->curregs[R15] = new_reg;
674
675 /* NOTE: Not subject to 'transmitter active' rule. */
676 write_zsreg(channel, R15, up->curregs[R15]);
677 }
678
679 spin_unlock_irqrestore(&port->lock, flags);
680 }
681
682 /* The port lock is not held. */
683 static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
684 {
685 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
686 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
687 unsigned char set_bits, clear_bits, new_reg;
688 unsigned long flags;
689
690 set_bits = clear_bits = 0;
691
692 if (break_state)
693 set_bits |= SND_BRK;
694 else
695 clear_bits |= SND_BRK;
696
697 spin_lock_irqsave(&port->lock, flags);
698
699 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
700 if (new_reg != up->curregs[R5]) {
701 up->curregs[R5] = new_reg;
702
703 /* NOTE: Not subject to 'transmitter active' rule. */
704 write_zsreg(channel, R5, up->curregs[R5]);
705 }
706
707 spin_unlock_irqrestore(&port->lock, flags);
708 }
709
710 static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
711 {
712 struct zilog_channel *channel;
713
714 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
715 up->prev_status = readb(&channel->control);
716
717 /* Enable receiver and transmitter. */
718 up->curregs[R3] |= RxENAB;
719 up->curregs[R5] |= TxENAB;
720
721 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
722 ip22zilog_maybe_update_regs(up, channel);
723 }
724
725 static int ip22zilog_startup(struct uart_port *port)
726 {
727 struct uart_ip22zilog_port *up = UART_ZILOG(port);
728 unsigned long flags;
729
730 if (ZS_IS_CONS(up))
731 return 0;
732
733 spin_lock_irqsave(&port->lock, flags);
734 __ip22zilog_startup(up);
735 spin_unlock_irqrestore(&port->lock, flags);
736 return 0;
737 }
738
739 /*
740 * The test for ZS_IS_CONS is explained by the following e-mail:
741 *****
742 * From: Russell King <rmk@arm.linux.org.uk>
743 * Date: Sun, 8 Dec 2002 10:18:38 +0000
744 *
745 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
746 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
747 * > and I noticed that something is not right with reference
748 * > counting in this case. It seems that when the console
749 * > is open by kernel initially, this is not accounted
750 * > as an open, and uart_startup is not called.
751 *
752 * That is correct. We are unable to call uart_startup when the serial
753 * console is initialised because it may need to allocate memory (as
754 * request_irq does) and the memory allocators may not have been
755 * initialised.
756 *
757 * 1. initialise the port into a state where it can send characters in the
758 * console write method.
759 *
760 * 2. don't do the actual hardware shutdown in your shutdown() method (but
761 * do the normal software shutdown - ie, free irqs etc)
762 *****
763 */
764 static void ip22zilog_shutdown(struct uart_port *port)
765 {
766 struct uart_ip22zilog_port *up = UART_ZILOG(port);
767 struct zilog_channel *channel;
768 unsigned long flags;
769
770 if (ZS_IS_CONS(up))
771 return;
772
773 spin_lock_irqsave(&port->lock, flags);
774
775 channel = ZILOG_CHANNEL_FROM_PORT(port);
776
777 /* Disable receiver and transmitter. */
778 up->curregs[R3] &= ~RxENAB;
779 up->curregs[R5] &= ~TxENAB;
780
781 /* Disable all interrupts and BRK assertion. */
782 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
783 up->curregs[R5] &= ~SND_BRK;
784 ip22zilog_maybe_update_regs(up, channel);
785
786 spin_unlock_irqrestore(&port->lock, flags);
787 }
788
789 /* Shared by TTY driver and serial console setup. The port lock is held
790 * and local interrupts are disabled.
791 */
792 static void
793 ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
794 unsigned int iflag, int brg)
795 {
796
797 up->curregs[R10] = NRZ;
798 up->curregs[R11] = TCBR | RCBR;
799
800 /* Program BAUD and clock source. */
801 up->curregs[R4] &= ~XCLK_MASK;
802 up->curregs[R4] |= X16CLK;
803 up->curregs[R12] = brg & 0xff;
804 up->curregs[R13] = (brg >> 8) & 0xff;
805 up->curregs[R14] = BRSRC | BRENAB;
806
807 /* Character size, stop bits, and parity. */
808 up->curregs[3] &= ~RxN_MASK;
809 up->curregs[5] &= ~TxN_MASK;
810 switch (cflag & CSIZE) {
811 case CS5:
812 up->curregs[3] |= Rx5;
813 up->curregs[5] |= Tx5;
814 up->parity_mask = 0x1f;
815 break;
816 case CS6:
817 up->curregs[3] |= Rx6;
818 up->curregs[5] |= Tx6;
819 up->parity_mask = 0x3f;
820 break;
821 case CS7:
822 up->curregs[3] |= Rx7;
823 up->curregs[5] |= Tx7;
824 up->parity_mask = 0x7f;
825 break;
826 case CS8:
827 default:
828 up->curregs[3] |= Rx8;
829 up->curregs[5] |= Tx8;
830 up->parity_mask = 0xff;
831 break;
832 };
833 up->curregs[4] &= ~0x0c;
834 if (cflag & CSTOPB)
835 up->curregs[4] |= SB2;
836 else
837 up->curregs[4] |= SB1;
838 if (cflag & PARENB)
839 up->curregs[4] |= PAR_ENAB;
840 else
841 up->curregs[4] &= ~PAR_ENAB;
842 if (!(cflag & PARODD))
843 up->curregs[4] |= PAR_EVEN;
844 else
845 up->curregs[4] &= ~PAR_EVEN;
846
847 up->port.read_status_mask = Rx_OVR;
848 if (iflag & INPCK)
849 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
850 if (iflag & (BRKINT | PARMRK))
851 up->port.read_status_mask |= BRK_ABRT;
852
853 up->port.ignore_status_mask = 0;
854 if (iflag & IGNPAR)
855 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
856 if (iflag & IGNBRK) {
857 up->port.ignore_status_mask |= BRK_ABRT;
858 if (iflag & IGNPAR)
859 up->port.ignore_status_mask |= Rx_OVR;
860 }
861
862 if ((cflag & CREAD) == 0)
863 up->port.ignore_status_mask = 0xff;
864 }
865
866 /* The port lock is not held. */
867 static void
868 ip22zilog_set_termios(struct uart_port *port, struct termios *termios,
869 struct termios *old)
870 {
871 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
872 unsigned long flags;
873 int baud, brg;
874
875 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
876
877 spin_lock_irqsave(&up->port.lock, flags);
878
879 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
880
881 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
882
883 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
884 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
885 else
886 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
887
888 up->cflag = termios->c_cflag;
889
890 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
891
892 spin_unlock_irqrestore(&up->port.lock, flags);
893 }
894
895 static const char *ip22zilog_type(struct uart_port *port)
896 {
897 return "IP22-Zilog";
898 }
899
900 /* We do not request/release mappings of the registers here, this
901 * happens at early serial probe time.
902 */
903 static void ip22zilog_release_port(struct uart_port *port)
904 {
905 }
906
907 static int ip22zilog_request_port(struct uart_port *port)
908 {
909 return 0;
910 }
911
912 /* These do not need to do anything interesting either. */
913 static void ip22zilog_config_port(struct uart_port *port, int flags)
914 {
915 }
916
917 /* We do not support letting the user mess with the divisor, IRQ, etc. */
918 static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)
919 {
920 return -EINVAL;
921 }
922
923 static struct uart_ops ip22zilog_pops = {
924 .tx_empty = ip22zilog_tx_empty,
925 .set_mctrl = ip22zilog_set_mctrl,
926 .get_mctrl = ip22zilog_get_mctrl,
927 .stop_tx = ip22zilog_stop_tx,
928 .start_tx = ip22zilog_start_tx,
929 .stop_rx = ip22zilog_stop_rx,
930 .enable_ms = ip22zilog_enable_ms,
931 .break_ctl = ip22zilog_break_ctl,
932 .startup = ip22zilog_startup,
933 .shutdown = ip22zilog_shutdown,
934 .set_termios = ip22zilog_set_termios,
935 .type = ip22zilog_type,
936 .release_port = ip22zilog_release_port,
937 .request_port = ip22zilog_request_port,
938 .config_port = ip22zilog_config_port,
939 .verify_port = ip22zilog_verify_port,
940 };
941
942 static struct uart_ip22zilog_port *ip22zilog_port_table;
943 static struct zilog_layout **ip22zilog_chip_regs;
944
945 static struct uart_ip22zilog_port *ip22zilog_irq_chain;
946 static int zilog_irq = -1;
947
948 static struct uart_driver ip22zilog_reg = {
949 .owner = THIS_MODULE,
950 .driver_name = "ttyS",
951 #ifdef CONFIG_DEVFS_FS
952 .dev_name = "tty/",
953 #else
954 .dev_name = "tty/",
955 #endif
956 .major = TTY_MAJOR,
957 };
958
959 static void * __init alloc_one_table(unsigned long size)
960 {
961 void *ret;
962
963 ret = kmalloc(size, GFP_KERNEL);
964 if (ret != NULL)
965 memset(ret, 0, size);
966
967 return ret;
968 }
969
970 static void __init ip22zilog_alloc_tables(void)
971 {
972 ip22zilog_port_table = (struct uart_ip22zilog_port *)
973 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port));
974 ip22zilog_chip_regs = (struct zilog_layout **)
975 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *));
976
977 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) {
978 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables.");
979 }
980 }
981
982 /* Get the address of the registers for IP22-Zilog instance CHIP. */
983 static struct zilog_layout * __init get_zs(int chip)
984 {
985 unsigned long base;
986
987 if (chip < 0 || chip >= NUM_IP22ZILOG) {
988 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip);
989 }
990
991 /* Not probe-able, hard code it. */
992 base = (unsigned long) &sgioc->serport;
993
994 zilog_irq = SGI_SERIAL_IRQ;
995 request_mem_region(base, 8, "IP22-Zilog");
996
997 return (struct zilog_layout *) base;
998 }
999
1000 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
1001
1002 static void ip22zilog_put_char(struct zilog_channel *channel, unsigned char ch)
1003 {
1004 int loops = ZS_PUT_CHAR_MAX_DELAY;
1005
1006 /* This is a timed polling loop so do not switch the explicit
1007 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1008 */
1009 do {
1010 unsigned char val = readb(&channel->control);
1011 if (val & Tx_BUF_EMP) {
1012 ZSDELAY();
1013 break;
1014 }
1015 udelay(5);
1016 } while (--loops);
1017
1018 writeb(ch, &channel->data);
1019 ZSDELAY();
1020 ZS_WSYNC(channel);
1021 }
1022
1023 static void
1024 ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
1025 {
1026 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1027 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1028 unsigned long flags;
1029 int i;
1030
1031 spin_lock_irqsave(&up->port.lock, flags);
1032 for (i = 0; i < count; i++, s++) {
1033 ip22zilog_put_char(channel, *s);
1034 if (*s == 10)
1035 ip22zilog_put_char(channel, 13);
1036 }
1037 udelay(2);
1038 spin_unlock_irqrestore(&up->port.lock, flags);
1039 }
1040
1041 void
1042 ip22serial_console_termios(struct console *con, char *options)
1043 {
1044 int baud = 9600, bits = 8, cflag;
1045 int parity = 'n';
1046 int flow = 'n';
1047 char *dbaud;
1048
1049 if (!serial_console)
1050 return;
1051
1052 if (options)
1053 uart_parse_options(options, &baud, &parity, &bits, &flow);
1054
1055 /*
1056 * If the user doesn't supply a console=... option try to read the
1057 * dbaud PROM variable - if this fails use 9600 baud and
1058 * inform the user about the problem
1059 */
1060 dbaud = ArcGetEnvironmentVariable("dbaud");
1061 if (dbaud)
1062 baud = simple_strtoul(dbaud, NULL, 10);
1063 else {
1064 printk("No dbaud variable, defaulting to 9600.\n");
1065 baud = 9600;
1066 }
1067
1068 cflag = CREAD | HUPCL | CLOCAL;
1069
1070 switch (baud) {
1071 case 150: cflag |= B150; break;
1072 case 300: cflag |= B300; break;
1073 case 600: cflag |= B600; break;
1074 case 1200: cflag |= B1200; break;
1075 case 2400: cflag |= B2400; break;
1076 case 4800: cflag |= B4800; break;
1077 case 9600: cflag |= B9600; break;
1078 case 19200: cflag |= B19200; break;
1079 case 38400: cflag |= B38400; break;
1080 default: baud = 9600; cflag |= B9600; break;
1081 }
1082
1083 con->cflag = cflag | CS8; /* 8N1 */
1084 }
1085
1086 static int __init ip22zilog_console_setup(struct console *con, char *options)
1087 {
1088 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1089 unsigned long flags;
1090 int baud, brg;
1091
1092 printk("Console: ttyS%d (IP22-Zilog)\n",
1093 (ip22zilog_reg.minor - 64) + con->index);
1094
1095 /* Get firmware console settings. */
1096 ip22serial_console_termios(con, options);
1097
1098 /* Firmware console speed is limited to 150-->38400 baud so
1099 * this hackish cflag thing is OK.
1100 */
1101 switch (con->cflag & CBAUD) {
1102 case B150: baud = 150; break;
1103 case B300: baud = 300; break;
1104 case B600: baud = 600; break;
1105 case B1200: baud = 1200; break;
1106 case B2400: baud = 2400; break;
1107 case B4800: baud = 4800; break;
1108 default: case B9600: baud = 9600; break;
1109 case B19200: baud = 19200; break;
1110 case B38400: baud = 38400; break;
1111 };
1112
1113 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1114
1115 spin_lock_irqsave(&up->port.lock, flags);
1116
1117 up->curregs[R15] = BRKIE;
1118 ip22zilog_convert_to_zs(up, con->cflag, 0, brg);
1119
1120 __ip22zilog_startup(up);
1121
1122 spin_unlock_irqrestore(&up->port.lock, flags);
1123
1124 return 0;
1125 }
1126
1127 static struct console ip22zilog_console = {
1128 .name = "ttyS",
1129 .write = ip22zilog_console_write,
1130 .device = uart_console_device,
1131 .setup = ip22zilog_console_setup,
1132 .flags = CON_PRINTBUFFER,
1133 .index = -1,
1134 .data = &ip22zilog_reg,
1135 };
1136
1137 static int __init ip22zilog_console_init(void)
1138 {
1139 int i;
1140
1141 if (con_is_present())
1142 return 0;
1143
1144 for (i = 0; i < NUM_CHANNELS; i++) {
1145 int this_minor = ip22zilog_reg.minor + i;
1146
1147 if ((this_minor - 64) == (serial_console - 1))
1148 break;
1149 }
1150 if (i == NUM_CHANNELS)
1151 return 0;
1152
1153 ip22zilog_console.index = i;
1154 register_console(&ip22zilog_console);
1155 return 0;
1156 }
1157
1158 static void __init ip22zilog_prepare(void)
1159 {
1160 struct uart_ip22zilog_port *up;
1161 struct zilog_layout *rp;
1162 int channel, chip;
1163
1164 /*
1165 * Temporary fix.
1166 */
1167 for (channel = 0; channel < NUM_CHANNELS; channel++)
1168 spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1169
1170 ip22zilog_irq_chain = up = &ip22zilog_port_table[0];
1171 for (channel = 0; channel < NUM_CHANNELS - 1; channel++)
1172 up[channel].next = &up[channel + 1];
1173 up[channel].next = NULL;
1174
1175 for (chip = 0; chip < NUM_IP22ZILOG; chip++) {
1176 if (!ip22zilog_chip_regs[chip]) {
1177 ip22zilog_chip_regs[chip] = rp = get_zs(chip);
1178
1179 up[(chip * 2) + 0].port.membase = (char *) &rp->channelA;
1180 up[(chip * 2) + 1].port.membase = (char *) &rp->channelB;
1181 }
1182
1183 /* Channel A */
1184 up[(chip * 2) + 0].port.iotype = SERIAL_IO_MEM;
1185 up[(chip * 2) + 0].port.irq = zilog_irq;
1186 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1187 up[(chip * 2) + 0].port.fifosize = 1;
1188 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1189 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1190 up[(chip * 2) + 0].port.flags = 0;
1191 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1192 up[(chip * 2) + 0].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1193
1194 /* Channel B */
1195 up[(chip * 2) + 1].port.iotype = SERIAL_IO_MEM;
1196 up[(chip * 2) + 1].port.irq = zilog_irq;
1197 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1198 up[(chip * 2) + 1].port.fifosize = 1;
1199 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1200 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1201 up[(chip * 2) + 1].port.flags = 0;
1202 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1203 up[(chip * 2) + 1].flags |= 0;
1204 }
1205 }
1206
1207 static void __init ip22zilog_init_hw(void)
1208 {
1209 int i;
1210
1211 for (i = 0; i < NUM_CHANNELS; i++) {
1212 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1213 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1214 unsigned long flags;
1215 int baud, brg;
1216
1217 spin_lock_irqsave(&up->port.lock, flags);
1218
1219 if (ZS_IS_CHANNEL_A(up)) {
1220 write_zsreg(channel, R9, FHWRES);
1221 ZSDELAY_LONG();
1222 (void) read_zsreg(channel, R0);
1223 }
1224
1225 /* Normal serial TTY. */
1226 up->parity_mask = 0xff;
1227 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1228 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1229 up->curregs[R3] = RxENAB | Rx8;
1230 up->curregs[R5] = TxENAB | Tx8;
1231 up->curregs[R9] = NV | MIE;
1232 up->curregs[R10] = NRZ;
1233 up->curregs[R11] = TCBR | RCBR;
1234 baud = 9600;
1235 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1236 up->curregs[R12] = (brg & 0xff);
1237 up->curregs[R13] = (brg >> 8) & 0xff;
1238 up->curregs[R14] = BRSRC | BRENAB;
1239 __load_zsregs(channel, up->curregs);
1240
1241 spin_unlock_irqrestore(&up->port.lock, flags);
1242 }
1243 }
1244
1245 static int __init ip22zilog_ports_init(void)
1246 {
1247 int ret;
1248
1249 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);
1250
1251 ip22zilog_prepare();
1252
1253 if (request_irq(zilog_irq, ip22zilog_interrupt, 0,
1254 "IP22-Zilog", ip22zilog_irq_chain)) {
1255 panic("IP22-Zilog: Unable to register zs interrupt handler.\n");
1256 }
1257
1258 ip22zilog_init_hw();
1259
1260 /* We can only init this once we have probed the Zilogs
1261 * in the system.
1262 */
1263 ip22zilog_reg.nr = NUM_CHANNELS;
1264 ip22zilog_reg.cons = &ip22zilog_console;
1265
1266 ip22zilog_reg.minor = ip22serial_current_minor;
1267 ip22serial_current_minor += NUM_CHANNELS;
1268
1269 ret = uart_register_driver(&ip22zilog_reg);
1270 if (ret == 0) {
1271 int i;
1272
1273 for (i = 0; i < NUM_CHANNELS; i++) {
1274 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1275
1276 uart_add_one_port(&ip22zilog_reg, &up->port);
1277 }
1278 }
1279
1280 return ret;
1281 }
1282
1283 static int __init ip22zilog_init(void)
1284 {
1285 /* IP22 Zilog setup is hard coded, no probing to do. */
1286
1287 ip22zilog_alloc_tables();
1288
1289 ip22zilog_ports_init();
1290 ip22zilog_console_init();
1291
1292 return 0;
1293 }
1294
1295 static void __exit ip22zilog_exit(void)
1296 {
1297 int i;
1298
1299 for (i = 0; i < NUM_CHANNELS; i++) {
1300 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1301
1302 uart_remove_one_port(&ip22zilog_reg, &up->port);
1303 }
1304
1305 uart_unregister_driver(&ip22zilog_reg);
1306 }
1307
1308 module_init(ip22zilog_init);
1309 module_exit(ip22zilog_exit);
1310
1311 /* David wrote it but I'm to blame for the bugs ... */
1312 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1313 MODULE_DESCRIPTION("SGI Zilog serial port driver");
1314 MODULE_LICENSE("GPL");
Mirror of the linux-mips.org kernel tree