2 ** PCI Lower Bus Adapter (LBA) manager
4 ** (c) Copyright 1999,2000 Grant Grundler
5 ** (c) Copyright 1999,2000 Hewlett-Packard Company
7 ** This program is free software; you can redistribute it and/or modify
8 ** it under the terms of the GNU General Public License as published by
9 ** the Free Software Foundation; either version 2 of the License, or
10 ** (at your option) any later version.
13 ** This module primarily provides access to PCI bus (config/IOport
14 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
15 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
17 ** LBA driver isn't as simple as the Dino driver because:
18 ** (a) this chip has substantial bug fixes between revisions
19 ** (Only one Dino bug has a software workaround :^( )
20 ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
21 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
22 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
23 ** (dino only deals with "Legacy" PDC)
25 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
26 ** (I/O SAPIC is integratd in the LBA chip).
28 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
29 ** FIXME: Add support for PCI card hot-plug (OLARD).
32 #include <linux/delay.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/spinlock.h>
36 #include <linux/init.h> /* for __init and __devinit */
37 /* #define PCI_DEBUG enable ASSERT */
38 #include <linux/pci.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/smp_lock.h>
43 #include <asm/byteorder.h>
44 #include <asm/irq.h> /* for struct irq_region support */
47 #include <asm/segment.h>
48 #include <asm/system.h>
50 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
51 #include <asm/parisc-device.h>
52 #include <asm/iosapic.h> /* for iosapic_register() */
53 #include <asm/io.h> /* read/write stuff */
57 #define FALSE (1 == 0)
60 #undef DEBUG_LBA /* general stuff */
61 #undef DEBUG_LBA_PORT /* debug I/O Port access */
62 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
63 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
65 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
69 #define DBG(x...) printk(x)
75 #define DBG_PORT(x...) printk(x)
77 #define DBG_PORT(x...)
81 #define DBG_CFG(x...) printk(x)
87 #define DBG_PAT(x...) printk(x)
93 ** Config accessor functions only pass in the 8-bit bus number and not
94 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
95 ** number based on what firmware wrote into the scratch register.
97 ** The "secondary" bus number is set to this before calling
98 ** pci_register_ops(). If any PPB's are present, the scan will
99 ** discover them and update the "secondary" and "subordinate"
100 ** fields in the pci_bus structure.
102 ** Changes in the configuration *may* result in a different
103 ** bus number for each LBA depending on what firmware does.
106 #define MODULE_NAME "lba"
108 #define LBA_FUNC_ID 0x0000 /* function id */
109 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
110 #define LBA_CAPABLE 0x0030 /* capabilities register */
112 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
113 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
115 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
116 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
117 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
119 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
120 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
121 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
122 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
124 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
126 #define LBA_STAT_CTL 0x0108 /* Status & Control */
127 #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
128 #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
129 #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
130 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
132 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
133 #define LBA_LMMIO_MASK 0x0208
135 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
136 #define LBA_GMMIO_MASK 0x0218
138 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
139 #define LBA_WLMMIO_MASK 0x0228
141 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
142 #define LBA_WGMMIO_MASK 0x0238
144 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
145 #define LBA_IOS_MASK 0x0248
147 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
148 #define LBA_ELMMIO_MASK 0x0258
150 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
151 #define LBA_EIOS_MASK 0x0268
153 #define LBA_DMA_CTL 0x0278 /* firmware sets this */
155 #define LBA_IBASE 0x0300 /* SBA DMA support */
156 #define LBA_IMASK 0x0308
158 /* FIXME: ignore DMA Hint stuff until we can measure performance */
159 #define LBA_HINT_CFG 0x0310
160 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
162 /* ERROR regs are needed for config cycle kluges */
163 #define LBA_ERROR_CONFIG 0x0680
164 #define LBA_SMART_MODE 0x20
165 #define LBA_ERROR_STATUS 0x0688
166 #define LBA_ROPE_CTL 0x06A0
168 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
170 /* non-postable I/O port space, densely packed */
172 #define LBA_ASTRO_PORT_BASE (0xfffffffffee00000UL)
174 #define LBA_ASTRO_PORT_BASE (0xfee00000UL)
179 ** lba_device: Per instance Elroy data structure
182 struct pci_hba_data hba
;
188 unsigned long lmmio_base
; /* PA_VIEW - fixup MEM addresses */
189 unsigned long gmmio_base
; /* PA_VIEW - Not used (yet) */
190 unsigned long iop_base
; /* PA_VIEW - for IO port accessor funcs */
193 int flags
; /* state/functionality enabled */
194 int hw_rev
; /* HW revision of chip */
203 #define LBA_FLAG_NO_DMA_DURING_CFG 0x01
204 #define LBA_FLAG_SKIP_PROBE 0x10
206 /* Tape Release 4 == hw_rev 5 */
207 #define LBA_TR4PLUS(d) ((d)->hw_rev > 0x4)
208 #define LBA_DMA_DURING_CFG_DISABLED(d) ((d)->flags & LBA_FLAG_NO_DMA_DURING_CFG)
209 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
212 /* Looks nice and keeps the compiler happy */
213 #define LBA_DEV(d) ((struct lba_device *) (d))
217 ** Only allow 8 subsidiary busses per LBA
218 ** Problem is the PCI bus numbering is globally shared.
220 #define LBA_MAX_NUM_BUSES 8
222 /************************************
223 * LBA register read and write support
225 * BE WARNED: register writes are posted.
226 * (ie follow writes which must reach HW with a read)
228 #define READ_U8(addr) __raw_readb(addr)
229 #define READ_U16(addr) __raw_readw(addr)
230 #define READ_U32(addr) __raw_readl(addr)
231 #define WRITE_U8(value, addr) __raw_writeb(value, addr)
232 #define WRITE_U16(value, addr) __raw_writew(value, addr)
233 #define WRITE_U32(value, addr) __raw_writel(value, addr)
235 #define READ_REG8(addr) readb(addr)
236 #define READ_REG16(addr) readw(addr)
237 #define READ_REG32(addr) readl(addr)
238 #define READ_REG64(addr) readq(addr)
239 #define WRITE_REG8(value, addr) writeb(value, addr)
240 #define WRITE_REG16(value, addr) writew(value, addr)
241 #define WRITE_REG32(value, addr) writel(value, addr)
244 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
245 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
246 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
247 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
251 ** Extract LBA (Rope) number from HPA
252 ** REVISIT: 16 ropes for Stretch/Ike?
254 #define ROPES_PER_SBA 8
255 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_SBA-1))
259 lba_dump_res(struct resource
*r
, int d
)
266 printk(KERN_DEBUG
"(%p)", r
->parent
);
267 for (i
= d
; i
; --i
) printk(" ");
268 printk(KERN_DEBUG
"%p [%lx,%lx]/%x\n", r
, r
->start
, r
->end
, (int) r
->flags
);
269 lba_dump_res(r
->child
, d
+2);
270 lba_dump_res(r
->sibling
, d
);
275 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
276 ** workaround for cfg cycles:
277 ** -- preserve LBA state
278 ** -- LBA_FLAG_NO_DMA_DURING_CFG workaround
279 ** -- turn on smart mode
280 ** -- probe with config writes before doing config reads
281 ** -- check ERROR_STATUS
282 ** -- clear ERROR_STATUS
283 ** -- restore LBA state
285 ** The workaround is only used for device discovery.
289 lba_device_present( u8 bus
, u8 dfn
, struct lba_device
*d
)
291 u8 first_bus
= d
->hba
.hba_bus
->secondary
;
292 u8 last_sub_bus
= d
->hba
.hba_bus
->subordinate
;
294 /* FIXME - see below in this function */
295 u8 dev
= PCI_SLOT(dfn
);
296 u8 func
= PCI_FUNC(dfn
);
299 ASSERT(bus
>= first_bus
);
300 ASSERT(bus
<= last_sub_bus
);
301 ASSERT((bus
- first_bus
) < LBA_MAX_NUM_BUSES
);
303 if ((bus
< first_bus
) ||
304 (bus
> last_sub_bus
) ||
305 ((bus
- first_bus
) >= LBA_MAX_NUM_BUSES
))
307 /* devices that fall into any of these cases won't get claimed */
313 ** FIXME: Need to implement code to fill the devices bitmap based
314 ** on contents of the local pci_bus tree "data base".
315 ** pci_register_ops() walks the bus for us and builds the tree.
316 ** For now, always do the config cycle.
320 return (((d
->devices
[bus
][dev
]) >> func
) & 0x1);
328 #define LBA_CFG_SETUP(d, tok) { \
329 /* Save contents of error config register. */ \
330 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
332 /* Save contents of status control register. */ \
333 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
335 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
336 ** arbitration for full bus walks. \
338 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
339 /* Save contents of arb mask register. */ \
340 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
343 * Turn off all device arbitration bits (i.e. everything \
344 * except arbitration enable bit). \
346 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
350 * Set the smart mode bit so that master aborts don't cause \
351 * LBA to go into PCI fatal mode (required). \
353 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
357 #define LBA_CFG_PROBE(d, tok) { \
359 * Setup Vendor ID write and read back the address register \
360 * to make sure that LBA is the bus master. \
362 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
364 * Read address register to ensure that LBA is the bus master, \
365 * which implies that DMA traffic has stopped when DMA arb is off. \
367 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
369 * Generate a cfg write cycle (will have no affect on \
370 * Vendor ID register since read-only). \
372 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
374 * Make sure write has completed before proceeding further, \
375 * i.e. before setting clear enable. \
377 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
383 * -- Can't tell if config cycle got the error.
385 * OV bit is broken until rev 4.0, so can't use OV bit and
386 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
388 * As of rev 4.0, no longer need the error check.
390 * -- Even if we could tell, we still want to return -1
391 * for **ANY** error (not just master abort).
393 * -- Only clear non-fatal errors (we don't want to bring
394 * LBA out of pci-fatal mode).
396 * Actually, there is still a race in which
397 * we could be clearing a fatal error. We will
398 * live with this during our initial bus walk
399 * until rev 4.0 (no driver activity during
400 * initial bus walk). The initial bus walk
401 * has race conditions concerning the use of
402 * smart mode as well.
405 #define LBA_MASTER_ABORT_ERROR 0xc
406 #define LBA_FATAL_ERROR 0x10
408 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
409 u32 error_status = 0; \
411 * Set clear enable (CE) bit. Unset by HW when new \
412 * errors are logged -- LBA HW ERS section 14.3.3). \
414 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
415 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
416 if ((error_status & 0x1f) != 0) { \
418 * Fail the config read request. \
421 if ((error_status & LBA_FATAL_ERROR) == 0) { \
423 * Clear error status (if fatal bit not set) by setting \
424 * clear error log bit (CL). \
426 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
431 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
432 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR)
434 #define LBA_CFG_ADDR_SETUP(d, addr) { \
435 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
438 * -- Potentially could skip this once DMA bug fixed. \
440 * Read address register to ensure that LBA is the bus master, \
441 * which implies that DMA traffic has stopped when DMA arb is off. \
443 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
447 #define LBA_CFG_RESTORE(d, base) { \
449 * Restore status control register (turn off clear enable). \
451 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
453 * Restore error config register (turn off smart mode). \
455 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
456 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
458 * Restore arb mask register (reenables DMA arbitration). \
460 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
467 lba_rd_cfg(struct lba_device
*d
, u32 tok
, u8 reg
, u32 size
)
471 u32 arb_mask
= 0; /* used by LBA_CFG_SETUP/RESTORE */
472 u32 error_config
= 0; /* used by LBA_CFG_SETUP/RESTORE */
473 u32 status_control
= 0; /* used by LBA_CFG_SETUP/RESTORE */
475 ASSERT((size
== sizeof(u8
)) ||
476 (size
== sizeof(u16
)) ||
477 (size
== sizeof(u32
)));
479 if ((size
!= sizeof(u8
)) &&
480 (size
!= sizeof(u16
)) &&
481 (size
!= sizeof(u32
))) {
485 LBA_CFG_SETUP(d
, tok
);
486 LBA_CFG_PROBE(d
, tok
);
487 LBA_CFG_MASTER_ABORT_CHECK(d
, d
->hba
.base_addr
, tok
, error
);
489 LBA_CFG_ADDR_SETUP(d
, tok
| reg
);
492 data
= (u32
) READ_REG8(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (reg
& 3));
495 data
= (u32
) READ_REG16(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (reg
& 2));
498 data
= READ_REG32(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
501 break; /* leave data as -1 */
504 LBA_CFG_RESTORE(d
, d
->hba
.base_addr
);
509 static int lba_cfg_read(struct pci_bus
*bus
, unsigned int devfn
, int pos
, int size
, u32
*data
)
511 struct lba_device
*d
= LBA_DEV(parisc_walk_tree(bus
->dev
));
512 u32 local_bus
= (bus
->parent
== NULL
) ? 0 : bus
->secondary
;
513 u32 tok
= LBA_CFG_TOK(local_bus
, devfn
);
515 /* FIXME: B2K/C3600 workaround is always use old method... */
516 /* if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) */ {
517 /* original - Generate config cycle on broken elroy
518 with risk we will miss PCI bus errors. */
519 *data
= lba_rd_cfg(d
, tok
, pos
, size
);
520 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__
, tok
, pos
, *data
);
521 return(*data
== ~0UL);
524 if (LBA_SKIP_PROBE(d
) && (!lba_device_present(bus
->secondary
, devfn
, d
)))
526 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__
, tok
, pos
);
527 /* either don't want to look or know device isn't present. */
533 ** Should only get here on fully working LBA rev.
534 ** This is how simple the code should have been.
536 LBA_CFG_TR4_ADDR_SETUP(d
, tok
| pos
);
538 case 1: *(u8
*) data
= READ_REG8(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
540 case 2: *(u16
*) data
= READ_REG16(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
542 case 4: *(u32
*) data
= READ_REG32(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
545 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__
, tok
, pos
, *data
);
546 return(*data
== ~0U);
551 lba_wr_cfg( struct lba_device
*d
, u32 tok
, u8 reg
, u32 data
, u32 size
)
555 u32 error_config
= 0;
556 u32 status_control
= 0;
558 ASSERT((size
== sizeof(u8
)) ||
559 (size
== sizeof(u16
)) ||
560 (size
== sizeof(u32
)));
562 if ((size
!= sizeof(u8
)) &&
563 (size
!= sizeof(u16
)) &&
564 (size
!= sizeof(u32
))) {
568 LBA_CFG_SETUP(d
, tok
);
569 LBA_CFG_ADDR_SETUP(d
, tok
| reg
);
572 WRITE_REG8((u8
) data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (reg
&3));
575 WRITE_REG16((u8
) data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+(reg
&2));
578 WRITE_REG32(data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
583 LBA_CFG_MASTER_ABORT_CHECK(d
, d
->hba
.base_addr
, tok
, error
);
584 LBA_CFG_RESTORE(d
, d
->hba
.base_addr
);
589 * LBA 4.0 config write code implements non-postable semantics
590 * by doing a read of CONFIG ADDR after the write.
593 static int lba_cfg_write(struct pci_bus
*bus
, unsigned int devfn
, int pos
, int size
, u32 data
)
595 struct lba_device
*d
= LBA_DEV(parisc_walk_tree(bus
->dev
));
596 u32 local_bus
= (bus
->parent
== NULL
) ? 0 : bus
->secondary
;
597 u32 tok
= LBA_CFG_TOK(local_bus
,devfn
);
599 ASSERT((tok
& 0xff) == 0);
602 if (!LBA_TR4PLUS(d
) && !LBA_SKIP_PROBE(d
)) {
603 /* Original Workaround */
604 lba_wr_cfg(d
, tok
, pos
, (u32
) data
, size
);
605 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__
, tok
, pos
,data
);
609 if (LBA_SKIP_PROBE(d
) && (!lba_device_present(bus
->secondary
, devfn
, d
))) {
610 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__
, tok
, pos
,data
);
611 return 1; /* New Workaround */
614 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__
, tok
, pos
, data
);
615 /* Basic Algorithm */
616 LBA_CFG_TR4_ADDR_SETUP(d
, tok
| pos
);
618 case 1: WRITE_REG8 (data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
620 case 2: WRITE_REG16(data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
622 case 4: WRITE_REG32(data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
625 lba_t32
= READ_REG32(d
->hba
.base_addr
+ LBA_PCI_CFG_ADDR
);
630 static struct pci_ops lba_cfg_ops
= {
631 .read
= lba_cfg_read
,
632 .write
= lba_cfg_write
,
639 DBG(MODULE_NAME
": lba_bios_init\n");
646 ** Determine if a device is already configured.
647 ** If so, reserve it resources.
649 ** Read PCI cfg command register and see if I/O or MMIO is enabled.
650 ** PAT has to enable the devices it's using.
652 ** Note: resources are fixed up before we try to claim them.
655 lba_claim_dev_resources(struct pci_dev
*dev
)
660 (void) pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
662 srch_flags
= (cmd
& PCI_COMMAND_IO
) ? IORESOURCE_IO
: 0;
663 if (cmd
& PCI_COMMAND_MEMORY
)
664 srch_flags
|= IORESOURCE_MEM
;
669 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
670 if (dev
->resource
[i
].flags
& srch_flags
) {
671 pci_claim_resource(dev
, i
);
672 DBG(" claimed %s %d [%lx,%lx]/%x\n",
674 dev
->resource
[i
].start
,
675 dev
->resource
[i
].end
,
676 (int) dev
->resource
[i
].flags
685 ** The algorithm is generic code.
686 ** But it needs to access local data structures to get the IRQ base.
687 ** Could make this a "pci_fixup_irq(bus, region)" but not sure
690 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
691 ** Resources aren't allocated until recursive buswalk below HBA is completed.
694 lba_fixup_bus(struct pci_bus
*bus
)
696 struct list_head
*ln
;
698 u16 fbb_enable
= PCI_STATUS_FAST_BACK
;
701 struct lba_device
*ldev
= LBA_DEV(parisc_walk_tree(bus
->dev
));
702 int lba_portbase
= HBA_PORT_BASE(ldev
->hba
.hba_num
);
704 DBG("lba_fixup_bus(0x%p) bus %d sysdata 0x%p\n",
705 bus
, bus
->secondary
, bus
->dev
->platform_data
);
708 ** Properly Setup MMIO resources for this bus.
709 ** pci_alloc_primary_bus() mangles this.
711 if (NULL
== bus
->self
) {
714 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
715 ldev
->hba
.io_space
.name
,
716 ldev
->hba
.io_space
.start
, ldev
->hba
.io_space
.end
,
717 (int) ldev
->hba
.io_space
.flags
);
718 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
719 ldev
->hba
.lmmio_space
.name
,
720 ldev
->hba
.lmmio_space
.start
, ldev
->hba
.lmmio_space
.end
,
721 (int) ldev
->hba
.lmmio_space
.flags
);
723 err
= request_resource(&ioport_resource
, &(ldev
->hba
.io_space
));
726 lba_dump_res(&ioport_resource
, 2);
728 err
= request_resource(&iomem_resource
, &(ldev
->hba
.lmmio_space
));
731 lba_dump_res(&iomem_resource
, 2);
734 bus
->resource
[0] = &(ldev
->hba
.io_space
);
735 bus
->resource
[1] = &(ldev
->hba
.lmmio_space
);
738 ** PCI-PCI Bridge resource munging.
739 ** This hack should go away in the near future.
740 ** It's based on the Alpha port.
745 for (i
= 0; i
< 4; i
++) {
747 &bus
->self
->resource
[PCI_BRIDGE_RESOURCES
+i
];
748 bus
->resource
[i
]->name
= bus
->name
;
751 bus
->resource
[0]->flags
|= pci_bridge_check_io(bus
->self
);
753 bus
->resource
[0]->flags
|= IORESOURCE_IO
;
755 bus
->resource
[1]->flags
|= IORESOURCE_MEM
;
756 bus
->resource
[2]->flags
= 0; /* Don't support prefetchable */
757 bus
->resource
[3]->flags
= 0; /* not used */
760 ** If the PPB is enabled (ie already configured) then
761 ** just read those values.
763 (void) pci_read_config_word(bus
->self
, PCI_COMMAND
, &cmd
);
764 if (cmd
& (PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
)) {
765 pci_read_bridge_bases(bus
);
768 ** For now, propagate HBA limits to the bus;
769 ** PCI will adjust them later.
771 bus
->resource
[0]->end
= ldev
->hba
.io_space
.end
;
772 bus
->resource
[1]->end
= ldev
->hba
.lmmio_space
.end
;
775 /* Turn off downstream PF memory address range by default */
776 bus
->resource
[2]->start
= 1024*1024;
777 bus
->resource
[2]->end
= bus
->resource
[2]->start
- 1;
781 list_for_each(ln
, &bus
->devices
) {
783 struct pci_dev
*dev
= pci_dev_b(ln
);
785 DBG("lba_fixup_bus() %s\n", dev
->name
);
787 /* Virtualize Device/Bridge Resources. */
788 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
789 struct resource
*res
= &dev
->resource
[i
];
791 /* If resource not allocated - skip it */
795 if (res
->flags
& IORESOURCE_IO
) {
796 DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ",
797 res
->start
, res
->end
);
798 res
->start
|= lba_portbase
;
799 res
->end
|= lba_portbase
;
800 DBG("[%lx/%lx]\n", res
->start
, res
->end
);
801 } else if (res
->flags
& IORESOURCE_MEM
) {
803 ** Convert PCI (IO_VIEW) addresses to
804 ** processor (PA_VIEW) addresses
806 DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ",
807 res
->start
, res
->end
);
808 res
->start
= PCI_HOST_ADDR(HBA_DATA(ldev
), res
->start
);
809 res
->end
= PCI_HOST_ADDR(HBA_DATA(ldev
), res
->end
);
810 DBG("[%lx/%lx]\n", res
->start
, res
->end
);
816 ** If one device does not support FBB transfers,
817 ** No one on the bus can be allowed to use them.
819 (void) pci_read_config_word(dev
, PCI_STATUS
, &status
);
820 fbb_enable
&= status
;
825 /* Claim resources for PDC's devices */
826 lba_claim_dev_resources(dev
);
831 ** P2PB's have no IRQs. ignore them.
833 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
)
836 /* Adjust INTERRUPT_LINE for this dev */
837 iosapic_fixup_irq(ldev
->iosapic_obj
, dev
);
841 /* FIXME/REVISIT - finish figuring out to set FBB on both
842 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
843 ** Can't fixup here anyway....garr...
849 (void) pci_read_config_byte(bus
->self
, PCI_BRIDGE_CONTROL
, &control
);
850 (void) pci_write_config_byte(bus
->self
, PCI_BRIDGE_CONTROL
, control
| PCI_STATUS_FAST_BACK
);
855 fbb_enable
= PCI_COMMAND_FAST_BACK
;
858 /* Lastly enable FBB/PERR/SERR on all devices too */
859 list_for_each(ln
, &bus
->devices
) {
860 (void) pci_read_config_word(dev
, PCI_COMMAND
, &status
);
861 status
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
| fbb_enable
;
862 (void) pci_write_config_word(dev
, PCI_COMMAND
, status
);
868 struct pci_bios_ops lba_bios_ops
= {
869 .init
= lba_bios_init
,
870 .fixup_bus
= lba_fixup_bus
,
876 /*******************************************************
878 ** LBA Sprockets "I/O Port" Space Accessor Functions
880 ** This set of accessor functions is intended for use with
881 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
883 ** Many PCI devices don't require use of I/O port space (eg Tulip,
884 ** NCR720) since they export the same registers to both MMIO and
885 ** I/O port space. In general I/O port space is slower than
886 ** MMIO since drivers are designed so PIO writes can be posted.
888 ********************************************************/
890 #define LBA_PORT_IN(size, mask) \
891 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
894 t = READ_REG##size(LBA_ASTRO_PORT_BASE + addr); \
895 DBG_PORT(" 0x%x\n", t); \
906 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
908 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
909 ** guarantee non-postable completion semantics - not avoid X4107.
910 ** The READ_U32 only guarantees the write data gets to elroy but
911 ** out to the PCI bus. We can't read stuff from I/O port space
912 ** since we don't know what has side-effects. Attempting to read
913 ** from configuration space would be suicidal given the number of
914 ** bugs in that elroy functionality.
917 ** DMA read results can improperly pass PIO writes (X4107). The
918 ** result of this bug is that if a processor modifies a location in
919 ** memory after having issued PIO writes, the PIO writes are not
920 ** guaranteed to be completed before a PCI device is allowed to see
921 ** the modified data in a DMA read.
923 ** Note that IKE bug X3719 in TR1 IKEs will result in the same
927 ** The workaround for this bug is to always follow a PIO write with
928 ** a PIO read to the same bus before starting DMA on that PCI bus.
931 #define LBA_PORT_OUT(size, mask) \
932 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
935 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \
936 WRITE_REG##size(val, LBA_ASTRO_PORT_BASE + addr); \
937 if (LBA_DEV(d)->hw_rev < 3) \
938 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
946 static struct pci_port_ops lba_astro_port_ops
= {
947 .inb
= lba_astro_in8
,
948 .inw
= lba_astro_in16
,
949 .inl
= lba_astro_in32
,
950 .outb
= lba_astro_out8
,
951 .outw
= lba_astro_out16
,
952 .outl
= lba_astro_out32
957 #define PIOP_TO_GMMIO(lba, addr) \
958 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
960 /*******************************************************
962 ** LBA PAT "I/O Port" Space Accessor Functions
964 ** This set of accessor functions is intended for use with
965 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
967 ** This uses the PIOP space located in the first 64MB of GMMIO.
968 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
969 ** bits 1:0 stay the same. bits 15:2 become 25:12.
970 ** Then add the base and we can generate an I/O Port cycle.
971 ********************************************************/
973 #define LBA_PORT_IN(size, mask) \
974 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
977 ASSERT(bus != NULL); \
978 DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \
979 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
980 DBG_PORT(" 0x%x\n", t); \
990 #define LBA_PORT_OUT(size, mask) \
991 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
993 void *where = (void *) PIOP_TO_GMMIO(LBA_DEV(l), addr); \
994 ASSERT(bus != NULL); \
995 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \
996 WRITE_REG##size(val, where); \
997 /* flush the I/O down to the elroy at least */ \
998 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
1006 static struct pci_port_ops lba_pat_port_ops
= {
1008 .inw
= lba_pat_in16
,
1009 .inl
= lba_pat_in32
,
1010 .outb
= lba_pat_out8
,
1011 .outw
= lba_pat_out16
,
1012 .outl
= lba_pat_out32
1018 ** make range information from PDC available to PCI subsystem.
1019 ** We make the PDC call here in order to get the PCI bus range
1020 ** numbers. The rest will get forwarded in pcibios_fixup_bus().
1021 ** We don't have a struct pci_bus assigned to us yet.
1024 lba_pat_resources(struct parisc_device
*pa_dev
, struct lba_device
*lba_dev
)
1026 unsigned long bytecnt
;
1027 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell
; /* PA_VIEW */
1028 pdc_pat_cell_mod_maddr_block_t io_pdc_cell
; /* IO_VIEW */
1030 long status
; /* PDC return status */
1034 /* return cell module (IO view) */
1035 status
= pdc_pat_cell_module(&bytecnt
, pa_dev
->pcell_loc
, pa_dev
->mod_index
,
1036 PA_VIEW
, & pa_pdc_cell
);
1037 pa_count
= pa_pdc_cell
.mod
[1];
1039 status
|= pdc_pat_cell_module(&bytecnt
, pa_dev
->pcell_loc
, pa_dev
->mod_index
,
1040 IO_VIEW
, &io_pdc_cell
);
1041 io_count
= io_pdc_cell
.mod
[1];
1043 /* We've already done this once for device discovery...*/
1044 if (status
!= PDC_OK
) {
1045 panic("pdc_pat_cell_module() call failed for LBA!\n");
1048 if (PAT_GET_ENTITY(pa_pdc_cell
.mod_info
) != PAT_ENTITY_LBA
) {
1049 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1053 ** Inspect the resources PAT tells us about
1055 for (i
= 0; i
< pa_count
; i
++) {
1058 unsigned long start
;
1059 unsigned long end
; /* aka finish */
1063 p
= (void *) &(pa_pdc_cell
.mod
[2+i
*3]);
1064 io
= (void *) &(io_pdc_cell
.mod
[2+i
*3]);
1066 /* Convert the PAT range data to PCI "struct resource" */
1067 switch(p
->type
& 0xff) {
1069 lba_dev
->hba
.bus_num
.start
= p
->start
;
1070 lba_dev
->hba
.bus_num
.end
= p
->end
;
1073 /* used to fix up pre-initialized MEM BARs */
1074 lba_dev
->hba
.lmmio_space_offset
= p
->start
- io
->start
;
1076 r
= &(lba_dev
->hba
.lmmio_space
);
1077 r
->name
= "LBA LMMIO";
1078 r
->start
= p
->start
;
1080 r
->flags
= IORESOURCE_MEM
;
1081 r
->parent
= r
->sibling
= r
->child
= NULL
;
1084 printk(KERN_WARNING MODULE_NAME
1085 " range[%d] : ignoring GMMIO (0x%lx)\n",
1087 lba_dev
->gmmio_base
= p
->start
;
1090 printk(KERN_WARNING MODULE_NAME
1091 " range[%d] : ignoring NPIOP (0x%lx)\n",
1096 ** Postable I/O port space is per PCI host adapter.
1099 /* save base of 64MB PIOP region */
1100 lba_dev
->iop_base
= p
->start
;
1102 r
= &(lba_dev
->hba
.io_space
);
1103 r
->name
= "LBA I/O Port";
1104 r
->start
= HBA_PORT_BASE(lba_dev
->hba
.hba_num
);
1105 r
->end
= r
->start
+ HBA_PORT_SPACE_SIZE
- 1;
1106 r
->flags
= IORESOURCE_IO
;
1107 r
->parent
= r
->sibling
= r
->child
= NULL
;
1110 printk(KERN_WARNING MODULE_NAME
1111 " range[%d] : unknown pat range type (0x%lx)\n",
1117 #endif /* __LP64__ */
1121 lba_legacy_resources(struct parisc_device
*pa_dev
, struct lba_device
*lba_dev
)
1124 unsigned long rsize
;
1129 ** Sign extend all BAR values on "legacy" platforms.
1130 ** "Sprockets" PDC (Forte/Allegro) initializes everything
1131 ** for "legacy" 32-bit OS (HPUX 10.20).
1132 ** Upper 32-bits of 64-bit BAR will be zero too.
1134 lba_dev
->hba
.lmmio_space_offset
= 0xffffffff00000000UL
;
1136 lba_dev
->hba
.lmmio_space_offset
= 0UL;
1140 ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1141 ** represents bus->secondary and the second byte represents
1142 ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1143 ** PCI bus walk *should* end up with the same result.
1144 ** FIXME: But we don't have sanity checks in PCI or LBA.
1146 lba_num
= READ_REG32(pa_dev
->hpa
+ LBA_FW_SCRATCH
);
1147 r
= &(lba_dev
->hba
.bus_num
);
1148 r
->name
= "LBA PCI Busses";
1149 r
->start
= lba_num
& 0xff;
1150 r
->end
= (lba_num
>>8) & 0xff;
1152 /* Set up local PCI Bus resources - we don't really need
1153 ** them for Legacy boxes but it's nice to see in /proc.
1155 r
= &(lba_dev
->hba
.lmmio_space
);
1156 r
->name
= "LBA PCI LMMIO";
1157 r
->flags
= IORESOURCE_MEM
;
1158 /* Ignore "Range Enable" bit in the BASE register */
1159 r
->start
= PCI_HOST_ADDR(HBA_DATA(lba_dev
),
1160 ((long) READ_REG32(pa_dev
->hpa
+ LBA_LMMIO_BASE
)) & ~1UL);
1161 rsize
= ~READ_REG32(pa_dev
->hpa
+ LBA_LMMIO_MASK
) + 1;
1164 ** Each rope only gets part of the distributed range.
1165 ** Adjust "window" for this rope
1167 rsize
/= ROPES_PER_SBA
;
1168 r
->start
+= rsize
* LBA_NUM(pa_dev
->hpa
);
1169 r
->end
= r
->start
+ rsize
- 1 ;
1172 ** XXX FIXME - ignore LBA_ELMMIO_BASE for now
1173 ** "Directed" ranges are used when the "distributed range" isn't
1174 ** sufficient for all devices below a given LBA. Typically devices
1175 ** like graphics cards or X25 may need a directed range when the
1176 ** bus has multiple slots (ie multiple devices) or the device
1177 ** needs more than the typical 4 or 8MB a distributed range offers.
1179 ** The main reason for ignoring it now frigging complications.
1180 ** Directed ranges may overlap (and have precedence) over
1181 ** distributed ranges. Ie a distributed range assigned to a unused
1182 ** rope may be used by a directed range on a different rope.
1183 ** Support for graphics devices may require fixing this
1184 ** since they may be assigned a directed range which overlaps
1185 ** an existing (but unused portion of) distributed range.
1187 r
= &(lba_dev
->hba
.elmmio_space
);
1188 r
->name
= "extra LBA PCI LMMIO";
1189 r
->flags
= IORESOURCE_MEM
;
1190 r
->start
= READ_REG32(pa_dev
->hpa
+ LBA_ELMMIO_BASE
);
1193 /* check Range Enable bit */
1195 /* First baby step to getting Direct Ranges listed in /proc.
1196 ** AFAIK, only Sprockets PDC will setup a directed Range.
1201 r
->end
+= ~READ_REG32(pa_dev
->hpa
+ LBA_ELMMIO_MASK
);
1202 printk(KERN_DEBUG
"WARNING: Ignoring enabled ELMMIO BASE 0x%0lx SIZE 0x%lx\n",
1208 r
= &(lba_dev
->hba
.io_space
);
1209 r
->name
= "LBA PCI I/O Ports";
1210 r
->flags
= IORESOURCE_IO
;
1211 r
->start
= READ_REG32(pa_dev
->hpa
+ LBA_IOS_BASE
) & ~1L;
1212 r
->end
= r
->start
+ (READ_REG32(pa_dev
->hpa
+ LBA_IOS_MASK
) ^ (HBA_PORT_SPACE_SIZE
- 1));
1214 /* Virtualize the I/O Port space ranges */
1215 lba_num
= HBA_PORT_BASE(lba_dev
->hba
.hba_num
);
1216 r
->start
|= lba_num
;
1221 /**************************************************************************
1223 ** LBA initialization code (HW and SW)
1225 ** o identify LBA chip itself
1226 ** o initialize LBA chip modes (HardFail)
1227 ** o FIXME: initialize DMA hints for reasonable defaults
1228 ** o enable configuration functions
1229 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1231 **************************************************************************/
1234 lba_hw_init(struct lba_device
*d
)
1237 u32 bus_reset
; /* PDC_PAT_BUG */
1240 printk(KERN_DEBUG
"LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n",
1242 READ_REG64(d
->hba
.base_addr
+ LBA_STAT_CTL
),
1243 READ_REG64(d
->hba
.base_addr
+ LBA_ERROR_CONFIG
),
1244 READ_REG64(d
->hba
.base_addr
+ LBA_ERROR_STATUS
),
1245 READ_REG64(d
->hba
.base_addr
+ LBA_DMA_CTL
) );
1246 printk(KERN_DEBUG
" ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n",
1247 READ_REG64(d
->hba
.base_addr
+ LBA_ARB_MASK
),
1248 READ_REG64(d
->hba
.base_addr
+ LBA_ARB_PRI
),
1249 READ_REG64(d
->hba
.base_addr
+ LBA_ARB_MODE
),
1250 READ_REG64(d
->hba
.base_addr
+ LBA_ARB_MTLT
) );
1251 printk(KERN_DEBUG
" HINT cfg 0x%Lx\n",
1252 READ_REG64(d
->hba
.base_addr
+ LBA_HINT_CFG
));
1253 printk(KERN_DEBUG
" HINT reg ");
1255 for (i
=LBA_HINT_BASE
; i
< (14*8 + LBA_HINT_BASE
); i
+=8)
1256 printk(" %Lx", READ_REG64(d
->hba
.base_addr
+ i
));
1259 #endif /* DEBUG_LBA_PAT */
1262 #warning FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1265 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */
1266 bus_reset
= READ_REG32(d
->hba
.base_addr
+ LBA_STAT_CTL
+ 4) & 1;
1268 printk(KERN_DEBUG
"NOTICE: PCI bus reset still asserted! (clearing)\n");
1271 stat
= READ_REG32(d
->hba
.base_addr
+ LBA_ERROR_CONFIG
);
1272 if (stat
& LBA_SMART_MODE
) {
1273 printk(KERN_DEBUG
"NOTICE: LBA in SMART mode! (cleared)\n");
1274 stat
&= ~LBA_SMART_MODE
;
1275 WRITE_REG32(stat
, d
->hba
.base_addr
+ LBA_ERROR_CONFIG
);
1278 /* Set HF mode as the default (vs. -1 mode). */
1279 stat
= READ_REG32(d
->hba
.base_addr
+ LBA_STAT_CTL
);
1280 WRITE_REG32(stat
| HF_ENABLE
, d
->hba
.base_addr
+ LBA_STAT_CTL
);
1283 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1284 ** if it's not already set. If we just cleared the PCI Bus Reset
1285 ** signal, wait a bit for the PCI devices to recover and setup.
1288 mdelay(pci_post_reset_delay
);
1290 if (0 == READ_REG32(d
->hba
.base_addr
+ LBA_ARB_MASK
)) {
1292 ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1293 ** B2000/C3600/J6000 also have this problem?
1295 ** Elroys with hot pluggable slots don't get configured
1296 ** correctly if the slot is empty. ARB_MASK is set to 0
1297 ** and we can't master transactions on the bus if it's
1298 ** not at least one. 0x3 enables elroy and first slot.
1300 printk(KERN_DEBUG
"NOTICE: Enabling PCI Arbitration\n");
1301 WRITE_REG32(0x3, d
->hba
.base_addr
+ LBA_ARB_MASK
);
1305 ** FIXME: Hint registers are programmed with default hint
1306 ** values by firmware. Hints should be sane even if we
1307 ** can't reprogram them the way drivers want.
1315 lba_common_init(struct lba_device
*lba_dev
)
1317 pci_bios
= &lba_bios_ops
;
1318 pcibios_register_hba(HBA_DATA(lba_dev
));
1319 lba_dev
->lba_lock
= SPIN_LOCK_UNLOCKED
;
1322 ** Set flags which depend on hw_rev
1324 if (!LBA_TR4PLUS(lba_dev
)) {
1325 lba_dev
->flags
|= LBA_FLAG_NO_DMA_DURING_CFG
;
1332 ** Determine if lba should claim this chip (return 0) or not (return 1).
1333 ** If so, initialize the chip and tell other partners in crime they
1337 lba_driver_callback(struct parisc_device
*dev
)
1339 struct lba_device
*lba_dev
;
1340 struct pci_bus
*lba_bus
;
1345 /* Read HW Rev First */
1346 func_class
= READ_REG32(dev
->hpa
+ LBA_FCLASS
);
1349 switch (func_class
) {
1350 case 0: version
= "TR1.0"; break;
1351 case 1: version
= "TR2.0"; break;
1352 case 2: version
= "TR2.1"; break;
1353 case 3: version
= "TR2.2"; break;
1354 case 4: version
= "TR3.0"; break;
1355 case 5: version
= "TR4.0"; break;
1356 default: version
= "TR4+";
1359 printk(KERN_INFO
"%s version %s (0x%x) found at 0x%lx\n",
1360 MODULE_NAME
, version
, func_class
& 0xf, dev
->hpa
);
1361 snprintf(dev
->dev
.name
, sizeof(dev
->dev
.name
), "%s version %s",
1362 MODULE_NAME
, version
);
1364 /* Just in case we find some prototypes... */
1365 if (func_class
< 2) {
1366 printk(KERN_WARNING
"Can't support LBA older than TR2.1 "
1367 "- continuing under adversity.\n");
1371 ** Tell I/O SAPIC driver we have a IRQ handler/region.
1373 tmp_obj
= iosapic_register(dev
->hpa
+ LBA_IOSAPIC_BASE
);
1375 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1376 ** have an IRT entry will get NULL back from iosapic code.
1379 lba_dev
= kmalloc(sizeof(struct lba_device
), GFP_KERNEL
);
1380 if (NULL
== lba_dev
)
1382 printk(KERN_ERR
"lba_init_chip - couldn't alloc lba_device\n");
1386 memset(lba_dev
, 0, sizeof(struct lba_device
));
1389 /* ---------- First : initialize data we already have --------- */
1392 ** Need hw_rev to adjust configuration space behavior.
1393 ** LBA_TR4PLUS macro uses hw_rev field.
1395 lba_dev
->hw_rev
= func_class
;
1397 lba_dev
->hba
.base_addr
= dev
->hpa
; /* faster access */
1398 lba_dev
->hba
.dev
= dev
;
1399 lba_dev
->iosapic_obj
= tmp_obj
; /* save interrupt handle */
1400 lba_dev
->hba
.iommu
= sba_get_iommu(dev
); /* get iommu data */
1402 /* ------------ Second : initialize common stuff ---------- */
1403 lba_common_init(lba_dev
);
1405 if (lba_hw_init(lba_dev
))
1408 /* ---------- Third : setup I/O Port and MMIO resources --------- */
1412 /* PDC PAT firmware uses PIOP region of GMMIO space. */
1413 pci_port
= &lba_pat_port_ops
;
1415 /* Go ask PDC PAT what resources this LBA has */
1416 lba_pat_resources(dev
, lba_dev
);
1420 /* Sprockets PDC uses NPIOP region */
1421 pci_port
= &lba_astro_port_ops
;
1423 /* Poke the chip a bit for /proc output */
1424 lba_legacy_resources(dev
, lba_dev
);
1428 ** Tell PCI support another PCI bus was found.
1429 ** Walks PCI bus for us too.
1431 dev
->dev
.platform_data
= lba_dev
;
1432 lba_bus
= lba_dev
->hba
.hba_bus
=
1433 pci_scan_bus_parented(&dev
->dev
, lba_dev
->hba
.bus_num
.start
,
1434 &lba_cfg_ops
, NULL
);
1438 /* assign resources to un-initialized devices */
1439 DBG_PAT("LBA pci_bus_assign_resources()\n");
1440 pci_bus_assign_resources(lba_bus
);
1442 #ifdef DEBUG_LBA_PAT
1443 DBG_PAT("\nLBA PIOP resource tree\n");
1444 lba_dump_res(&lba_dev
->hba
.io_space
, 2);
1445 DBG_PAT("\nLBA LMMIO resource tree\n");
1446 lba_dump_res(&lba_dev
->hba
.lmmio_space
, 2);
1452 ** Once PCI register ops has walked the bus, access to config
1453 ** space is restricted. Avoids master aborts on config cycles.
1454 ** Early LBA revs go fatal on *any* master abort.
1456 if (!LBA_TR4PLUS(lba_dev
)) {
1457 lba_dev
->flags
|= LBA_FLAG_SKIP_PROBE
;
1460 /* Whew! Finally done! Tell services we got this one covered. */
1464 static struct parisc_device_id lba_tbl
[] = {
1465 { HPHW_BRIDGE
, HVERSION_REV_ANY_ID
, 0x782, 0xa },
1469 static struct parisc_driver lba_driver
= {
1470 .name
= MODULE_NAME
,
1471 .id_table
= lba_tbl
,
1472 .probe
= lba_driver_callback
,
1476 ** One time initialization to let the world know the LBA was found.
1477 ** Must be called exactly once before pci_init().
1479 void __init
lba_init(void)
1481 register_parisc_driver(&lba_driver
);
1485 ** Initialize the IBASE/IMASK registers for LBA (Elroy).
1486 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1487 ** sba_iommu is responsible for locking (none needed at init time).
1490 lba_set_iregs(struct parisc_device
*lba
, u32 ibase
, u32 imask
)
1492 unsigned long base_addr
= lba
->hpa
;
1494 imask
<<= 2; /* adjust for hints - 2 more bits */
1496 ASSERT((ibase
& 0x003fffff) == 0);
1497 ASSERT((imask
& 0x003fffff) == 0);
1499 DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__
, ibase
, imask
);
1500 WRITE_REG32( imask
, base_addr
+ LBA_IMASK
);
1501 WRITE_REG32( ibase
, base_addr
+ LBA_IBASE
);