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[linux-2.6/linux-mips.git] / drivers / net / tc35815.c
bloba86c6376f6d52f9de6f65a2f3263fd49ec7c488c
1 /* tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: MontaVista Software, Inc.
5 * ahennessy@mvista.com
6 *
7 * Based on skelton.c by Donald Becker.
8 * Copyright (C) 2000-2001 Toshiba Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 static const char *version =
32 "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/fcntl.h>
38 #include <linux/interrupt.h>
39 #include <linux/ioport.h>
40 #include <linux/in.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/errno.h>
44 #include <linux/init.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/delay.h>
49 #include <linux/pci.h>
50 #include <linux/proc_fs.h>
51
52 #include <asm/system.h>
53 #include <asm/bitops.h>
54 #include <asm/io.h>
55 #include <asm/dma.h>
56 #include <asm/byteorder.h>
57
58 /*
59 * The name of the card. Is used for messages and in the requests for
60 * io regions, irqs and dma channels
61 */
62 static const char* cardname = "TC35815CF";
63 #define TC35815_PROC_ENTRY "net/tc35815"
64
65 #define TC35815_MODULE_NAME "TC35815CF"
66 #define TX_TIMEOUT (4*HZ)
67
68 /* First, a few definitions that the brave might change. */
69
70 /* use 0 for production, 1 for verification, >2 for debug */
71 #ifndef TC35815_DEBUG
72 #define TC35815_DEBUG 1
73 #endif
74 static unsigned int tc35815_debug = TC35815_DEBUG;
75
76 #define GATHER_TXINT /* On-Demand Tx Interrupt */
77
78 #define vtonocache(p) KSEG1ADDR(virt_to_phys(p))
79
80 /*
81 * Registers
82 */
83 struct tc35815_regs {
84 volatile __u32 DMA_Ctl; /* 0x00 */
85 volatile __u32 TxFrmPtr;
86 volatile __u32 TxThrsh;
87 volatile __u32 TxPollCtr;
88 volatile __u32 BLFrmPtr;
89 volatile __u32 RxFragSize;
90 volatile __u32 Int_En;
91 volatile __u32 FDA_Bas;
92 volatile __u32 FDA_Lim; /* 0x20 */
93 volatile __u32 Int_Src;
94 volatile __u32 unused0[2];
95 volatile __u32 PauseCnt;
96 volatile __u32 RemPauCnt;
97 volatile __u32 TxCtlFrmStat;
98 volatile __u32 unused1;
99 volatile __u32 MAC_Ctl; /* 0x40 */
100 volatile __u32 CAM_Ctl;
101 volatile __u32 Tx_Ctl;
102 volatile __u32 Tx_Stat;
103 volatile __u32 Rx_Ctl;
104 volatile __u32 Rx_Stat;
105 volatile __u32 MD_Data;
106 volatile __u32 MD_CA;
107 volatile __u32 CAM_Adr; /* 0x60 */
108 volatile __u32 CAM_Data;
109 volatile __u32 CAM_Ena;
110 volatile __u32 PROM_Ctl;
111 volatile __u32 PROM_Data;
112 volatile __u32 Algn_Cnt;
113 volatile __u32 CRC_Cnt;
114 volatile __u32 Miss_Cnt;
115 };
116
117 /*
118 * Bit assignments
119 */
120 /* DMA_Ctl bit asign ------------------------------------------------------- */
121 #define DMA_IntMask 0x00040000 /* 1:Interupt mask */
122 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
123 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
124 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
125 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
126 #define DMA_TestMode 0x00002000 /* 1:Test Mode */
127 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
128 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
129
130 /* RxFragSize bit asign ---------------------------------------------------- */
131 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
132 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
133
134 /* MAC_Ctl bit asign ------------------------------------------------------- */
135 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
136 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
137 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
138 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
139 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
140 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
141 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
142 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
143 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
144 #define MAC_Reset 0x00000004 /* 1:Software Reset */
145 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
146 #define MAC_HaltReq 0x00000001 /* 1:Halt request */
147
148 /* PROM_Ctl bit asign ------------------------------------------------------ */
149 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
150 #define PROM_Read 0x00004000 /*10:Read operation */
151 #define PROM_Write 0x00002000 /*01:Write operation */
152 #define PROM_Erase 0x00006000 /*11:Erase operation */
153 /*00:Enable or Disable Writting, */
154 /* as specified in PROM_Addr. */
155 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
156 /*00xxxx: disable */
157
158 /* CAM_Ctl bit asign ------------------------------------------------------- */
159 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
160 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
161 /* accept other */
162 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
163 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
164 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
165
166 /* CAM_Ena bit asign ------------------------------------------------------- */
167 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
168 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
169 #define CAM_Ena_Bit(index) (1<<(index))
170 #define CAM_ENTRY_DESTINATION 0
171 #define CAM_ENTRY_SOURCE 1
172 #define CAM_ENTRY_MACCTL 20
173
174 /* Tx_Ctl bit asign -------------------------------------------------------- */
175 #define Tx_En 0x00000001 /* 1:Transmit enable */
176 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
177 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
178 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
179 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
180 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
181 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
182 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
183 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
184 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
185 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
186 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
187
188 /* Tx_Stat bit asign ------------------------------------------------------- */
189 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
190 #define Tx_ExColl 0x00000010 /* Excessive Collision */
191 #define Tx_TXDefer 0x00000020 /* Transmit Defered */
192 #define Tx_Paused 0x00000040 /* Transmit Paused */
193 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
194 #define Tx_Under 0x00000100 /* Underrun */
195 #define Tx_Defer 0x00000200 /* Deferral */
196 #define Tx_NCarr 0x00000400 /* No Carrier */
197 #define Tx_10Stat 0x00000800 /* 10Mbps Status */
198 #define Tx_LateColl 0x00001000 /* Late Collision */
199 #define Tx_TxPar 0x00002000 /* Tx Parity Error */
200 #define Tx_Comp 0x00004000 /* Completion */
201 #define Tx_Halted 0x00008000 /* Tx Halted */
202 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
203
204 /* Rx_Ctl bit asign -------------------------------------------------------- */
205 #define Rx_EnGood 0x00004000 /* 1:Enable Good */
206 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
207 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
208 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
209 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
210 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
211 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
212 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
213 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
214 #define Rx_LongEn 0x00000004 /* 1:Long Enable */
215 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
216 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
217
218 /* Rx_Stat bit asign ------------------------------------------------------- */
219 #define Rx_Halted 0x00008000 /* Rx Halted */
220 #define Rx_Good 0x00004000 /* Rx Good */
221 #define Rx_RxPar 0x00002000 /* Rx Parity Error */
222 /* 0x00001000 not use */
223 #define Rx_LongErr 0x00000800 /* Rx Long Error */
224 #define Rx_Over 0x00000400 /* Rx Overflow */
225 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
226 #define Rx_Align 0x00000100 /* Rx Alignment Error */
227 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
228 #define Rx_IntRx 0x00000040 /* Rx Interrupt */
229 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
230
231 #define Rx_Stat_Mask 0x0000EFC0 /* Rx All Status Mask */
232
233 /* Int_En bit asign -------------------------------------------------------- */
234 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
235 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Control Complete Enable */
236 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
237 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
238 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
239 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
240 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
241 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
242 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
243 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
244 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
245 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
246 /* Exhausted Enable */
247
248 /* Int_Src bit asign ------------------------------------------------------- */
249 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
250 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
251 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
252 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
253 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
254 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
255 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
256 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
257 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
258 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
259 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
260 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
261 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
262 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
263 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
264
265 /* MD_CA bit asign --------------------------------------------------------- */
266 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
267 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
268 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
269
270
271 /* MII register offsets */
272 #define MII_CONTROL 0x0000
273 #define MII_STATUS 0x0001
274 #define MII_PHY_ID0 0x0002
275 #define MII_PHY_ID1 0x0003
276 #define MII_ANAR 0x0004
277 #define MII_ANLPAR 0x0005
278 #define MII_ANER 0x0006
279 /* MII Control register bit definitions. */
280 #define MIICNTL_FDX 0x0100
281 #define MIICNTL_RST_AUTO 0x0200
282 #define MIICNTL_ISOLATE 0x0400
283 #define MIICNTL_PWRDWN 0x0800
284 #define MIICNTL_AUTO 0x1000
285 #define MIICNTL_SPEED 0x2000
286 #define MIICNTL_LPBK 0x4000
287 #define MIICNTL_RESET 0x8000
288 /* MII Status register bit significance. */
289 #define MIISTAT_EXT 0x0001
290 #define MIISTAT_JAB 0x0002
291 #define MIISTAT_LINK 0x0004
292 #define MIISTAT_CAN_AUTO 0x0008
293 #define MIISTAT_FAULT 0x0010
294 #define MIISTAT_AUTO_DONE 0x0020
295 #define MIISTAT_CAN_T 0x0800
296 #define MIISTAT_CAN_T_FDX 0x1000
297 #define MIISTAT_CAN_TX 0x2000
298 #define MIISTAT_CAN_TX_FDX 0x4000
299 #define MIISTAT_CAN_T4 0x8000
300 /* MII Auto-Negotiation Expansion/RemoteEnd Register Bits */
301 #define MII_AN_TX_FDX 0x0100
302 #define MII_AN_TX_HDX 0x0080
303 #define MII_AN_10_FDX 0x0040
304 #define MII_AN_10_HDX 0x0020
305
306
307 /*
308 * Descriptors
309 */
310
311 /* Frame descripter */
312 struct FDesc {
313 volatile __u32 FDNext;
314 volatile __u32 FDSystem;
315 volatile __u32 FDStat;
316 volatile __u32 FDCtl;
317 };
318
319 /* Buffer descripter */
320 struct BDesc {
321 volatile __u32 BuffData;
322 volatile __u32 BDCtl;
323 };
324
325 #define FD_ALIGN 16
326
327 /* Frame Descripter bit asign ---------------------------------------------- */
328 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
329 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
330 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
331 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
332 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
333 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
334 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
335 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
336 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
337 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
338 #define FD_BDCnt_SHIFT 16
339
340 /* Buffer Descripter bit asign --------------------------------------------- */
341 #define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
342 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
343 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
344 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
345 #define BD_RxBDID_SHIFT 16
346 #define BD_RxBDSeqN_SHIFT 24
347
348
349 /* Some useful constants. */
350 #undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
351
352 #ifdef NO_CHECK_CARRIER
353 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
354 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
355 Tx_En) /* maybe 0x7d01 */
356 #else
357 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
358 Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
359 Tx_En) /* maybe 0x7f01 */
360 #endif
361 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
362 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
363
364 #define INT_EN_CMD (Int_NRAbtEn | \
365 Int_DParDEn | Int_DParErrEn | \
366 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
367 Int_STargAbtEn | \
368 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
369
370 /* Tuning parameters */
371 #define DMA_BURST_SIZE 32
372 #define TX_THRESHOLD 1024
373
374 #define FD_PAGE_NUM 2
375 #define FD_PAGE_ORDER 1
376 /* 16 + RX_BUF_PAGES * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*2 */
377 #define RX_BUF_PAGES 8 /* >= 2 */
378 #define RX_FD_NUM 250 /* >= 32 */
379 #define TX_FD_NUM 128
380
381 struct TxFD {
382 struct FDesc fd;
383 struct BDesc bd;
384 struct BDesc unused;
385 };
386
387 struct RxFD {
388 struct FDesc fd;
389 struct BDesc bd[0]; /* variable length */
390 };
391
392 struct FrFD {
393 struct FDesc fd;
394 struct BDesc bd[RX_BUF_PAGES];
395 };
396
397
398 extern unsigned long tc_readl(volatile __u32 *addr);
399 extern void tc_writel(unsigned long data, volatile __u32 *addr);
400
401 dma_addr_t priv_dma_handle;
402
403 /* Information that need to be kept for each board. */
404 struct tc35815_local {
405 struct net_device *next_module;
406
407 /* statistics */
408 struct net_device_stats stats;
409 struct {
410 int max_tx_qlen;
411 int tx_ints;
412 int rx_ints;
413 } lstats;
414
415 int tbusy;
416 int option;
417 #define TC35815_OPT_AUTO 0x00
418 #define TC35815_OPT_10M 0x01
419 #define TC35815_OPT_100M 0x02
420 #define TC35815_OPT_FULLDUP 0x04
421 int linkspeed; /* 10 or 100 */
422 int fullduplex;
423
424 /*
425 * Transmitting: Batch Mode.
426 * 1 BD in 1 TxFD.
427 * Receiving: Packing Mode.
428 * 1 circular FD for Free Buffer List.
429 * RX_BUG_PAGES BD in Free Buffer FD.
430 * One Free Buffer BD has PAGE_SIZE data buffer.
431 */
432 struct pci_dev *pdev;
433 dma_addr_t fd_buf_dma_handle;
434 void * fd_buf; /* for TxFD, TxFD, FrFD */
435 struct TxFD *tfd_base;
436 int tfd_start;
437 int tfd_end;
438 struct RxFD *rfd_base;
439 struct RxFD *rfd_limit;
440 struct RxFD *rfd_cur;
441 struct FrFD *fbl_ptr;
442 unsigned char fbl_curid;
443 dma_addr_t data_buf_dma_handle[RX_BUF_PAGES];
444 void * data_buf[RX_BUF_PAGES]; /* packing */
445 };
446
447 /* Index to functions, as function prototypes. */
448
449 static int __init tc35815_probe1(struct pci_dev *pdev, unsigned int base_addr, unsigned int irq);
450
451 static int tc35815_open(struct net_device *dev);
452 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
453 static void tc35815_tx_timeout(struct net_device *dev);
454 static irqreturn_t tc35815_interrupt(int irq, void *dev_id, struct pt_regs *regs);
455 static void tc35815_rx(struct net_device *dev);
456 static void tc35815_txdone(struct net_device *dev);
457 static int tc35815_close(struct net_device *dev);
458 static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
459 static void tc35815_set_multicast_list(struct net_device *dev);
460
461 static void tc35815_chip_reset(struct net_device *dev);
462 static void tc35815_chip_init(struct net_device *dev);
463 static void tc35815_phy_chip_init(struct net_device *dev);
464 static int tc35815_proc_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data);
465
466 /* A list of all installed tc35815 devices. */
467 static struct net_device *root_tc35815_dev = NULL;
468
469 /*
470 * PCI device identifiers for "new style" Linux PCI Device Drivers
471 */
472 static struct pci_device_id tc35815_pci_tbl[] __devinitdata = {
473 { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
474 { 0, }
475 };
476
477 MODULE_DEVICE_TABLE (pci, tc35815_pci_tbl);
478
479 int
480 tc35815_probe(struct pci_dev *pdev,
481 const struct pci_device_id *ent)
482 {
483 static int called = 0;
484 int err = 0;
485 int ret;
486
487 if (called)
488 return -ENODEV;
489 called++;
490
491 if (pdev) {
492 unsigned int pci_memaddr;
493 unsigned int pci_irq_line;
494
495 printk(KERN_INFO "tc35815_probe: found device %#08x.%#08x\n", ent->vendor, ent->device);
496
497 pci_memaddr = pci_resource_start (pdev, 1);
498
499 printk(KERN_INFO " pci_memaddr=%#08lx resource_flags=%#08lx\n", pci_memaddr, pci_resource_flags (pdev, 0));
500
501 if (!pci_memaddr) {
502 printk(KERN_WARNING "no PCI MEM resources, aborting\n");
503 return -ENODEV;
504 }
505 pci_irq_line = pdev->irq;
506 /* irq disabled. */
507 if (pci_irq_line == 0) {
508 printk(KERN_WARNING "no PCI irq, aborting\n");
509 return -ENODEV;
510 }
511
512 ret = tc35815_probe1(pdev, pci_memaddr, pci_irq_line);
513
514 if (!ret) {
515 if ((err = pci_enable_device(pdev)) < 0) {
516 printk(KERN_ERR "tc35815_probe: failed to enable device -- err=%d\n", err);
517 return err;
518 }
519 pci_set_master(pdev);
520 }
521
522 return ret;
523 }
524 return -ENODEV;
525 }
526
527 static int __init tc35815_probe1(struct pci_dev *pdev, unsigned int base_addr, unsigned int irq)
528 {
529 static unsigned version_printed = 0;
530 int i;
531 struct tc35815_local *lp;
532 struct tc35815_regs *tr;
533 struct net_device *dev;
534
535 /* Allocate a new 'dev' if needed. */
536 dev = init_etherdev(NULL, sizeof(struct tc35815_local));
537 if (dev == NULL)
538 return -ENOMEM;
539
540 /*
541 * init_etherdev allocs and zeros dev->priv
542 */
543 lp = dev->priv;
544
545 if (tc35815_debug && version_printed++ == 0)
546 printk(KERN_DEBUG "%s", version);
547
548 printk(KERN_INFO "%s: %s found at %#x, irq %d\n",
549 dev->name, cardname, base_addr, irq);
550
551 /* Fill in the 'dev' fields. */
552 dev->irq = irq;
553 dev->base_addr = (unsigned long)ioremap(base_addr,
554 sizeof(struct tc35815_regs));
555 tr = (struct tc35815_regs*)dev->base_addr;
556
557 tc35815_chip_reset(dev);
558
559 /* Retrieve and print the ethernet address. */
560 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
561 ;
562 for (i = 0; i < 6; i += 2) {
563 unsigned short data;
564 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
565 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
566 ;
567 data = tc_readl(&tr->PROM_Data);
568 dev->dev_addr[i] = data & 0xff;
569 dev->dev_addr[i+1] = data >> 8;
570 }
571 for (i = 0; i < 6; i++)
572 printk(" %2.2x", dev->dev_addr[i]);
573 printk("\n");
574
575 /* Initialize the device structure. */
576 lp->pdev = pdev;
577 lp->next_module = root_tc35815_dev;
578 root_tc35815_dev = dev;
579
580 if (dev->mem_start > 0) {
581 lp->option = dev->mem_start;
582 if ((lp->option & TC35815_OPT_10M) &&
583 (lp->option & TC35815_OPT_100M)) {
584 /* if both speed speficied, auto select. */
585 lp->option &= ~(TC35815_OPT_10M | TC35815_OPT_100M);
586 }
587 }
588 //XXX fixme
589 lp->option |= TC35815_OPT_10M;
590
591 /* do auto negotiation */
592 tc35815_phy_chip_init(dev);
593 printk(KERN_INFO "%s: linkspeed %dMbps, %s Duplex\n",
594 dev->name, lp->linkspeed, lp->fullduplex ? "Full" : "Half");
595
596 dev->open = tc35815_open;
597 dev->stop = tc35815_close;
598 dev->tx_timeout = tc35815_tx_timeout;
599 dev->watchdog_timeo = TX_TIMEOUT;
600 dev->hard_start_xmit = tc35815_send_packet;
601 dev->get_stats = tc35815_get_stats;
602 dev->set_multicast_list = tc35815_set_multicast_list;
603
604 #if 0 /* XXX called in init_etherdev */
605 /* Fill in the fields of the device structure with ethernet values. */
606 ether_setup(dev);
607 #endif
608
609 return 0;
610 }
611
612
613 static int
614 tc35815_init_queues(struct net_device *dev)
615 {
616 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
617 int i;
618 unsigned long fd_addr;
619
620 if (!lp->fd_buf) {
621 if (sizeof(struct FDesc) +
622 sizeof(struct BDesc) * RX_BUF_PAGES +
623 sizeof(struct FDesc) * RX_FD_NUM +
624 sizeof(struct TxFD) * TX_FD_NUM > PAGE_SIZE * FD_PAGE_NUM) {
625 printk(KERN_WARNING "%s: Invalid Queue Size.\n", dev->name);
626 return -ENOMEM;
627 }
628
629 if ((lp->fd_buf = (void *)__get_free_pages(GFP_KERNEL, FD_PAGE_ORDER)) == 0)
630 return -ENOMEM;
631 for (i = 0; i < RX_BUF_PAGES; i++) {
632 if ((lp->data_buf[i] = (void *)get_zeroed_page(GFP_KERNEL)) == 0) {
633 while (--i >= 0) {
634 free_page((unsigned long)lp->data_buf[i]);
635 lp->data_buf[i] = 0;
636 }
637 free_page((unsigned long)lp->fd_buf);
638 lp->fd_buf = 0;
639 return -ENOMEM;
640 }
641 #ifdef __mips__
642 dma_cache_wback_inv((unsigned long)lp->data_buf[i], PAGE_SIZE * FD_PAGE_NUM);
643 #endif
644 }
645 #ifdef __mips__
646 dma_cache_wback_inv((unsigned long)lp->fd_buf, PAGE_SIZE * FD_PAGE_NUM);
647 #endif
648 } else {
649 clear_page(lp->fd_buf);
650 #ifdef __mips__
651 dma_cache_wback_inv((unsigned long)lp->fd_buf, PAGE_SIZE * FD_PAGE_NUM);
652 #endif
653 }
654 #ifdef __mips__
655 fd_addr = (unsigned long)vtonocache(lp->fd_buf);
656 #else
657 fd_addr = (unsigned long)lp->fd_buf;
658 #endif
659
660 /* Free Descriptors (for Receive) */
661 lp->rfd_base = (struct RxFD *)fd_addr;
662 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
663 for (i = 0; i < RX_FD_NUM; i++) {
664 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
665 }
666 lp->rfd_cur = lp->rfd_base;
667 lp->rfd_limit = (struct RxFD *)(fd_addr -
668 sizeof(struct FDesc) -
669 sizeof(struct BDesc) * 30);
670
671 /* Transmit Descriptors */
672 lp->tfd_base = (struct TxFD *)fd_addr;
673 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
674 for (i = 0; i < TX_FD_NUM; i++) {
675 lp->tfd_base[i].fd.FDNext = cpu_to_le32(virt_to_bus(&lp->tfd_base[i+1]));
676 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
677 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
678 }
679 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(virt_to_bus(&lp->tfd_base[0]));
680 lp->tfd_start = 0;
681 lp->tfd_end = 0;
682
683 /* Buffer List (for Receive) */
684 lp->fbl_ptr = (struct FrFD *)fd_addr;
685 lp->fbl_ptr->fd.FDNext = cpu_to_le32(virt_to_bus(lp->fbl_ptr));
686 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_PAGES | FD_CownsFD);
687 for (i = 0; i < RX_BUF_PAGES; i++) {
688 lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(virt_to_bus(lp->data_buf[i]));
689 /* BDID is index of FrFD.bd[] */
690 lp->fbl_ptr->bd[i].BDCtl =
691 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) | PAGE_SIZE);
692 }
693 lp->fbl_curid = 0;
694
695 return 0;
696 }
697
698 static void
699 tc35815_clear_queues(struct net_device *dev)
700 {
701 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
702 int i;
703
704 for (i = 0; i < TX_FD_NUM; i++) {
705 struct sk_buff *skb = (struct sk_buff *)
706 le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
707 if (skb)
708 dev_kfree_skb_any(skb);
709 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
710 }
711
712 tc35815_init_queues(dev);
713 }
714
715 static void
716 tc35815_free_queues(struct net_device *dev)
717 {
718 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
719 int i;
720
721 if (lp->tfd_base) {
722 for (i = 0; i < TX_FD_NUM; i++) {
723 struct sk_buff *skb = (struct sk_buff *)
724 le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
725 if (skb)
726 dev_kfree_skb_any(skb);
727 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
728 }
729 }
730
731 lp->rfd_base = NULL;
732 lp->rfd_base = NULL;
733 lp->rfd_limit = NULL;
734 lp->rfd_cur = NULL;
735 lp->fbl_ptr = NULL;
736
737 for (i = 0; i < RX_BUF_PAGES; i++) {
738 if (lp->data_buf[i])
739 free_page((unsigned long)lp->data_buf[i]);
740 lp->data_buf[i] = 0;
741 }
742 if (lp->fd_buf)
743 __free_pages(lp->fd_buf, FD_PAGE_ORDER);
744 lp->fd_buf = NULL;
745 }
746
747 static void
748 dump_txfd(struct TxFD *fd)
749 {
750 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
751 le32_to_cpu(fd->fd.FDNext),
752 le32_to_cpu(fd->fd.FDSystem),
753 le32_to_cpu(fd->fd.FDStat),
754 le32_to_cpu(fd->fd.FDCtl));
755 printk("BD: ");
756 printk(" %08x %08x",
757 le32_to_cpu(fd->bd.BuffData),
758 le32_to_cpu(fd->bd.BDCtl));
759 printk("\n");
760 }
761
762 static int
763 dump_rxfd(struct RxFD *fd)
764 {
765 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
766 if (bd_count > 8)
767 bd_count = 8;
768 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
769 le32_to_cpu(fd->fd.FDNext),
770 le32_to_cpu(fd->fd.FDSystem),
771 le32_to_cpu(fd->fd.FDStat),
772 le32_to_cpu(fd->fd.FDCtl));
773 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
774 return 0;
775 printk("BD: ");
776 for (i = 0; i < bd_count; i++)
777 printk(" %08x %08x",
778 le32_to_cpu(fd->bd[i].BuffData),
779 le32_to_cpu(fd->bd[i].BDCtl));
780 printk("\n");
781 return bd_count;
782 }
783
784 static void
785 dump_frfd(struct FrFD *fd)
786 {
787 int i;
788 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
789 le32_to_cpu(fd->fd.FDNext),
790 le32_to_cpu(fd->fd.FDSystem),
791 le32_to_cpu(fd->fd.FDStat),
792 le32_to_cpu(fd->fd.FDCtl));
793 printk("BD: ");
794 for (i = 0; i < RX_BUF_PAGES; i++)
795 printk(" %08x %08x",
796 le32_to_cpu(fd->bd[i].BuffData),
797 le32_to_cpu(fd->bd[i].BDCtl));
798 printk("\n");
799 }
800
801 static void
802 panic_queues(struct net_device *dev)
803 {
804 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
805 int i;
806
807 printk("TxFD base %p, start %d, end %d\n",
808 lp->tfd_base, lp->tfd_start, lp->tfd_end);
809 printk("RxFD base %p limit %p cur %p\n",
810 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
811 printk("FrFD %p\n", lp->fbl_ptr);
812 for (i = 0; i < TX_FD_NUM; i++)
813 dump_txfd(&lp->tfd_base[i]);
814 for (i = 0; i < RX_FD_NUM; i++) {
815 int bd_count = dump_rxfd(&lp->rfd_base[i]);
816 i += (bd_count + 1) / 2; /* skip BDs */
817 }
818 dump_frfd(lp->fbl_ptr);
819 panic("%s: Illegal queue state.", dev->name);
820 }
821
822 static void print_buf(char *add, int length)
823 {
824 int i;
825 int len = length;
826
827 printk("print_buf(%08x)(%x)\n", (unsigned int) add,length);
828
829 if (len > 100)
830 len = 100;
831 for (i = 0; i < len; i++) {
832 printk(" %2.2X", (unsigned char) add[i]);
833 if (!(i % 16))
834 printk("\n");
835 }
836 printk("\n");
837 }
838
839 static void print_eth(char *add)
840 {
841 int i;
842
843 printk("print_eth(%08x)\n", (unsigned int) add);
844 for (i = 0; i < 6; i++)
845 printk(" %2.2X", (unsigned char) add[i + 6]);
846 printk(" =>");
847 for (i = 0; i < 6; i++)
848 printk(" %2.2X", (unsigned char) add[i]);
849 printk(" : %2.2X%2.2X\n", (unsigned char) add[12], (unsigned char) add[13]);
850 }
851
852 /*
853 * Open/initialize the board. This is called (in the current kernel)
854 * sometime after booting when the 'ifconfig' program is run.
855 *
856 * This routine should set everything up anew at each open, even
857 * registers that "should" only need to be set once at boot, so that
858 * there is non-reboot way to recover if something goes wrong.
859 */
860 static int
861 tc35815_open(struct net_device *dev)
862 {
863 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
864 /*
865 * This is used if the interrupt line can turned off (shared).
866 * See 3c503.c for an example of selecting the IRQ at config-time.
867 */
868
869 if (dev->irq == 0 ||
870 request_irq(dev->irq, &tc35815_interrupt, SA_SHIRQ, cardname, dev)) {
871 return -EAGAIN;
872 }
873
874 tc35815_chip_reset(dev);
875
876 if (tc35815_init_queues(dev) != 0) {
877 free_irq(dev->irq, dev);
878 return -EAGAIN;
879 }
880
881 /* Reset the hardware here. Don't forget to set the station address. */
882 tc35815_chip_init(dev);
883
884 lp->tbusy = 0;
885 netif_start_queue(dev);
886
887 MOD_INC_USE_COUNT;
888
889 return 0;
890 }
891
892 static void tc35815_tx_timeout(struct net_device *dev)
893 {
894 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
895 struct tc35815_regs *tr = (struct tc35815_regs *)dev->base_addr;
896 int flags;
897
898 save_and_cli(flags);
899 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
900 dev->name, tc_readl(&tr->Tx_Stat));
901 /* Try to restart the adaptor. */
902 tc35815_chip_reset(dev);
903 tc35815_clear_queues(dev);
904 tc35815_chip_init(dev);
905 lp->tbusy=0;
906 restore_flags(flags);
907 dev->trans_start = jiffies;
908 netif_wake_queue(dev);
909 }
910
911 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
912 {
913 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
914 struct tc35815_regs *tr = (struct tc35815_regs *)dev->base_addr;
915
916 if (netif_queue_stopped(dev)) {
917 /*
918 * If we get here, some higher level has decided we are broken.
919 * There should really be a "kick me" function call instead.
920 */
921 int tickssofar = jiffies - dev->trans_start;
922 if (tickssofar < 5)
923 return 1;
924 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
925 dev->name, tc_readl(&tr->Tx_Stat));
926 /* Try to restart the adaptor. */
927 tc35815_chip_reset(dev);
928 tc35815_clear_queues(dev);
929 tc35815_chip_init(dev);
930 lp->tbusy=0;
931 dev->trans_start = jiffies;
932 netif_wake_queue(dev);
933 }
934
935 /*
936 * Block a timer-based transmit from overlapping. This could better be
937 * done with atomic_swap(1, lp->tbusy), but set_bit() works as well.
938 */
939 if (test_and_set_bit(0, (void*)&lp->tbusy) != 0) {
940 printk(KERN_WARNING "%s: Transmitter access conflict.\n", dev->name);
941 dev_kfree_skb_any(skb);
942 } else {
943 short length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
944 unsigned char *buf = skb->data;
945 struct TxFD *txfd = &lp->tfd_base[lp->tfd_start];
946 int flags;
947 lp->stats.tx_bytes += skb->len;
948
949
950 #ifdef __mips__
951 dma_cache_wback_inv((unsigned long)buf, length);
952 #endif
953
954 save_and_cli(flags);
955
956 /* failsafe... */
957 if (lp->tfd_start != lp->tfd_end)
958 tc35815_txdone(dev);
959
960
961 txfd->bd.BuffData = cpu_to_le32(virt_to_bus(buf));
962
963 txfd->bd.BDCtl = cpu_to_le32(length);
964 txfd->fd.FDSystem = cpu_to_le32((__u32)skb);
965 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
966
967 if (lp->tfd_start == lp->tfd_end) {
968 /* Start DMA Transmitter. */
969 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
970 #ifdef GATHER_TXINT
971 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
972 #endif
973 if (tc35815_debug > 2) {
974 printk("%s: starting TxFD.\n", dev->name);
975 dump_txfd(txfd);
976 if (tc35815_debug > 3)
977 print_eth(buf);
978 }
979 tc_writel(virt_to_bus(txfd), &tr->TxFrmPtr);
980 } else {
981 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
982 if (tc35815_debug > 2) {
983 printk("%s: queueing TxFD.\n", dev->name);
984 dump_txfd(txfd);
985 if (tc35815_debug > 3)
986 print_eth(buf);
987 }
988 }
989 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
990
991 dev->trans_start = jiffies;
992
993 if ((lp->tfd_start + 1) % TX_FD_NUM != lp->tfd_end) {
994 /* we can send another packet */
995 lp->tbusy = 0;
996 netif_start_queue(dev);
997 } else {
998 netif_stop_queue(dev);
999 if (tc35815_debug > 1)
1000 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1001 }
1002 restore_flags(flags);
1003 }
1004
1005 return 0;
1006 }
1007
1008 #define FATAL_ERROR_INT \
1009 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1010 static void tc35815_fatal_error_interrupt(struct net_device *dev, int status)
1011 {
1012 static int count;
1013 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1014 dev->name, status);
1015
1016 if (status & Int_IntPCI)
1017 printk(" IntPCI");
1018 if (status & Int_DmParErr)
1019 printk(" DmParErr");
1020 if (status & Int_IntNRAbt)
1021 printk(" IntNRAbt");
1022 printk("\n");
1023 if (count++ > 100)
1024 panic("%s: Too many fatal errors.", dev->name);
1025 printk(KERN_WARNING "%s: Resetting %s...\n", dev->name, cardname);
1026 /* Try to restart the adaptor. */
1027 tc35815_chip_reset(dev);
1028 tc35815_clear_queues(dev);
1029 tc35815_chip_init(dev);
1030 }
1031
1032 /*
1033 * The typical workload of the driver:
1034 * Handle the network interface interrupts.
1035 */
1036 static irqreturn_t tc35815_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1037 {
1038 struct net_device *dev = dev_id;
1039 struct tc35815_regs *tr;
1040 struct tc35815_local *lp;
1041 int status, boguscount = 0;
1042 int handled = 0;
1043
1044 if (dev == NULL) {
1045 printk(KERN_WARNING "%s: irq %d for unknown device.\n", cardname, irq);
1046 return IRQ_NONE;
1047 }
1048
1049 tr = (struct tc35815_regs*)dev->base_addr;
1050 lp = (struct tc35815_local *)dev->priv;
1051
1052 do {
1053 status = tc_readl(&tr->Int_Src);
1054 if (status == 0)
1055 break;
1056 handled = 1;
1057 tc_writel(status, &tr->Int_Src); /* write to clear */
1058
1059 /* Fatal errors... */
1060 if (status & FATAL_ERROR_INT) {
1061 tc35815_fatal_error_interrupt(dev, status);
1062 break;
1063 }
1064 /* recoverable errors */
1065 if (status & Int_IntFDAEx) {
1066 /* disable FDAEx int. (until we make rooms...) */
1067 tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);
1068 printk(KERN_WARNING
1069 "%s: Free Descriptor Area Exhausted (%#x).\n",
1070 dev->name, status);
1071 lp->stats.rx_dropped++;
1072 }
1073 if (status & Int_IntBLEx) {
1074 /* disable BLEx int. (until we make rooms...) */
1075 tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);
1076 printk(KERN_WARNING
1077 "%s: Buffer List Exhausted (%#x).\n",
1078 dev->name, status);
1079 lp->stats.rx_dropped++;
1080 }
1081 if (status & Int_IntExBD) {
1082 printk(KERN_WARNING
1083 "%s: Excessive Buffer Descriptiors (%#x).\n",
1084 dev->name, status);
1085 lp->stats.rx_length_errors++;
1086 }
1087 /* normal notification */
1088 if (status & Int_IntMacRx) {
1089 /* Got a packet(s). */
1090 lp->lstats.rx_ints++;
1091 tc35815_rx(dev);
1092 }
1093 if (status & Int_IntMacTx) {
1094 lp->lstats.tx_ints++;
1095 tc35815_txdone(dev);
1096 }
1097 } while (++boguscount < 20) ;
1098
1099 return IRQ_RETVAL(handled);
1100 }
1101
1102 /* We have a good packet(s), get it/them out of the buffers. */
1103 static void
1104 tc35815_rx(struct net_device *dev)
1105 {
1106 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1107 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1108 unsigned int fdctl;
1109 int i;
1110 int buf_free_count = 0;
1111 int fd_free_count = 0;
1112
1113 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1114 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1115 int pkt_len = fdctl & FD_FDLength_MASK;
1116 struct RxFD *next_rfd;
1117 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1118
1119 if (tc35815_debug > 2)
1120 dump_rxfd(lp->rfd_cur);
1121 if (status & Rx_Good) {
1122 /* Malloc up new buffer. */
1123 struct sk_buff *skb;
1124 unsigned char *data;
1125 int cur_bd, offset;
1126
1127 lp->stats.rx_bytes += pkt_len;
1128
1129 skb = dev_alloc_skb(pkt_len + 2); /* +2: for reserve */
1130 if (skb == NULL) {
1131 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
1132 dev->name);
1133 lp->stats.rx_dropped++;
1134 break;
1135 }
1136 skb_reserve(skb, 2); /* 16 bit alignment */
1137 skb->dev = dev;
1138
1139 data = skb_put(skb, pkt_len);
1140
1141 /* copy from receive buffer */
1142 cur_bd = 0;
1143 offset = 0;
1144 while (offset < pkt_len && cur_bd < bd_count) {
1145 int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
1146 BD_BuffLength_MASK;
1147 void *rxbuf =
1148 bus_to_virt(le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData));
1149 #ifdef __mips__
1150 dma_cache_inv((unsigned long)rxbuf, len);
1151 #endif
1152 memcpy(data + offset, rxbuf, len);
1153 offset += len;
1154 cur_bd++;
1155 }
1156 // print_buf(data,pkt_len);
1157 if (tc35815_debug > 3)
1158 print_eth(data);
1159 skb->protocol = eth_type_trans(skb, dev);
1160 netif_rx(skb);
1161 lp->stats.rx_packets++;
1162 } else {
1163 lp->stats.rx_errors++;
1164 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1165 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1166 status &= ~(Rx_LongErr|Rx_CRCErr);
1167 status |= Rx_Over;
1168 }
1169 if (status & Rx_LongErr) lp->stats.rx_length_errors++;
1170 if (status & Rx_Over) lp->stats.rx_fifo_errors++;
1171 if (status & Rx_CRCErr) lp->stats.rx_crc_errors++;
1172 if (status & Rx_Align) lp->stats.rx_frame_errors++;
1173 }
1174
1175 if (bd_count > 0) {
1176 /* put Free Buffer back to controller */
1177 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1178 unsigned char id =
1179 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1180 if (id >= RX_BUF_PAGES) {
1181 printk("%s: invalid BDID.\n", dev->name);
1182 panic_queues(dev);
1183 }
1184 /* free old buffers */
1185 while (lp->fbl_curid != id) {
1186 bdctl = le32_to_cpu(lp->fbl_ptr->bd[lp->fbl_curid].BDCtl);
1187 if (bdctl & BD_CownsBD) {
1188 printk("%s: Freeing invalid BD.\n",
1189 dev->name);
1190 panic_queues(dev);
1191 }
1192 /* pass BD to controler */
1193 /* Note: BDLength was modified by chip. */
1194 lp->fbl_ptr->bd[lp->fbl_curid].BDCtl =
1195 cpu_to_le32(BD_CownsBD |
1196 (lp->fbl_curid << BD_RxBDID_SHIFT) |
1197 PAGE_SIZE);
1198 lp->fbl_curid =
1199 (lp->fbl_curid + 1) % RX_BUF_PAGES;
1200 if (tc35815_debug > 2) {
1201 printk("%s: Entering new FBD %d\n",
1202 dev->name, lp->fbl_curid);
1203 dump_frfd(lp->fbl_ptr);
1204 }
1205 buf_free_count++;
1206 }
1207 }
1208
1209 /* put RxFD back to controller */
1210 next_rfd = bus_to_virt(le32_to_cpu(lp->rfd_cur->fd.FDNext));
1211 #ifdef __mips__
1212 next_rfd = (struct RxFD *)vtonocache(next_rfd);
1213 #endif
1214 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1215 printk("%s: RxFD FDNext invalid.\n", dev->name);
1216 panic_queues(dev);
1217 }
1218 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1219 /* pass FD to controler */
1220 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead); /* for debug */
1221 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1222 lp->rfd_cur++;
1223 fd_free_count++;
1224 }
1225
1226 lp->rfd_cur = next_rfd;
1227 }
1228
1229 /* re-enable BL/FDA Exhaust interrupts. */
1230 if (fd_free_count) {
1231 tc_writel(tc_readl(&tr->Int_En) | Int_FDAExEn, &tr->Int_En);
1232 if (buf_free_count)
1233 tc_writel(tc_readl(&tr->Int_En) | Int_BLExEn, &tr->Int_En);
1234 }
1235 }
1236
1237 #ifdef NO_CHECK_CARRIER
1238 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1239 #else
1240 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1241 #endif
1242
1243 static void
1244 tc35815_check_tx_stat(struct net_device *dev, int status)
1245 {
1246 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1247 const char *msg = NULL;
1248
1249 /* count collisions */
1250 if (status & Tx_ExColl)
1251 lp->stats.collisions += 16;
1252 if (status & Tx_TxColl_MASK)
1253 lp->stats.collisions += status & Tx_TxColl_MASK;
1254
1255 /* WORKAROUND: ignore LostCrS in full duplex operation */
1256 if (lp->fullduplex)
1257 status &= ~Tx_NCarr;
1258
1259 if (!(status & TX_STA_ERR)) {
1260 /* no error. */
1261 lp->stats.tx_packets++;
1262 return;
1263 }
1264
1265 lp->stats.tx_errors++;
1266 if (status & Tx_ExColl) {
1267 lp->stats.tx_aborted_errors++;
1268 msg = "Excessive Collision.";
1269 }
1270 if (status & Tx_Under) {
1271 lp->stats.tx_fifo_errors++;
1272 msg = "Tx FIFO Underrun.";
1273 }
1274 if (status & Tx_Defer) {
1275 lp->stats.tx_fifo_errors++;
1276 msg = "Excessive Deferral.";
1277 }
1278 #ifndef NO_CHECK_CARRIER
1279 if (status & Tx_NCarr) {
1280 lp->stats.tx_carrier_errors++;
1281 msg = "Lost Carrier Sense.";
1282 }
1283 #endif
1284 if (status & Tx_LateColl) {
1285 lp->stats.tx_aborted_errors++;
1286 msg = "Late Collision.";
1287 }
1288 if (status & Tx_TxPar) {
1289 lp->stats.tx_fifo_errors++;
1290 msg = "Transmit Parity Error.";
1291 }
1292 if (status & Tx_SQErr) {
1293 lp->stats.tx_heartbeat_errors++;
1294 msg = "Signal Quality Error.";
1295 }
1296 if (msg)
1297 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1298 }
1299
1300 static void
1301 tc35815_txdone(struct net_device *dev)
1302 {
1303 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1304 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1305 struct TxFD *txfd;
1306 unsigned int fdctl;
1307 int num_done = 0;
1308
1309 txfd = &lp->tfd_base[lp->tfd_end];
1310 while (lp->tfd_start != lp->tfd_end &&
1311 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1312 int status = le32_to_cpu(txfd->fd.FDStat);
1313 struct sk_buff *skb;
1314 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1315
1316 if (tc35815_debug > 2) {
1317 printk("%s: complete TxFD.\n", dev->name);
1318 dump_txfd(txfd);
1319 }
1320 tc35815_check_tx_stat(dev, status);
1321
1322 skb = (struct sk_buff *)le32_to_cpu(txfd->fd.FDSystem);
1323 if (skb) {
1324 dev_kfree_skb_any(skb);
1325 }
1326 txfd->fd.FDSystem = cpu_to_le32(0);
1327
1328 num_done++;
1329 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1330 txfd = &lp->tfd_base[lp->tfd_end];
1331 if ((fdnext & ~FD_Next_EOL) != virt_to_bus(txfd)) {
1332 printk("%s: TxFD FDNext invalid.\n", dev->name);
1333 panic_queues(dev);
1334 }
1335 if (fdnext & FD_Next_EOL) {
1336 /* DMA Transmitter has been stopping... */
1337 if (lp->tfd_end != lp->tfd_start) {
1338 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1339 struct TxFD* txhead = &lp->tfd_base[head];
1340 int qlen = (lp->tfd_start + TX_FD_NUM
1341 - lp->tfd_end) % TX_FD_NUM;
1342
1343 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1344 printk("%s: TxFD FDCtl invalid.\n", dev->name);
1345 panic_queues(dev);
1346 }
1347 /* log max queue length */
1348 if (lp->lstats.max_tx_qlen < qlen)
1349 lp->lstats.max_tx_qlen = qlen;
1350
1351
1352 /* start DMA Transmitter again */
1353 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1354 #ifdef GATHER_TXINT
1355 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1356 #endif
1357 if (tc35815_debug > 2) {
1358 printk("%s: start TxFD on queue.\n",
1359 dev->name);
1360 dump_txfd(txfd);
1361 }
1362 tc_writel(virt_to_bus(txfd), &tr->TxFrmPtr);
1363 }
1364 break;
1365 }
1366 }
1367
1368 if (num_done > 0 && lp->tbusy) {
1369 lp->tbusy = 0;
1370 netif_start_queue(dev);
1371 }
1372 }
1373
1374 /* The inverse routine to tc35815_open(). */
1375 static int
1376 tc35815_close(struct net_device *dev)
1377 {
1378 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1379
1380 lp->tbusy = 1;
1381 netif_stop_queue(dev);
1382
1383 /* Flush the Tx and disable Rx here. */
1384
1385 tc35815_chip_reset(dev);
1386 free_irq(dev->irq, dev);
1387
1388 tc35815_free_queues(dev);
1389
1390 MOD_DEC_USE_COUNT;
1391
1392 return 0;
1393 }
1394
1395 /*
1396 * Get the current statistics.
1397 * This may be called with the card open or closed.
1398 */
1399 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1400 {
1401 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1402 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1403 unsigned long flags;
1404
1405 if (netif_running(dev)) {
1406 save_and_cli(flags);
1407 /* Update the statistics from the device registers. */
1408 lp->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);
1409 restore_flags(flags);
1410 }
1411
1412 return &lp->stats;
1413 }
1414
1415 static void tc35815_set_cam_entry(struct tc35815_regs *tr, int index, unsigned char *addr)
1416 {
1417 int cam_index = index * 6;
1418 unsigned long cam_data;
1419 unsigned long saved_addr;
1420 saved_addr = tc_readl(&tr->CAM_Adr);
1421
1422 if (tc35815_debug > 1) {
1423 int i;
1424 printk(KERN_DEBUG "%s: CAM %d:", cardname, index);
1425 for (i = 0; i < 6; i++)
1426 printk(" %02x", addr[i]);
1427 printk("\n");
1428 }
1429 if (index & 1) {
1430 /* read modify write */
1431 tc_writel(cam_index - 2, &tr->CAM_Adr);
1432 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1433 cam_data |= addr[0] << 8 | addr[1];
1434 tc_writel(cam_data, &tr->CAM_Data);
1435 /* write whole word */
1436 tc_writel(cam_index + 2, &tr->CAM_Adr);
1437 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1438 tc_writel(cam_data, &tr->CAM_Data);
1439 } else {
1440 /* write whole word */
1441 tc_writel(cam_index, &tr->CAM_Adr);
1442 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1443 tc_writel(cam_data, &tr->CAM_Data);
1444 /* read modify write */
1445 tc_writel(cam_index + 4, &tr->CAM_Adr);
1446 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1447 cam_data |= addr[4] << 24 | (addr[5] << 16);
1448 tc_writel(cam_data, &tr->CAM_Data);
1449 }
1450
1451 if (tc35815_debug > 2) {
1452 int i;
1453 for (i = cam_index / 4; i < cam_index / 4 + 2; i++) {
1454 tc_writel(i * 4, &tr->CAM_Adr);
1455 printk("CAM 0x%x: %08x",
1456 i * 4, tc_readl(&tr->CAM_Data));
1457 }
1458 }
1459 tc_writel(saved_addr, &tr->CAM_Adr);
1460 }
1461
1462
1463 /*
1464 * Set or clear the multicast filter for this adaptor.
1465 * num_addrs == -1 Promiscuous mode, receive all packets
1466 * num_addrs == 0 Normal mode, clear multicast list
1467 * num_addrs > 0 Multicast mode, receive normal and MC packets,
1468 * and do best-effort filtering.
1469 */
1470 static void
1471 tc35815_set_multicast_list(struct net_device *dev)
1472 {
1473 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1474
1475 if (dev->flags&IFF_PROMISC)
1476 {
1477 /* Enable promiscuous mode */
1478 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1479 }
1480 else if((dev->flags&IFF_ALLMULTI) || dev->mc_count > CAM_ENTRY_MAX - 3)
1481 {
1482 /* CAM 0, 1, 20 are reserved. */
1483 /* Disable promiscuous mode, use normal mode. */
1484 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1485 }
1486 else if(dev->mc_count)
1487 {
1488 struct dev_mc_list* cur_addr = dev->mc_list;
1489 int i;
1490 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1491
1492 tc_writel(0, &tr->CAM_Ctl);
1493 /* Walk the address list, and load the filter */
1494 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
1495 if (!cur_addr)
1496 break;
1497 /* entry 0,1 is reserved. */
1498 tc35815_set_cam_entry(tr, i + 2, cur_addr->dmi_addr);
1499 ena_bits |= CAM_Ena_Bit(i + 2);
1500 }
1501 tc_writel(ena_bits, &tr->CAM_Ena);
1502 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1503 }
1504 else {
1505 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1506 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1507 }
1508 }
1509
1510 static unsigned long tc_phy_read(struct tc35815_regs *tr, int phy, int phy_reg)
1511 {
1512 unsigned long data;
1513 int flags;
1514 save_and_cli(flags);
1515 tc_writel(MD_CA_Busy | (phy << 5) | phy_reg, &tr->MD_CA);
1516 while (tc_readl(&tr->MD_CA) & MD_CA_Busy)
1517 ;
1518 data = tc_readl(&tr->MD_Data);
1519 restore_flags(flags);
1520 return data;
1521 }
1522
1523 static void tc_phy_write(unsigned long d, struct tc35815_regs *tr, int phy, int phy_reg)
1524 {
1525 int flags;
1526 save_and_cli(flags);
1527 tc_writel(d, &tr->MD_Data);
1528 tc_writel(MD_CA_Busy | MD_CA_Wr | (phy << 5) | phy_reg, &tr->MD_CA);
1529 while (tc_readl(&tr->MD_CA) & MD_CA_Busy)
1530 ;
1531 restore_flags(flags);
1532 }
1533
1534 static void tc35815_phy_chip_init(struct net_device *dev)
1535 {
1536 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1537 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1538 static int first = 1;
1539 unsigned short ctl;
1540
1541 if (first) {
1542 unsigned short id0, id1;
1543 int count;
1544 first = 0;
1545
1546 /* first data written to the PHY will be an ID number */
1547 tc_phy_write(0, tr, 0, MII_CONTROL); /* ID:0 */
1548 #if 0
1549 tc_phy_write(MIICNTL_RESET, tr, 0, MII_CONTROL);
1550 printk(KERN_INFO "%s: Resetting PHY...", dev->name);
1551 while (tc_phy_read(tr, 0, MII_CONTROL) & MIICNTL_RESET)
1552 ;
1553 printk("\n");
1554 tc_phy_write(MIICNTL_AUTO|MIICNTL_SPEED|MIICNTL_FDX, tr, 0,
1555 MII_CONTROL);
1556 #endif
1557 id0 = tc_phy_read(tr, 0, MII_PHY_ID0);
1558 id1 = tc_phy_read(tr, 0, MII_PHY_ID1);
1559 printk(KERN_DEBUG "%s: PHY ID %04x %04x\n", dev->name,
1560 id0, id1);
1561 if (lp->option & TC35815_OPT_10M) {
1562 lp->linkspeed = 10;
1563 lp->fullduplex = (lp->option & TC35815_OPT_FULLDUP) != 0;
1564 } else if (lp->option & TC35815_OPT_100M) {
1565 lp->linkspeed = 100;
1566 lp->fullduplex = (lp->option & TC35815_OPT_FULLDUP) != 0;
1567 } else {
1568 /* auto negotiation */
1569 unsigned long neg_result;
1570 tc_phy_write(MIICNTL_AUTO | MIICNTL_RST_AUTO, tr, 0, MII_CONTROL);
1571 printk(KERN_INFO "%s: Auto Negotiation...", dev->name);
1572 count = 0;
1573 while (!(tc_phy_read(tr, 0, MII_STATUS) & MIISTAT_AUTO_DONE)) {
1574 if (count++ > 5000) {
1575 printk(" failed. Assume 10Mbps\n");
1576 lp->linkspeed = 10;
1577 lp->fullduplex = 0;
1578 goto done;
1579 }
1580 if (count % 512 == 0)
1581 printk(".");
1582 mdelay(1);
1583 }
1584 printk(" done.\n");
1585 neg_result = tc_phy_read(tr, 0, MII_ANLPAR);
1586 if (neg_result & (MII_AN_TX_FDX | MII_AN_TX_HDX))
1587 lp->linkspeed = 100;
1588 else
1589 lp->linkspeed = 10;
1590 if (neg_result & (MII_AN_TX_FDX | MII_AN_10_FDX))
1591 lp->fullduplex = 1;
1592 else
1593 lp->fullduplex = 0;
1594 done:
1595 ;
1596 }
1597 }
1598
1599 ctl = 0;
1600 if (lp->linkspeed == 100)
1601 ctl |= MIICNTL_SPEED;
1602 if (lp->fullduplex)
1603 ctl |= MIICNTL_FDX;
1604 tc_phy_write(ctl, tr, 0, MII_CONTROL);
1605
1606 if (lp->fullduplex) {
1607 tc_writel(tc_readl(&tr->MAC_Ctl) | MAC_FullDup, &tr->MAC_Ctl);
1608 }
1609 }
1610
1611 static void tc35815_chip_reset(struct net_device *dev)
1612 {
1613 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1614
1615 /* reset the controller */
1616 tc_writel(MAC_Reset, &tr->MAC_Ctl);
1617 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset)
1618 ;
1619
1620 tc_writel(0, &tr->MAC_Ctl);
1621
1622 /* initialize registers to default value */
1623 tc_writel(0, &tr->DMA_Ctl);
1624 tc_writel(0, &tr->TxThrsh);
1625 tc_writel(0, &tr->TxPollCtr);
1626 tc_writel(0, &tr->RxFragSize);
1627 tc_writel(0, &tr->Int_En);
1628 tc_writel(0, &tr->FDA_Bas);
1629 tc_writel(0, &tr->FDA_Lim);
1630 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
1631 tc_writel(0, &tr->CAM_Ctl);
1632 tc_writel(0, &tr->Tx_Ctl);
1633 tc_writel(0, &tr->Rx_Ctl);
1634 tc_writel(0, &tr->CAM_Ena);
1635 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
1636
1637 }
1638
1639 static void tc35815_chip_init(struct net_device *dev)
1640 {
1641 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1642 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1643 int flags;
1644 unsigned long txctl = TX_CTL_CMD;
1645
1646 tc35815_phy_chip_init(dev);
1647
1648 /* load station address to CAM */
1649 tc35815_set_cam_entry(tr, CAM_ENTRY_SOURCE, dev->dev_addr);
1650
1651 /* Enable CAM (broadcast and unicast) */
1652 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1653 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1654
1655 save_and_cli(flags);
1656
1657 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
1658
1659 tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
1660 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
1661 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
1662 tc_writel(INT_EN_CMD, &tr->Int_En);
1663
1664 /* set queues */
1665 tc_writel(virt_to_bus(lp->rfd_base), &tr->FDA_Bas);
1666 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
1667 &tr->FDA_Lim);
1668 /*
1669 * Activation method:
1670 * First, enable eht MAC Transmitter and the DMA Receive circuits.
1671 * Then enable the DMA Transmitter and the MAC Receive circuits.
1672 */
1673 tc_writel(virt_to_bus(lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
1674 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
1675 /* start MAC transmitter */
1676 /* WORKAROUND: ignore LostCrS in full duplex operation */
1677 if (lp->fullduplex)
1678 txctl = TX_CTL_CMD & ~Tx_EnLCarr;
1679 #ifdef GATHER_TXINT
1680 txctl &= ~Tx_EnComp; /* disable global tx completion int. */
1681 #endif
1682 tc_writel(txctl, &tr->Tx_Ctl);
1683 #if 0 /* No need to polling */
1684 tc_writel(virt_to_bus(lp->tfd_base), &tr->TxFrmPtr); /* start DMA transmitter */
1685 #endif
1686 restore_flags(flags);
1687 }
1688
1689 static int tc35815_proc_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data)
1690 {
1691 int len = 0;
1692 off_t pos = 0;
1693 off_t begin = 0;
1694 struct net_device *dev;
1695
1696 len += sprintf(buffer, "TC35815 statistics:\n");
1697 for (dev = root_tc35815_dev; dev; dev = ((struct tc35815_local *)dev->priv)->next_module) {
1698 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1699 len += sprintf(buffer + len,
1700 "%s: tx_ints %d, rx_ints %d, max_tx_qlen %d\n",
1701 dev->name,
1702 lp->lstats.tx_ints,
1703 lp->lstats.rx_ints,
1704 lp->lstats.max_tx_qlen);
1705 pos = begin + len;
1706
1707 if (pos < offset) {
1708 len = 0;
1709 begin = pos;
1710 }
1711
1712 if (pos > offset+length) break;
1713 }
1714
1715 *start = buffer + (offset - begin);
1716 len -= (offset - begin);
1717
1718 if (len > length) len = length;
1719
1720 return len;
1721 }
1722
1723 /* XXX */
1724 void
1725 tc35815_killall(void)
1726 {
1727 struct net_device *dev;
1728
1729 for (dev = root_tc35815_dev; dev; dev = ((struct tc35815_local *)dev->priv)->next_module) {
1730 if (dev->flags&IFF_UP){
1731 dev->stop(dev);
1732 }
1733 }
1734 }
1735
1736 static struct pci_driver tc35815_driver = {
1737 .name =TC35815_MODULE_NAME,
1738 .probe = tc35815_probe,
1739 .remove = NULL,
1740 .id_table = tc35815_pci_tbl,
1741 };
1742
1743 static int __init tc35815_init_module(void)
1744 {
1745 int err;
1746
1747 if ((err = pci_module_init(&tc35815_driver)) < 0 )
1748 return err;
1749 else
1750 return 0;
1751 }
1752
1753 static void __exit tc35815_cleanup_module(void)
1754 {
1755 struct net_device *next_dev;
1756
1757 while (root_tc35815_dev) {
1758 struct net_device *dev = root_tc35815_dev;
1759 next_dev = ((struct tc35815_local *)dev->priv)->next_module;
1760 iounmap((void *)(dev->base_addr));
1761 unregister_netdev(dev);
1762 kfree(dev);
1763 root_tc35815_dev = next_dev;
1764 }
1765 }
1766 module_init(tc35815_init_module);
1767 module_exit(tc35815_cleanup_module);
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