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[linux-2.6/linux-mips.git] / drivers / net / sunhme.c
bloba031b0f152df72ea5eb12fd1415fd38c9cd9670d
1 /* $Id: sunhme.c,v 1.124 2002/01/15 06:25:51 davem Exp $
2 * sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
3 * auto carrier detecting ethernet driver. Also known as the
4 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
5 *
6 * Copyright (C) 1996, 1998, 1999, 2002 David S. Miller (davem@redhat.com)
7 *
8 * Changes :
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
14 */
15
16 static char version[] =
17 "sunhme.c:v2.01 26/Mar/2002 David S. Miller (davem@redhat.com)\n";
18
19 #include <linux/module.h>
20 #include <linux/config.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/fcntl.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/in.h>
27 #include <linux/slab.h>
28 #include <linux/string.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/ethtool.h>
32 #include <linux/mii.h>
33 #include <linux/crc32.h>
34 #include <linux/random.h>
35 #include <linux/errno.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39
40 #include <asm/system.h>
41 #include <asm/bitops.h>
42 #include <asm/io.h>
43 #include <asm/dma.h>
44 #include <asm/byteorder.h>
45
46 #ifdef __sparc__
47 #include <asm/idprom.h>
48 #include <asm/sbus.h>
49 #include <asm/openprom.h>
50 #include <asm/oplib.h>
51 #include <asm/auxio.h>
52 #ifndef __sparc_v9__
53 #include <asm/io-unit.h>
54 #endif
55 #endif
56 #include <asm/uaccess.h>
57
58 #include <asm/pgtable.h>
59 #include <asm/irq.h>
60
61 #ifdef CONFIG_PCI
62 #include <linux/pci.h>
63 #ifdef __sparc__
64 #include <asm/pbm.h>
65 #endif
66 #endif
67
68 #include "sunhme.h"
69
70
71 static int macaddr[6];
72
73 /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
74 MODULE_PARM(macaddr, "6i");
75 MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
76 MODULE_LICENSE("GPL");
77
78 static struct happy_meal *root_happy_dev;
79
80 #ifdef CONFIG_SBUS
81 static struct quattro *qfe_sbus_list;
82 #endif
83
84 #ifdef CONFIG_PCI
85 static struct quattro *qfe_pci_list;
86 #endif
87
88 #undef HMEDEBUG
89 #undef SXDEBUG
90 #undef RXDEBUG
91 #undef TXDEBUG
92 #undef TXLOGGING
93
94 #ifdef TXLOGGING
95 struct hme_tx_logent {
96 unsigned int tstamp;
97 int tx_new, tx_old;
98 unsigned int action;
99 #define TXLOG_ACTION_IRQ 0x01
100 #define TXLOG_ACTION_TXMIT 0x02
101 #define TXLOG_ACTION_TBUSY 0x04
102 #define TXLOG_ACTION_NBUFS 0x08
103 unsigned int status;
104 };
105 #define TX_LOG_LEN 128
106 static struct hme_tx_logent tx_log[TX_LOG_LEN];
107 static int txlog_cur_entry;
108 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
109 {
110 struct hme_tx_logent *tlp;
111 unsigned long flags;
112
113 save_and_cli(flags);
114 tlp = &tx_log[txlog_cur_entry];
115 tlp->tstamp = (unsigned int)jiffies;
116 tlp->tx_new = hp->tx_new;
117 tlp->tx_old = hp->tx_old;
118 tlp->action = a;
119 tlp->status = s;
120 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
121 restore_flags(flags);
122 }
123 static __inline__ void tx_dump_log(void)
124 {
125 int i, this;
126
127 this = txlog_cur_entry;
128 for (i = 0; i < TX_LOG_LEN; i++) {
129 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
130 tx_log[this].tstamp,
131 tx_log[this].tx_new, tx_log[this].tx_old,
132 tx_log[this].action, tx_log[this].status);
133 this = (this + 1) & (TX_LOG_LEN - 1);
134 }
135 }
136 static __inline__ void tx_dump_ring(struct happy_meal *hp)
137 {
138 struct hmeal_init_block *hb = hp->happy_block;
139 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
140 int i;
141
142 for (i = 0; i < TX_RING_SIZE; i+=4) {
143 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
144 i, i + 4,
145 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
146 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
147 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
148 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
149 }
150 }
151 #else
152 #define tx_add_log(hp, a, s) do { } while(0)
153 #define tx_dump_log() do { } while(0)
154 #define tx_dump_ring(hp) do { } while(0)
155 #endif
156
157 #ifdef HMEDEBUG
158 #define HMD(x) printk x
159 #else
160 #define HMD(x)
161 #endif
162
163 /* #define AUTO_SWITCH_DEBUG */
164
165 #ifdef AUTO_SWITCH_DEBUG
166 #define ASD(x) printk x
167 #else
168 #define ASD(x)
169 #endif
170
171 #define DEFAULT_IPG0 16 /* For lance-mode only */
172 #define DEFAULT_IPG1 8 /* For all modes */
173 #define DEFAULT_IPG2 4 /* For all modes */
174 #define DEFAULT_JAMSIZE 4 /* Toe jam */
175
176 #ifdef CONFIG_PCI
177 /* This happy_pci_ids is declared __initdata because it is only used
178 as an advisory to depmod. If this is ported to the new PCI interface
179 where it could be referenced at any time due to hot plugging,
180 it should be changed to __devinitdata. */
181
182 struct pci_device_id happymeal_pci_ids[] __initdata = {
183 {
184 .vendor = PCI_VENDOR_ID_SUN,
185 .device = PCI_DEVICE_ID_SUN_HAPPYMEAL,
186 .subvendor = PCI_ANY_ID,
187 .subdevice = PCI_ANY_ID,
188 },
189 { } /* Terminating entry */
190 };
191
192 MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
193
194 #endif
195
196 /* NOTE: In the descriptor writes one _must_ write the address
197 * member _first_. The card must not be allowed to see
198 * the updated descriptor flags until the address is
199 * correct. I've added a write memory barrier between
200 * the two stores so that I can sleep well at night... -DaveM
201 */
202
203 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
204 static void sbus_hme_write32(unsigned long reg, u32 val)
205 {
206 sbus_writel(val, reg);
207 }
208
209 static u32 sbus_hme_read32(unsigned long reg)
210 {
211 return sbus_readl(reg);
212 }
213
214 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
215 {
216 rxd->rx_addr = addr;
217 wmb();
218 rxd->rx_flags = flags;
219 }
220
221 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
222 {
223 txd->tx_addr = addr;
224 wmb();
225 txd->tx_flags = flags;
226 }
227
228 static u32 sbus_hme_read_desc32(u32 *p)
229 {
230 return *p;
231 }
232
233 static void pci_hme_write32(unsigned long reg, u32 val)
234 {
235 writel(val, reg);
236 }
237
238 static u32 pci_hme_read32(unsigned long reg)
239 {
240 return readl(reg);
241 }
242
243 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
244 {
245 rxd->rx_addr = cpu_to_le32(addr);
246 wmb();
247 rxd->rx_flags = cpu_to_le32(flags);
248 }
249
250 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
251 {
252 txd->tx_addr = cpu_to_le32(addr);
253 wmb();
254 txd->tx_flags = cpu_to_le32(flags);
255 }
256
257 static u32 pci_hme_read_desc32(u32 *p)
258 {
259 return cpu_to_le32p(p);
260 }
261
262 #define hme_write32(__hp, __reg, __val) \
263 ((__hp)->write32((__reg), (__val)))
264 #define hme_read32(__hp, __reg) \
265 ((__hp)->read32(__reg))
266 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
267 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
268 #define hme_write_txd(__hp, __txd, __flags, __addr) \
269 ((__hp)->write_txd((__txd), (__flags), (__addr)))
270 #define hme_read_desc32(__hp, __p) \
271 ((__hp)->read_desc32(__p))
272 #define hme_dma_map(__hp, __ptr, __size, __dir) \
273 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
274 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
275 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
276 #define hme_dma_sync(__hp, __addr, __size, __dir) \
277 ((__hp)->dma_sync((__hp)->happy_dev, (__addr), (__size), (__dir)))
278 #else
279 #ifdef CONFIG_SBUS
280 /* SBUS only compilation */
281 #define hme_write32(__hp, __reg, __val) \
282 sbus_writel((__val), (__reg))
283 #define hme_read32(__hp, __reg) \
284 sbus_readl(__reg)
285 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
286 do { (__rxd)->rx_addr = (__addr); \
287 wmb(); \
288 (__rxd)->rx_flags = (__flags); \
289 } while(0)
290 #define hme_write_txd(__hp, __txd, __flags, __addr) \
291 do { (__txd)->tx_addr = (__addr); \
292 wmb(); \
293 (__txd)->tx_flags = (__flags); \
294 } while(0)
295 #define hme_read_desc32(__hp, __p) (*(__p))
296 #define hme_dma_map(__hp, __ptr, __size, __dir) \
297 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
298 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
299 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
300 #define hme_dma_sync(__hp, __addr, __size, __dir) \
301 sbus_dma_sync_single((__hp)->happy_dev, (__addr), (__size), (__dir))
302 #else
303 /* PCI only compilation */
304 #define hme_write32(__hp, __reg, __val) \
305 writel((__val), (__reg))
306 #define hme_read32(__hp, __reg) \
307 readl(__reg)
308 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
309 do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
310 wmb(); \
311 (__rxd)->rx_flags = cpu_to_le32(__flags); \
312 } while(0)
313 #define hme_write_txd(__hp, __txd, __flags, __addr) \
314 do { (__txd)->tx_addr = cpu_to_le32(__addr); \
315 wmb(); \
316 (__txd)->tx_flags = cpu_to_le32(__flags); \
317 } while(0)
318 #define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
319 #define hme_dma_map(__hp, __ptr, __size, __dir) \
320 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
321 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
322 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
323 #define hme_dma_sync(__hp, __addr, __size, __dir) \
324 pci_dma_sync_single((__hp)->happy_dev, (__addr), (__size), (__dir))
325 #endif
326 #endif
327
328
329 #ifdef SBUS_DMA_BIDIRECTIONAL
330 # define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
331 #else
332 # define DMA_BIDIRECTIONAL 0
333 #endif
334
335 #ifdef SBUS_DMA_FROMDEVICE
336 # define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
337 #else
338 # define DMA_TODEVICE 1
339 #endif
340
341 #ifdef SBUS_DMA_TODEVICE
342 # define DMA_TODEVICE SBUS_DMA_TODEVICE
343 #else
344 # define DMA_FROMDEVICE 2
345 #endif
346
347
348 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
349 static void BB_PUT_BIT(struct happy_meal *hp, unsigned long tregs, int bit)
350 {
351 hme_write32(hp, tregs + TCVR_BBDATA, bit);
352 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
353 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
354 }
355
356 #if 0
357 static u32 BB_GET_BIT(struct happy_meal *hp, unsigned long tregs, int internal)
358 {
359 u32 ret;
360
361 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
362 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
363 ret = hme_read32(hp, tregs + TCVR_CFG);
364 if (internal)
365 ret &= TCV_CFG_MDIO0;
366 else
367 ret &= TCV_CFG_MDIO1;
368
369 return ret;
370 }
371 #endif
372
373 static u32 BB_GET_BIT2(struct happy_meal *hp, unsigned long tregs, int internal)
374 {
375 u32 retval;
376
377 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
378 udelay(1);
379 retval = hme_read32(hp, tregs + TCVR_CFG);
380 if (internal)
381 retval &= TCV_CFG_MDIO0;
382 else
383 retval &= TCV_CFG_MDIO1;
384 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
385
386 return retval;
387 }
388
389 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
390
391 static int happy_meal_bb_read(struct happy_meal *hp,
392 unsigned long tregs, int reg)
393 {
394 u32 tmp;
395 int retval = 0;
396 int i;
397
398 ASD(("happy_meal_bb_read: reg=%d ", reg));
399
400 /* Enable the MIF BitBang outputs. */
401 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
402
403 /* Force BitBang into the idle state. */
404 for (i = 0; i < 32; i++)
405 BB_PUT_BIT(hp, tregs, 1);
406
407 /* Give it the read sequence. */
408 BB_PUT_BIT(hp, tregs, 0);
409 BB_PUT_BIT(hp, tregs, 1);
410 BB_PUT_BIT(hp, tregs, 1);
411 BB_PUT_BIT(hp, tregs, 0);
412
413 /* Give it the PHY address. */
414 tmp = hp->paddr & 0xff;
415 for (i = 4; i >= 0; i--)
416 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
417
418 /* Tell it what register we want to read. */
419 tmp = (reg & 0xff);
420 for (i = 4; i >= 0; i--)
421 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
422
423 /* Close down the MIF BitBang outputs. */
424 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
425
426 /* Now read in the value. */
427 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
428 for (i = 15; i >= 0; i--)
429 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
430 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
431 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
432 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
433 ASD(("value=%x\n", retval));
434 return retval;
435 }
436
437 static void happy_meal_bb_write(struct happy_meal *hp,
438 unsigned long tregs, int reg,
439 unsigned short value)
440 {
441 u32 tmp;
442 int i;
443
444 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
445
446 /* Enable the MIF BitBang outputs. */
447 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
448
449 /* Force BitBang into the idle state. */
450 for (i = 0; i < 32; i++)
451 BB_PUT_BIT(hp, tregs, 1);
452
453 /* Give it write sequence. */
454 BB_PUT_BIT(hp, tregs, 0);
455 BB_PUT_BIT(hp, tregs, 1);
456 BB_PUT_BIT(hp, tregs, 0);
457 BB_PUT_BIT(hp, tregs, 1);
458
459 /* Give it the PHY address. */
460 tmp = (hp->paddr & 0xff);
461 for (i = 4; i >= 0; i--)
462 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
463
464 /* Tell it what register we will be writing. */
465 tmp = (reg & 0xff);
466 for (i = 4; i >= 0; i--)
467 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
468
469 /* Tell it to become ready for the bits. */
470 BB_PUT_BIT(hp, tregs, 1);
471 BB_PUT_BIT(hp, tregs, 0);
472
473 for (i = 15; i >= 0; i--)
474 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
475
476 /* Close down the MIF BitBang outputs. */
477 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
478 }
479
480 #define TCVR_READ_TRIES 16
481
482 static int happy_meal_tcvr_read(struct happy_meal *hp,
483 unsigned long tregs, int reg)
484 {
485 int tries = TCVR_READ_TRIES;
486 int retval;
487
488 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
489 if (hp->tcvr_type == none) {
490 ASD(("no transceiver, value=TCVR_FAILURE\n"));
491 return TCVR_FAILURE;
492 }
493
494 if (!(hp->happy_flags & HFLAG_FENABLE)) {
495 ASD(("doing bit bang\n"));
496 return happy_meal_bb_read(hp, tregs, reg);
497 }
498
499 hme_write32(hp, tregs + TCVR_FRAME,
500 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
501 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
502 udelay(20);
503 if (!tries) {
504 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
505 return TCVR_FAILURE;
506 }
507 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
508 ASD(("value=%04x\n", retval));
509 return retval;
510 }
511
512 #define TCVR_WRITE_TRIES 16
513
514 static void happy_meal_tcvr_write(struct happy_meal *hp,
515 unsigned long tregs, int reg,
516 unsigned short value)
517 {
518 int tries = TCVR_WRITE_TRIES;
519
520 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
521
522 /* Welcome to Sun Microsystems, can I take your order please? */
523 if (!(hp->happy_flags & HFLAG_FENABLE))
524 return happy_meal_bb_write(hp, tregs, reg, value);
525
526 /* Would you like fries with that? */
527 hme_write32(hp, tregs + TCVR_FRAME,
528 (FRAME_WRITE | (hp->paddr << 23) |
529 ((reg & 0xff) << 18) | (value & 0xffff)));
530 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
531 udelay(20);
532
533 /* Anything else? */
534 if (!tries)
535 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
536
537 /* Fifty-two cents is your change, have a nice day. */
538 }
539
540 /* Auto negotiation. The scheme is very simple. We have a timer routine
541 * that keeps watching the auto negotiation process as it progresses.
542 * The DP83840 is first told to start doing it's thing, we set up the time
543 * and place the timer state machine in it's initial state.
544 *
545 * Here the timer peeks at the DP83840 status registers at each click to see
546 * if the auto negotiation has completed, we assume here that the DP83840 PHY
547 * will time out at some point and just tell us what (didn't) happen. For
548 * complete coverage we only allow so many of the ticks at this level to run,
549 * when this has expired we print a warning message and try another strategy.
550 * This "other" strategy is to force the interface into various speed/duplex
551 * configurations and we stop when we see a link-up condition before the
552 * maximum number of "peek" ticks have occurred.
553 *
554 * Once a valid link status has been detected we configure the BigMAC and
555 * the rest of the Happy Meal to speak the most efficient protocol we could
556 * get a clean link for. The priority for link configurations, highest first
557 * is:
558 * 100 Base-T Full Duplex
559 * 100 Base-T Half Duplex
560 * 10 Base-T Full Duplex
561 * 10 Base-T Half Duplex
562 *
563 * We start a new timer now, after a successful auto negotiation status has
564 * been detected. This timer just waits for the link-up bit to get set in
565 * the BMCR of the DP83840. When this occurs we print a kernel log message
566 * describing the link type in use and the fact that it is up.
567 *
568 * If a fatal error of some sort is signalled and detected in the interrupt
569 * service routine, and the chip is reset, or the link is ifconfig'd down
570 * and then back up, this entire process repeats itself all over again.
571 */
572 static int try_next_permutation(struct happy_meal *hp, unsigned long tregs)
573 {
574 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
575
576 /* Downgrade from full to half duplex. Only possible
577 * via ethtool.
578 */
579 if (hp->sw_bmcr & BMCR_FULLDPLX) {
580 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
581 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
582 return 0;
583 }
584
585 /* Downgrade from 100 to 10. */
586 if (hp->sw_bmcr & BMCR_SPEED100) {
587 hp->sw_bmcr &= ~(BMCR_SPEED100);
588 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
589 return 0;
590 }
591
592 /* We've tried everything. */
593 return -1;
594 }
595
596 static void display_link_mode(struct happy_meal *hp, unsigned long tregs)
597 {
598 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
599 if (hp->tcvr_type == external)
600 printk("external ");
601 else
602 printk("internal ");
603 printk("transceiver at ");
604 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
605 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
606 if (hp->sw_lpa & LPA_100FULL)
607 printk("100Mb/s, Full Duplex.\n");
608 else
609 printk("100Mb/s, Half Duplex.\n");
610 } else {
611 if (hp->sw_lpa & LPA_10FULL)
612 printk("10Mb/s, Full Duplex.\n");
613 else
614 printk("10Mb/s, Half Duplex.\n");
615 }
616 }
617
618 static void display_forced_link_mode(struct happy_meal *hp, unsigned long tregs)
619 {
620 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
621 if (hp->tcvr_type == external)
622 printk("external ");
623 else
624 printk("internal ");
625 printk("transceiver at ");
626 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
627 if (hp->sw_bmcr & BMCR_SPEED100)
628 printk("100Mb/s, ");
629 else
630 printk("10Mb/s, ");
631 if (hp->sw_bmcr & BMCR_FULLDPLX)
632 printk("Full Duplex.\n");
633 else
634 printk("Half Duplex.\n");
635 }
636
637 static int set_happy_link_modes(struct happy_meal *hp, unsigned long tregs)
638 {
639 int full;
640
641 /* All we care about is making sure the bigmac tx_cfg has a
642 * proper duplex setting.
643 */
644 if (hp->timer_state == arbwait) {
645 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
646 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
647 goto no_response;
648 if (hp->sw_lpa & LPA_100FULL)
649 full = 1;
650 else if (hp->sw_lpa & LPA_100HALF)
651 full = 0;
652 else if (hp->sw_lpa & LPA_10FULL)
653 full = 1;
654 else
655 full = 0;
656 } else {
657 /* Forcing a link mode. */
658 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
659 if (hp->sw_bmcr & BMCR_FULLDPLX)
660 full = 1;
661 else
662 full = 0;
663 }
664
665 /* Before changing other bits in the tx_cfg register, and in
666 * general any of other the TX config registers too, you
667 * must:
668 * 1) Clear Enable
669 * 2) Poll with reads until that bit reads back as zero
670 * 3) Make TX configuration changes
671 * 4) Set Enable once more
672 */
673 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
674 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
675 ~(BIGMAC_TXCFG_ENABLE));
676 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
677 barrier();
678 if (full) {
679 hp->happy_flags |= HFLAG_FULL;
680 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
681 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
682 BIGMAC_TXCFG_FULLDPLX);
683 } else {
684 hp->happy_flags &= ~(HFLAG_FULL);
685 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
686 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
687 ~(BIGMAC_TXCFG_FULLDPLX));
688 }
689 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
690 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
691 BIGMAC_TXCFG_ENABLE);
692 return 0;
693 no_response:
694 return 1;
695 }
696
697 static int happy_meal_init(struct happy_meal *hp);
698
699 static int is_lucent_phy(struct happy_meal *hp)
700 {
701 unsigned long tregs = hp->tcvregs;
702 unsigned short mr2, mr3;
703 int ret = 0;
704
705 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
706 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
707 if ((mr2 & 0xffff) == 0x0180 &&
708 ((mr3 & 0xffff) >> 10) == 0x1d)
709 ret = 1;
710
711 return ret;
712 }
713
714 static void happy_meal_timer(unsigned long data)
715 {
716 struct happy_meal *hp = (struct happy_meal *) data;
717 unsigned long tregs = hp->tcvregs;
718 int restart_timer = 0;
719
720 spin_lock_irq(&hp->happy_lock);
721
722 hp->timer_ticks++;
723 switch(hp->timer_state) {
724 case arbwait:
725 /* Only allow for 5 ticks, thats 10 seconds and much too
726 * long to wait for arbitration to complete.
727 */
728 if (hp->timer_ticks >= 10) {
729 /* Enter force mode. */
730 do_force_mode:
731 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
732 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
733 hp->dev->name);
734 hp->sw_bmcr = BMCR_SPEED100;
735 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
736
737 if (!is_lucent_phy(hp)) {
738 /* OK, seems we need do disable the transceiver for the first
739 * tick to make sure we get an accurate link state at the
740 * second tick.
741 */
742 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
743 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
744 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
745 }
746 hp->timer_state = ltrywait;
747 hp->timer_ticks = 0;
748 restart_timer = 1;
749 } else {
750 /* Anything interesting happen? */
751 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
752 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
753 int ret;
754
755 /* Just what we've been waiting for... */
756 ret = set_happy_link_modes(hp, tregs);
757 if (ret) {
758 /* Ooops, something bad happened, go to force
759 * mode.
760 *
761 * XXX Broken hubs which don't support 802.3u
762 * XXX auto-negotiation make this happen as well.
763 */
764 goto do_force_mode;
765 }
766
767 /* Success, at least so far, advance our state engine. */
768 hp->timer_state = lupwait;
769 restart_timer = 1;
770 } else {
771 restart_timer = 1;
772 }
773 }
774 break;
775
776 case lupwait:
777 /* Auto negotiation was successful and we are awaiting a
778 * link up status. I have decided to let this timer run
779 * forever until some sort of error is signalled, reporting
780 * a message to the user at 10 second intervals.
781 */
782 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
783 if (hp->sw_bmsr & BMSR_LSTATUS) {
784 /* Wheee, it's up, display the link mode in use and put
785 * the timer to sleep.
786 */
787 display_link_mode(hp, tregs);
788 hp->timer_state = asleep;
789 restart_timer = 0;
790 } else {
791 if (hp->timer_ticks >= 10) {
792 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
793 "not completely up.\n", hp->dev->name);
794 hp->timer_ticks = 0;
795 restart_timer = 1;
796 } else {
797 restart_timer = 1;
798 }
799 }
800 break;
801
802 case ltrywait:
803 /* Making the timeout here too long can make it take
804 * annoyingly long to attempt all of the link mode
805 * permutations, but then again this is essentially
806 * error recovery code for the most part.
807 */
808 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
809 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
810 if (hp->timer_ticks == 1) {
811 if (!is_lucent_phy(hp)) {
812 /* Re-enable transceiver, we'll re-enable the transceiver next
813 * tick, then check link state on the following tick.
814 */
815 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
816 happy_meal_tcvr_write(hp, tregs,
817 DP83840_CSCONFIG, hp->sw_csconfig);
818 }
819 restart_timer = 1;
820 break;
821 }
822 if (hp->timer_ticks == 2) {
823 if (!is_lucent_phy(hp)) {
824 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
825 happy_meal_tcvr_write(hp, tregs,
826 DP83840_CSCONFIG, hp->sw_csconfig);
827 }
828 restart_timer = 1;
829 break;
830 }
831 if (hp->sw_bmsr & BMSR_LSTATUS) {
832 /* Force mode selection success. */
833 display_forced_link_mode(hp, tregs);
834 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
835 hp->timer_state = asleep;
836 restart_timer = 0;
837 } else {
838 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
839 int ret;
840
841 ret = try_next_permutation(hp, tregs);
842 if (ret == -1) {
843 /* Aieee, tried them all, reset the
844 * chip and try all over again.
845 */
846
847 /* Let the user know... */
848 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
849 hp->dev->name);
850
851 ret = happy_meal_init(hp);
852 if (ret) {
853 /* ho hum... */
854 printk(KERN_ERR "%s: Error, cannot re-init the "
855 "Happy Meal.\n", hp->dev->name);
856 }
857 goto out;
858 }
859 if (!is_lucent_phy(hp)) {
860 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
861 DP83840_CSCONFIG);
862 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
863 happy_meal_tcvr_write(hp, tregs,
864 DP83840_CSCONFIG, hp->sw_csconfig);
865 }
866 hp->timer_ticks = 0;
867 restart_timer = 1;
868 } else {
869 restart_timer = 1;
870 }
871 }
872 break;
873
874 case asleep:
875 default:
876 /* Can't happens.... */
877 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
878 hp->dev->name);
879 restart_timer = 0;
880 hp->timer_ticks = 0;
881 hp->timer_state = asleep; /* foo on you */
882 break;
883 };
884
885 if (restart_timer) {
886 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
887 add_timer(&hp->happy_timer);
888 }
889
890 out:
891 spin_unlock_irq(&hp->happy_lock);
892 }
893
894 #define TX_RESET_TRIES 32
895 #define RX_RESET_TRIES 32
896
897 /* hp->happy_lock must be held */
898 static void happy_meal_tx_reset(struct happy_meal *hp, unsigned long bregs)
899 {
900 int tries = TX_RESET_TRIES;
901
902 HMD(("happy_meal_tx_reset: reset, "));
903
904 /* Would you like to try our SMCC Delux? */
905 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
906 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
907 udelay(20);
908
909 /* Lettuce, tomato, buggy hardware (no extra charge)? */
910 if (!tries)
911 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
912
913 /* Take care. */
914 HMD(("done\n"));
915 }
916
917 /* hp->happy_lock must be held */
918 static void happy_meal_rx_reset(struct happy_meal *hp, unsigned long bregs)
919 {
920 int tries = RX_RESET_TRIES;
921
922 HMD(("happy_meal_rx_reset: reset, "));
923
924 /* We have a special on GNU/Viking hardware bugs today. */
925 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
926 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
927 udelay(20);
928
929 /* Will that be all? */
930 if (!tries)
931 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
932
933 /* Don't forget your vik_1137125_wa. Have a nice day. */
934 HMD(("done\n"));
935 }
936
937 #define STOP_TRIES 16
938
939 /* hp->happy_lock must be held */
940 static void happy_meal_stop(struct happy_meal *hp, unsigned long gregs)
941 {
942 int tries = STOP_TRIES;
943
944 HMD(("happy_meal_stop: reset, "));
945
946 /* We're consolidating our STB products, it's your lucky day. */
947 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
948 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
949 udelay(20);
950
951 /* Come back next week when we are "Sun Microelectronics". */
952 if (!tries)
953 printk(KERN_ERR "happy meal: Fry guys.");
954
955 /* Remember: "Different name, same old buggy as shit hardware." */
956 HMD(("done\n"));
957 }
958
959 /* hp->happy_lock must be held */
960 static void happy_meal_get_counters(struct happy_meal *hp, unsigned long bregs)
961 {
962 struct net_device_stats *stats = &hp->net_stats;
963
964 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
965 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
966
967 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
968 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
969
970 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
971 hme_write32(hp, bregs + BMAC_GLECTR, 0);
972
973 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
974
975 stats->collisions +=
976 (hme_read32(hp, bregs + BMAC_EXCTR) +
977 hme_read32(hp, bregs + BMAC_LTCTR));
978 hme_write32(hp, bregs + BMAC_EXCTR, 0);
979 hme_write32(hp, bregs + BMAC_LTCTR, 0);
980 }
981
982 /* hp->happy_lock must be held */
983 static void happy_meal_poll_stop(struct happy_meal *hp, unsigned long tregs)
984 {
985 ASD(("happy_meal_poll_stop: "));
986
987 /* If polling disabled or not polling already, nothing to do. */
988 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
989 (HFLAG_POLLENABLE | HFLAG_POLL)) {
990 HMD(("not polling, return\n"));
991 return;
992 }
993
994 /* Shut up the MIF. */
995 ASD(("were polling, mif ints off, "));
996 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
997
998 /* Turn off polling. */
999 ASD(("polling off, "));
1000 hme_write32(hp, tregs + TCVR_CFG,
1001 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
1002
1003 /* We are no longer polling. */
1004 hp->happy_flags &= ~(HFLAG_POLL);
1005
1006 /* Let the bits set. */
1007 udelay(200);
1008 ASD(("done\n"));
1009 }
1010
1011 /* Only Sun can take such nice parts and fuck up the programming interface
1012 * like this. Good job guys...
1013 */
1014 #define TCVR_RESET_TRIES 16 /* It should reset quickly */
1015 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
1016
1017 /* hp->happy_lock must be held */
1018 static int happy_meal_tcvr_reset(struct happy_meal *hp, unsigned long tregs)
1019 {
1020 u32 tconfig;
1021 int result, tries = TCVR_RESET_TRIES;
1022
1023 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1024 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1025 if (hp->tcvr_type == external) {
1026 ASD(("external<"));
1027 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1028 hp->tcvr_type = internal;
1029 hp->paddr = TCV_PADDR_ITX;
1030 ASD(("ISOLATE,"));
1031 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1032 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1033 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1034 if (result == TCVR_FAILURE) {
1035 ASD(("phyread_fail>\n"));
1036 return -1;
1037 }
1038 ASD(("phyread_ok,PSELECT>"));
1039 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1040 hp->tcvr_type = external;
1041 hp->paddr = TCV_PADDR_ETX;
1042 } else {
1043 if (tconfig & TCV_CFG_MDIO1) {
1044 ASD(("internal<PSELECT,"));
1045 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1046 ASD(("ISOLATE,"));
1047 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1048 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1049 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1050 if (result == TCVR_FAILURE) {
1051 ASD(("phyread_fail>\n"));
1052 return -1;
1053 }
1054 ASD(("phyread_ok,~PSELECT>"));
1055 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1056 hp->tcvr_type = internal;
1057 hp->paddr = TCV_PADDR_ITX;
1058 }
1059 }
1060
1061 ASD(("BMCR_RESET "));
1062 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1063
1064 while (--tries) {
1065 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1066 if (result == TCVR_FAILURE)
1067 return -1;
1068 hp->sw_bmcr = result;
1069 if (!(result & BMCR_RESET))
1070 break;
1071 udelay(20);
1072 }
1073 if (!tries) {
1074 ASD(("BMCR RESET FAILED!\n"));
1075 return -1;
1076 }
1077 ASD(("RESET_OK\n"));
1078
1079 /* Get fresh copies of the PHY registers. */
1080 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1081 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1082 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1083 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1084
1085 ASD(("UNISOLATE"));
1086 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1087 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1088
1089 tries = TCVR_UNISOLATE_TRIES;
1090 while (--tries) {
1091 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1092 if (result == TCVR_FAILURE)
1093 return -1;
1094 if (!(result & BMCR_ISOLATE))
1095 break;
1096 udelay(20);
1097 }
1098 if (!tries) {
1099 ASD((" FAILED!\n"));
1100 return -1;
1101 }
1102 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1103 if (!is_lucent_phy(hp)) {
1104 result = happy_meal_tcvr_read(hp, tregs,
1105 DP83840_CSCONFIG);
1106 happy_meal_tcvr_write(hp, tregs,
1107 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1108 }
1109 return 0;
1110 }
1111
1112 /* Figure out whether we have an internal or external transceiver.
1113 *
1114 * hp->happy_lock must be held
1115 */
1116 static void happy_meal_transceiver_check(struct happy_meal *hp, unsigned long tregs)
1117 {
1118 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1119
1120 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1121 if (hp->happy_flags & HFLAG_POLL) {
1122 /* If we are polling, we must stop to get the transceiver type. */
1123 ASD(("<polling> "));
1124 if (hp->tcvr_type == internal) {
1125 if (tconfig & TCV_CFG_MDIO1) {
1126 ASD(("<internal> <poll stop> "));
1127 happy_meal_poll_stop(hp, tregs);
1128 hp->paddr = TCV_PADDR_ETX;
1129 hp->tcvr_type = external;
1130 ASD(("<external>\n"));
1131 tconfig &= ~(TCV_CFG_PENABLE);
1132 tconfig |= TCV_CFG_PSELECT;
1133 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1134 }
1135 } else {
1136 if (hp->tcvr_type == external) {
1137 ASD(("<external> "));
1138 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1139 ASD(("<poll stop> "));
1140 happy_meal_poll_stop(hp, tregs);
1141 hp->paddr = TCV_PADDR_ITX;
1142 hp->tcvr_type = internal;
1143 ASD(("<internal>\n"));
1144 hme_write32(hp, tregs + TCVR_CFG,
1145 hme_read32(hp, tregs + TCVR_CFG) &
1146 ~(TCV_CFG_PSELECT));
1147 }
1148 ASD(("\n"));
1149 } else {
1150 ASD(("<none>\n"));
1151 }
1152 }
1153 } else {
1154 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1155
1156 /* Else we can just work off of the MDIO bits. */
1157 ASD(("<not polling> "));
1158 if (reread & TCV_CFG_MDIO1) {
1159 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1160 hp->paddr = TCV_PADDR_ETX;
1161 hp->tcvr_type = external;
1162 ASD(("<external>\n"));
1163 } else {
1164 if (reread & TCV_CFG_MDIO0) {
1165 hme_write32(hp, tregs + TCVR_CFG,
1166 tconfig & ~(TCV_CFG_PSELECT));
1167 hp->paddr = TCV_PADDR_ITX;
1168 hp->tcvr_type = internal;
1169 ASD(("<internal>\n"));
1170 } else {
1171 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1172 hp->tcvr_type = none; /* Grrr... */
1173 ASD(("<none>\n"));
1174 }
1175 }
1176 }
1177 }
1178
1179 /* The receive ring buffers are a bit tricky to get right. Here goes...
1180 *
1181 * The buffers we dma into must be 64 byte aligned. So we use a special
1182 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1183 * we really need.
1184 *
1185 * We use skb_reserve() to align the data block we get in the skb. We
1186 * also program the etxregs->cfg register to use an offset of 2. This
1187 * imperical constant plus the ethernet header size will always leave
1188 * us with a nicely aligned ip header once we pass things up to the
1189 * protocol layers.
1190 *
1191 * The numbers work out to:
1192 *
1193 * Max ethernet frame size 1518
1194 * Ethernet header size 14
1195 * Happy Meal base offset 2
1196 *
1197 * Say a skb data area is at 0xf001b010, and its size alloced is
1198 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1199 *
1200 * First our alloc_skb() routine aligns the data base to a 64 byte
1201 * boundary. We now have 0xf001b040 as our skb data address. We
1202 * plug this into the receive descriptor address.
1203 *
1204 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1205 * So now the data we will end up looking at starts at 0xf001b042. When
1206 * the packet arrives, we will check out the size received and subtract
1207 * this from the skb->length. Then we just pass the packet up to the
1208 * protocols as is, and allocate a new skb to replace this slot we have
1209 * just received from.
1210 *
1211 * The ethernet layer will strip the ether header from the front of the
1212 * skb we just sent to it, this leaves us with the ip header sitting
1213 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1214 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1215 * bit checksum is obtained from the low bits of the receive descriptor
1216 * flags, thus:
1217 *
1218 * skb->csum = rxd->rx_flags & 0xffff;
1219 * skb->ip_summed = CHECKSUM_HW;
1220 *
1221 * before sending off the skb to the protocols, and we are good as gold.
1222 */
1223 static void happy_meal_clean_rings(struct happy_meal *hp)
1224 {
1225 int i;
1226
1227 for (i = 0; i < RX_RING_SIZE; i++) {
1228 if (hp->rx_skbs[i] != NULL) {
1229 struct sk_buff *skb = hp->rx_skbs[i];
1230 struct happy_meal_rxd *rxd;
1231 u32 dma_addr;
1232
1233 rxd = &hp->happy_block->happy_meal_rxd[i];
1234 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1235 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1236 dev_kfree_skb_any(skb);
1237 hp->rx_skbs[i] = NULL;
1238 }
1239 }
1240
1241 for (i = 0; i < TX_RING_SIZE; i++) {
1242 if (hp->tx_skbs[i] != NULL) {
1243 struct sk_buff *skb = hp->tx_skbs[i];
1244 struct happy_meal_txd *txd;
1245 u32 dma_addr;
1246 int frag;
1247
1248 hp->tx_skbs[i] = NULL;
1249
1250 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1251 txd = &hp->happy_block->happy_meal_txd[i];
1252 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1253 hme_dma_unmap(hp, dma_addr,
1254 (hme_read_desc32(hp, &txd->tx_flags)
1255 & TXFLAG_SIZE),
1256 DMA_TODEVICE);
1257
1258 if (frag != skb_shinfo(skb)->nr_frags)
1259 i++;
1260 }
1261
1262 dev_kfree_skb_any(skb);
1263 }
1264 }
1265 }
1266
1267 /* hp->happy_lock must be held */
1268 static void happy_meal_init_rings(struct happy_meal *hp)
1269 {
1270 struct hmeal_init_block *hb = hp->happy_block;
1271 struct net_device *dev = hp->dev;
1272 int i;
1273
1274 HMD(("happy_meal_init_rings: counters to zero, "));
1275 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1276
1277 /* Free any skippy bufs left around in the rings. */
1278 HMD(("clean, "));
1279 happy_meal_clean_rings(hp);
1280
1281 /* Now get new skippy bufs for the receive ring. */
1282 HMD(("init rxring, "));
1283 for (i = 0; i < RX_RING_SIZE; i++) {
1284 struct sk_buff *skb;
1285
1286 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1287 if (!skb) {
1288 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1289 continue;
1290 }
1291 hp->rx_skbs[i] = skb;
1292 skb->dev = dev;
1293
1294 /* Because we reserve afterwards. */
1295 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1296 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1297 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1298 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1299 skb_reserve(skb, RX_OFFSET);
1300 }
1301
1302 HMD(("init txring, "));
1303 for (i = 0; i < TX_RING_SIZE; i++)
1304 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1305
1306 HMD(("done\n"));
1307 }
1308
1309 /* hp->happy_lock must be held */
1310 static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1311 unsigned long tregs,
1312 struct ethtool_cmd *ep)
1313 {
1314 int timeout;
1315
1316 /* Read all of the registers we are interested in now. */
1317 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1318 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1319 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1320 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1321
1322 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1323
1324 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1325 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1326 /* Advertise everything we can support. */
1327 if (hp->sw_bmsr & BMSR_10HALF)
1328 hp->sw_advertise |= (ADVERTISE_10HALF);
1329 else
1330 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1331
1332 if (hp->sw_bmsr & BMSR_10FULL)
1333 hp->sw_advertise |= (ADVERTISE_10FULL);
1334 else
1335 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1336 if (hp->sw_bmsr & BMSR_100HALF)
1337 hp->sw_advertise |= (ADVERTISE_100HALF);
1338 else
1339 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1340 if (hp->sw_bmsr & BMSR_100FULL)
1341 hp->sw_advertise |= (ADVERTISE_100FULL);
1342 else
1343 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1344 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1345
1346 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1347 * XXX and this is because the DP83840 does not support it, changes
1348 * XXX would need to be made to the tx/rx logic in the driver as well
1349 * XXX so I completely skip checking for it in the BMSR for now.
1350 */
1351
1352 #ifdef AUTO_SWITCH_DEBUG
1353 ASD(("%s: Advertising [ ", hp->dev->name));
1354 if (hp->sw_advertise & ADVERTISE_10HALF)
1355 ASD(("10H "));
1356 if (hp->sw_advertise & ADVERTISE_10FULL)
1357 ASD(("10F "));
1358 if (hp->sw_advertise & ADVERTISE_100HALF)
1359 ASD(("100H "));
1360 if (hp->sw_advertise & ADVERTISE_100FULL)
1361 ASD(("100F "));
1362 #endif
1363
1364 /* Enable Auto-Negotiation, this is usually on already... */
1365 hp->sw_bmcr |= BMCR_ANENABLE;
1366 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1367
1368 /* Restart it to make sure it is going. */
1369 hp->sw_bmcr |= BMCR_ANRESTART;
1370 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1371
1372 /* BMCR_ANRESTART self clears when the process has begun. */
1373
1374 timeout = 64; /* More than enough. */
1375 while (--timeout) {
1376 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1377 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1378 break; /* got it. */
1379 udelay(10);
1380 }
1381 if (!timeout) {
1382 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1383 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1384 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1385 hp->dev->name);
1386 goto force_link;
1387 } else {
1388 hp->timer_state = arbwait;
1389 }
1390 } else {
1391 force_link:
1392 /* Force the link up, trying first a particular mode.
1393 * Either we are here at the request of ethtool or
1394 * because the Happy Meal would not start to autoneg.
1395 */
1396
1397 /* Disable auto-negotiation in BMCR, enable the duplex and
1398 * speed setting, init the timer state machine, and fire it off.
1399 */
1400 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1401 hp->sw_bmcr = BMCR_SPEED100;
1402 } else {
1403 if (ep->speed == SPEED_100)
1404 hp->sw_bmcr = BMCR_SPEED100;
1405 else
1406 hp->sw_bmcr = 0;
1407 if (ep->duplex == DUPLEX_FULL)
1408 hp->sw_bmcr |= BMCR_FULLDPLX;
1409 }
1410 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1411
1412 if (!is_lucent_phy(hp)) {
1413 /* OK, seems we need do disable the transceiver for the first
1414 * tick to make sure we get an accurate link state at the
1415 * second tick.
1416 */
1417 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1418 DP83840_CSCONFIG);
1419 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1420 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1421 hp->sw_csconfig);
1422 }
1423 hp->timer_state = ltrywait;
1424 }
1425
1426 hp->timer_ticks = 0;
1427 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1428 hp->happy_timer.data = (unsigned long) hp;
1429 hp->happy_timer.function = &happy_meal_timer;
1430 add_timer(&hp->happy_timer);
1431 }
1432
1433 /* hp->happy_lock must be held */
1434 static int happy_meal_init(struct happy_meal *hp)
1435 {
1436 unsigned long gregs = hp->gregs;
1437 unsigned long etxregs = hp->etxregs;
1438 unsigned long erxregs = hp->erxregs;
1439 unsigned long bregs = hp->bigmacregs;
1440 unsigned long tregs = hp->tcvregs;
1441 u32 regtmp, rxcfg;
1442 unsigned char *e = &hp->dev->dev_addr[0];
1443
1444 /* If auto-negotiation timer is running, kill it. */
1445 del_timer(&hp->happy_timer);
1446
1447 HMD(("happy_meal_init: happy_flags[%08x] ",
1448 hp->happy_flags));
1449 if (!(hp->happy_flags & HFLAG_INIT)) {
1450 HMD(("set HFLAG_INIT, "));
1451 hp->happy_flags |= HFLAG_INIT;
1452 happy_meal_get_counters(hp, bregs);
1453 }
1454
1455 /* Stop polling. */
1456 HMD(("to happy_meal_poll_stop\n"));
1457 happy_meal_poll_stop(hp, tregs);
1458
1459 /* Stop transmitter and receiver. */
1460 HMD(("happy_meal_init: to happy_meal_stop\n"));
1461 happy_meal_stop(hp, gregs);
1462
1463 /* Alloc and reset the tx/rx descriptor chains. */
1464 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1465 happy_meal_init_rings(hp);
1466
1467 /* Shut up the MIF. */
1468 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1469 hme_read32(hp, tregs + TCVR_IMASK)));
1470 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1471
1472 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1473 if (hp->happy_flags & HFLAG_FENABLE) {
1474 HMD(("use frame old[%08x], ",
1475 hme_read32(hp, tregs + TCVR_CFG)));
1476 hme_write32(hp, tregs + TCVR_CFG,
1477 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1478 } else {
1479 HMD(("use bitbang old[%08x], ",
1480 hme_read32(hp, tregs + TCVR_CFG)));
1481 hme_write32(hp, tregs + TCVR_CFG,
1482 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1483 }
1484
1485 /* Check the state of the transceiver. */
1486 HMD(("to happy_meal_transceiver_check\n"));
1487 happy_meal_transceiver_check(hp, tregs);
1488
1489 /* Put the Big Mac into a sane state. */
1490 HMD(("happy_meal_init: "));
1491 switch(hp->tcvr_type) {
1492 case none:
1493 /* Cannot operate if we don't know the transceiver type! */
1494 HMD(("AAIEEE no transceiver type, EAGAIN"));
1495 return -EAGAIN;
1496
1497 case internal:
1498 /* Using the MII buffers. */
1499 HMD(("internal, using MII, "));
1500 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1501 break;
1502
1503 case external:
1504 /* Not using the MII, disable it. */
1505 HMD(("external, disable MII, "));
1506 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1507 break;
1508 };
1509
1510 if (happy_meal_tcvr_reset(hp, tregs))
1511 return -EAGAIN;
1512
1513 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1514 HMD(("tx/rx reset, "));
1515 happy_meal_tx_reset(hp, bregs);
1516 happy_meal_rx_reset(hp, bregs);
1517
1518 /* Set jam size and inter-packet gaps to reasonable defaults. */
1519 HMD(("jsize/ipg1/ipg2, "));
1520 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1521 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1522 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1523
1524 /* Load up the MAC address and random seed. */
1525 HMD(("rseed/macaddr, "));
1526
1527 /* The docs recommend to use the 10LSB of our MAC here. */
1528 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1529
1530 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1531 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1532 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1533
1534 HMD(("htable, "));
1535 if ((hp->dev->flags & IFF_ALLMULTI) ||
1536 (hp->dev->mc_count > 64)) {
1537 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1538 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1539 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1540 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1541 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1542 u16 hash_table[4];
1543 struct dev_mc_list *dmi = hp->dev->mc_list;
1544 char *addrs;
1545 int i;
1546 u32 crc;
1547
1548 for (i = 0; i < 4; i++)
1549 hash_table[i] = 0;
1550
1551 for (i = 0; i < hp->dev->mc_count; i++) {
1552 addrs = dmi->dmi_addr;
1553 dmi = dmi->next;
1554
1555 if (!(*addrs & 1))
1556 continue;
1557
1558 crc = ether_crc_le(6, addrs);
1559 crc >>= 26;
1560 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1561 }
1562 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1563 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1564 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1565 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1566 } else {
1567 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1568 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1569 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1570 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1571 }
1572
1573 /* Set the RX and TX ring ptrs. */
1574 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1575 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1576 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1577 hme_write32(hp, erxregs + ERX_RING,
1578 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1579 hme_write32(hp, etxregs + ETX_RING,
1580 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1581
1582 /* Parity issues in the ERX unit of some HME revisions can cause some
1583 * registers to not be written unless their parity is even. Detect such
1584 * lost writes and simply rewrite with a low bit set (which will be ignored
1585 * since the rxring needs to be 2K aligned).
1586 */
1587 if (hme_read32(hp, erxregs + ERX_RING) !=
1588 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1589 hme_write32(hp, erxregs + ERX_RING,
1590 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1591 | 0x4);
1592
1593 /* Set the supported burst sizes. */
1594 HMD(("happy_meal_init: old[%08x] bursts<",
1595 hme_read32(hp, gregs + GREG_CFG)));
1596
1597 #ifndef __sparc__
1598 /* It is always PCI and can handle 64byte bursts. */
1599 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1600 #else
1601 if ((hp->happy_bursts & DMA_BURST64) &&
1602 ((hp->happy_flags & HFLAG_PCI) != 0
1603 #ifdef CONFIG_SBUS
1604 || sbus_can_burst64(hp->happy_dev)
1605 #endif
1606 || 0)) {
1607 u32 gcfg = GREG_CFG_BURST64;
1608
1609 /* I have no idea if I should set the extended
1610 * transfer mode bit for Cheerio, so for now I
1611 * do not. -DaveM
1612 */
1613 #ifdef CONFIG_SBUS
1614 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1615 sbus_can_dma_64bit(hp->happy_dev)) {
1616 sbus_set_sbus64(hp->happy_dev,
1617 hp->happy_bursts);
1618 gcfg |= GREG_CFG_64BIT;
1619 }
1620 #endif
1621
1622 HMD(("64>"));
1623 hme_write32(hp, gregs + GREG_CFG, gcfg);
1624 } else if (hp->happy_bursts & DMA_BURST32) {
1625 HMD(("32>"));
1626 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1627 } else if (hp->happy_bursts & DMA_BURST16) {
1628 HMD(("16>"));
1629 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1630 } else {
1631 HMD(("XXX>"));
1632 hme_write32(hp, gregs + GREG_CFG, 0);
1633 }
1634 #endif /* __sparc__ */
1635
1636 /* Turn off interrupts we do not want to hear. */
1637 HMD((", enable global interrupts, "));
1638 hme_write32(hp, gregs + GREG_IMASK,
1639 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1640 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1641
1642 /* Set the transmit ring buffer size. */
1643 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1644 hme_read32(hp, etxregs + ETX_RSIZE)));
1645 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1646
1647 /* Enable transmitter DVMA. */
1648 HMD(("tx dma enable old[%08x], ",
1649 hme_read32(hp, etxregs + ETX_CFG)));
1650 hme_write32(hp, etxregs + ETX_CFG,
1651 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1652
1653 /* This chip really rots, for the receiver sometimes when you
1654 * write to its control registers not all the bits get there
1655 * properly. I cannot think of a sane way to provide complete
1656 * coverage for this hardware bug yet.
1657 */
1658 HMD(("erx regs bug old[%08x]\n",
1659 hme_read32(hp, erxregs + ERX_CFG)));
1660 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1661 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1662 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1663 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1664 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1665 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1666 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1667 /* XXX Should return failure here... */
1668 }
1669
1670 /* Enable Big Mac hash table filter. */
1671 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1672 hme_read32(hp, bregs + BMAC_RXCFG)));
1673 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1674 if (hp->dev->flags & IFF_PROMISC)
1675 rxcfg |= BIGMAC_RXCFG_PMISC;
1676 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1677
1678 /* Let the bits settle in the chip. */
1679 udelay(10);
1680
1681 /* Ok, configure the Big Mac transmitter. */
1682 HMD(("BIGMAC init, "));
1683 regtmp = 0;
1684 if (hp->happy_flags & HFLAG_FULL)
1685 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1686
1687 /* Don't turn on the "don't give up" bit for now. It could cause hme
1688 * to deadlock with the PHY if a Jabber occurs.
1689 */
1690 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1691
1692 /* Give up after 16 TX attempts. */
1693 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1694
1695 /* Enable the output drivers no matter what. */
1696 regtmp = BIGMAC_XCFG_ODENABLE;
1697
1698 /* If card can do lance mode, enable it. */
1699 if (hp->happy_flags & HFLAG_LANCE)
1700 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1701
1702 /* Disable the MII buffers if using external transceiver. */
1703 if (hp->tcvr_type == external)
1704 regtmp |= BIGMAC_XCFG_MIIDISAB;
1705
1706 HMD(("XIF config old[%08x], ",
1707 hme_read32(hp, bregs + BMAC_XIFCFG)));
1708 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1709
1710 /* Start things up. */
1711 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1712 hme_read32(hp, bregs + BMAC_TXCFG),
1713 hme_read32(hp, bregs + BMAC_RXCFG)));
1714 hme_write32(hp, bregs + BMAC_TXCFG,
1715 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1716 hme_write32(hp, bregs + BMAC_RXCFG,
1717 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1718
1719 /* Get the autonegotiation started, and the watch timer ticking. */
1720 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1721
1722 /* Success. */
1723 return 0;
1724 }
1725
1726 /* hp->happy_lock must be held */
1727 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1728 {
1729 unsigned long tregs = hp->tcvregs;
1730 unsigned long bregs = hp->bigmacregs;
1731 unsigned long gregs = hp->gregs;
1732
1733 happy_meal_stop(hp, gregs);
1734 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1735 if (hp->happy_flags & HFLAG_FENABLE)
1736 hme_write32(hp, tregs + TCVR_CFG,
1737 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1738 else
1739 hme_write32(hp, tregs + TCVR_CFG,
1740 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1741 happy_meal_transceiver_check(hp, tregs);
1742 switch(hp->tcvr_type) {
1743 case none:
1744 return;
1745 case internal:
1746 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1747 break;
1748 case external:
1749 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1750 break;
1751 };
1752 if (happy_meal_tcvr_reset(hp, tregs))
1753 return;
1754
1755 /* Latch PHY registers as of now. */
1756 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1757 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1758
1759 /* Advertise everything we can support. */
1760 if (hp->sw_bmsr & BMSR_10HALF)
1761 hp->sw_advertise |= (ADVERTISE_10HALF);
1762 else
1763 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1764
1765 if (hp->sw_bmsr & BMSR_10FULL)
1766 hp->sw_advertise |= (ADVERTISE_10FULL);
1767 else
1768 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1769 if (hp->sw_bmsr & BMSR_100HALF)
1770 hp->sw_advertise |= (ADVERTISE_100HALF);
1771 else
1772 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1773 if (hp->sw_bmsr & BMSR_100FULL)
1774 hp->sw_advertise |= (ADVERTISE_100FULL);
1775 else
1776 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1777
1778 /* Update the PHY advertisement register. */
1779 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1780 }
1781
1782 /* Once status is latched (by happy_meal_interrupt) it is cleared by
1783 * the hardware, so we cannot re-read it and get a correct value.
1784 *
1785 * hp->happy_lock must be held
1786 */
1787 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1788 {
1789 int reset = 0;
1790
1791 /* Only print messages for non-counter related interrupts. */
1792 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1793 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1794 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1795 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1796 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1797 GREG_STAT_SLVPERR))
1798 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1799 hp->dev->name, status);
1800
1801 if (status & GREG_STAT_RFIFOVF) {
1802 /* Receive FIFO overflow is harmless and the hardware will take
1803 care of it, just some packets are lost. Who cares. */
1804 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1805 }
1806
1807 if (status & GREG_STAT_STSTERR) {
1808 /* BigMAC SQE link test failed. */
1809 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1810 reset = 1;
1811 }
1812
1813 if (status & GREG_STAT_TFIFO_UND) {
1814 /* Transmit FIFO underrun, again DMA error likely. */
1815 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1816 hp->dev->name);
1817 reset = 1;
1818 }
1819
1820 if (status & GREG_STAT_MAXPKTERR) {
1821 /* Driver error, tried to transmit something larger
1822 * than ethernet max mtu.
1823 */
1824 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1825 reset = 1;
1826 }
1827
1828 if (status & GREG_STAT_NORXD) {
1829 /* This is harmless, it just means the system is
1830 * quite loaded and the incoming packet rate was
1831 * faster than the interrupt handler could keep up
1832 * with.
1833 */
1834 printk(KERN_INFO "%s: Happy Meal out of receive "
1835 "descriptors, packet dropped.\n",
1836 hp->dev->name);
1837 }
1838
1839 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1840 /* All sorts of DMA receive errors. */
1841 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1842 if (status & GREG_STAT_RXERR)
1843 printk("GenericError ");
1844 if (status & GREG_STAT_RXPERR)
1845 printk("ParityError ");
1846 if (status & GREG_STAT_RXTERR)
1847 printk("RxTagBotch ");
1848 printk("]\n");
1849 reset = 1;
1850 }
1851
1852 if (status & GREG_STAT_EOPERR) {
1853 /* Driver bug, didn't set EOP bit in tx descriptor given
1854 * to the happy meal.
1855 */
1856 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1857 hp->dev->name);
1858 reset = 1;
1859 }
1860
1861 if (status & GREG_STAT_MIFIRQ) {
1862 /* MIF signalled an interrupt, were we polling it? */
1863 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1864 }
1865
1866 if (status &
1867 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1868 /* All sorts of transmit DMA errors. */
1869 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1870 if (status & GREG_STAT_TXEACK)
1871 printk("GenericError ");
1872 if (status & GREG_STAT_TXLERR)
1873 printk("LateError ");
1874 if (status & GREG_STAT_TXPERR)
1875 printk("ParityErro ");
1876 if (status & GREG_STAT_TXTERR)
1877 printk("TagBotch ");
1878 printk("]\n");
1879 reset = 1;
1880 }
1881
1882 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1883 /* Bus or parity error when cpu accessed happy meal registers
1884 * or it's internal FIFO's. Should never see this.
1885 */
1886 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1887 hp->dev->name,
1888 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1889 reset = 1;
1890 }
1891
1892 if (reset) {
1893 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1894 happy_meal_init(hp);
1895 return 1;
1896 }
1897 return 0;
1898 }
1899
1900 /* hp->happy_lock must be held */
1901 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1902 {
1903 unsigned long tregs = hp->tcvregs;
1904
1905 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1906 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1907 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1908
1909 /* Use the fastest transmission protocol possible. */
1910 if (hp->sw_lpa & LPA_100FULL) {
1911 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1912 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1913 } else if (hp->sw_lpa & LPA_100HALF) {
1914 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1915 hp->sw_bmcr |= BMCR_SPEED100;
1916 } else if (hp->sw_lpa & LPA_10FULL) {
1917 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1918 hp->sw_bmcr |= BMCR_FULLDPLX;
1919 } else {
1920 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1921 }
1922 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1923
1924 /* Finally stop polling and shut up the MIF. */
1925 happy_meal_poll_stop(hp, tregs);
1926 }
1927
1928 #ifdef TXDEBUG
1929 #define TXD(x) printk x
1930 #else
1931 #define TXD(x)
1932 #endif
1933
1934 /* hp->happy_lock must be held */
1935 static void happy_meal_tx(struct happy_meal *hp)
1936 {
1937 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1938 struct happy_meal_txd *this;
1939 struct net_device *dev = hp->dev;
1940 int elem;
1941
1942 elem = hp->tx_old;
1943 TXD(("TX<"));
1944 while (elem != hp->tx_new) {
1945 struct sk_buff *skb;
1946 u32 flags, dma_addr, dma_len;
1947 int frag;
1948
1949 TXD(("[%d]", elem));
1950 this = &txbase[elem];
1951 flags = hme_read_desc32(hp, &this->tx_flags);
1952 if (flags & TXFLAG_OWN)
1953 break;
1954 skb = hp->tx_skbs[elem];
1955 if (skb_shinfo(skb)->nr_frags) {
1956 int last;
1957
1958 last = elem + skb_shinfo(skb)->nr_frags;
1959 last &= (TX_RING_SIZE - 1);
1960 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1961 if (flags & TXFLAG_OWN)
1962 break;
1963 }
1964 hp->tx_skbs[elem] = NULL;
1965 hp->net_stats.tx_bytes += skb->len;
1966
1967 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1968 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1969 dma_len = hme_read_desc32(hp, &this->tx_flags);
1970
1971 dma_len &= TXFLAG_SIZE;
1972 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE);
1973
1974 elem = NEXT_TX(elem);
1975 this = &txbase[elem];
1976 }
1977
1978 dev_kfree_skb_irq(skb);
1979 hp->net_stats.tx_packets++;
1980 }
1981 hp->tx_old = elem;
1982 TXD((">"));
1983
1984 if (netif_queue_stopped(dev) &&
1985 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1986 netif_wake_queue(dev);
1987 }
1988
1989 #ifdef RXDEBUG
1990 #define RXD(x) printk x
1991 #else
1992 #define RXD(x)
1993 #endif
1994
1995 /* Originally I used to handle the allocation failure by just giving back just
1996 * that one ring buffer to the happy meal. Problem is that usually when that
1997 * condition is triggered, the happy meal expects you to do something reasonable
1998 * with all of the packets it has DMA'd in. So now I just drop the entire
1999 * ring when we cannot get a new skb and give them all back to the happy meal,
2000 * maybe things will be "happier" now.
2001 *
2002 * hp->happy_lock must be held
2003 */
2004 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
2005 {
2006 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
2007 struct happy_meal_rxd *this;
2008 int elem = hp->rx_new, drops = 0;
2009 u32 flags;
2010
2011 RXD(("RX<"));
2012 this = &rxbase[elem];
2013 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2014 struct sk_buff *skb;
2015 int len = flags >> 16;
2016 u16 csum = flags & RXFLAG_CSUM;
2017 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2018
2019 RXD(("[%d ", elem));
2020
2021 /* Check for errors. */
2022 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2023 RXD(("ERR(%08x)]", flags));
2024 hp->net_stats.rx_errors++;
2025 if (len < ETH_ZLEN)
2026 hp->net_stats.rx_length_errors++;
2027 if (len & (RXFLAG_OVERFLOW >> 16)) {
2028 hp->net_stats.rx_over_errors++;
2029 hp->net_stats.rx_fifo_errors++;
2030 }
2031
2032 /* Return it to the Happy meal. */
2033 drop_it:
2034 hp->net_stats.rx_dropped++;
2035 hme_write_rxd(hp, this,
2036 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2037 dma_addr);
2038 goto next;
2039 }
2040 skb = hp->rx_skbs[elem];
2041 if (len > RX_COPY_THRESHOLD) {
2042 struct sk_buff *new_skb;
2043
2044 /* Now refill the entry, if we can. */
2045 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2046 if (new_skb == NULL) {
2047 drops++;
2048 goto drop_it;
2049 }
2050 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
2051 hp->rx_skbs[elem] = new_skb;
2052 new_skb->dev = dev;
2053 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
2054 hme_write_rxd(hp, this,
2055 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2056 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
2057 skb_reserve(new_skb, RX_OFFSET);
2058
2059 /* Trim the original skb for the netif. */
2060 skb_trim(skb, len);
2061 } else {
2062 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2063
2064 if (copy_skb == NULL) {
2065 drops++;
2066 goto drop_it;
2067 }
2068
2069 copy_skb->dev = dev;
2070 skb_reserve(copy_skb, 2);
2071 skb_put(copy_skb, len);
2072 hme_dma_sync(hp, dma_addr, len, DMA_FROMDEVICE);
2073 memcpy(copy_skb->data, skb->data, len);
2074
2075 /* Reuse original ring buffer. */
2076 hme_write_rxd(hp, this,
2077 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2078 dma_addr);
2079
2080 skb = copy_skb;
2081 }
2082
2083 /* This card is _fucking_ hot... */
2084 skb->csum = ntohs(csum ^ 0xffff);
2085 skb->ip_summed = CHECKSUM_HW;
2086
2087 RXD(("len=%d csum=%4x]", len, csum));
2088 skb->protocol = eth_type_trans(skb, dev);
2089 netif_rx(skb);
2090
2091 dev->last_rx = jiffies;
2092 hp->net_stats.rx_packets++;
2093 hp->net_stats.rx_bytes += len;
2094 next:
2095 elem = NEXT_RX(elem);
2096 this = &rxbase[elem];
2097 }
2098 hp->rx_new = elem;
2099 if (drops)
2100 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2101 RXD((">"));
2102 }
2103
2104 static irqreturn_t happy_meal_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2105 {
2106 struct net_device *dev = (struct net_device *) dev_id;
2107 struct happy_meal *hp = dev->priv;
2108 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2109
2110 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2111
2112 spin_lock(&hp->happy_lock);
2113
2114 if (happy_status & GREG_STAT_ERRORS) {
2115 HMD(("ERRORS "));
2116 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2117 goto out;
2118 }
2119
2120 if (happy_status & GREG_STAT_MIFIRQ) {
2121 HMD(("MIFIRQ "));
2122 happy_meal_mif_interrupt(hp);
2123 }
2124
2125 if (happy_status & GREG_STAT_TXALL) {
2126 HMD(("TXALL "));
2127 happy_meal_tx(hp);
2128 }
2129
2130 if (happy_status & GREG_STAT_RXTOHOST) {
2131 HMD(("RXTOHOST "));
2132 happy_meal_rx(hp, dev);
2133 }
2134
2135 HMD(("done\n"));
2136 out:
2137 spin_unlock(&hp->happy_lock);
2138
2139 return IRQ_HANDLED;
2140 }
2141
2142 #ifdef CONFIG_SBUS
2143 static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie, struct pt_regs *ptregs)
2144 {
2145 struct quattro *qp = (struct quattro *) cookie;
2146 int i;
2147
2148 for (i = 0; i < 4; i++) {
2149 struct net_device *dev = qp->happy_meals[i];
2150 struct happy_meal *hp = dev->priv;
2151 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2152
2153 HMD(("quattro_interrupt: status=%08x ", happy_status));
2154
2155 if (!(happy_status & (GREG_STAT_ERRORS |
2156 GREG_STAT_MIFIRQ |
2157 GREG_STAT_TXALL |
2158 GREG_STAT_RXTOHOST)))
2159 continue;
2160
2161 spin_lock(&hp->happy_lock);
2162
2163 if (happy_status & GREG_STAT_ERRORS) {
2164 HMD(("ERRORS "));
2165 if (happy_meal_is_not_so_happy(hp, happy_status))
2166 goto next;
2167 }
2168
2169 if (happy_status & GREG_STAT_MIFIRQ) {
2170 HMD(("MIFIRQ "));
2171 happy_meal_mif_interrupt(hp);
2172 }
2173
2174 if (happy_status & GREG_STAT_TXALL) {
2175 HMD(("TXALL "));
2176 happy_meal_tx(hp);
2177 }
2178
2179 if (happy_status & GREG_STAT_RXTOHOST) {
2180 HMD(("RXTOHOST "));
2181 happy_meal_rx(hp, dev);
2182 }
2183
2184 next:
2185 spin_unlock(&hp->happy_lock);
2186 }
2187 HMD(("done\n"));
2188
2189 return IRQ_HANDLED;
2190 }
2191 #endif
2192
2193 static int happy_meal_open(struct net_device *dev)
2194 {
2195 struct happy_meal *hp = dev->priv;
2196 int res;
2197
2198 HMD(("happy_meal_open: "));
2199
2200 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2201 * into a single source which we register handling at probe time.
2202 */
2203 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2204 if (request_irq(dev->irq, &happy_meal_interrupt,
2205 SA_SHIRQ, dev->name, (void *)dev)) {
2206 HMD(("EAGAIN\n"));
2207 #ifdef __sparc__
2208 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %s to go.\n",
2209 __irq_itoa(dev->irq));
2210 #else
2211 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2212 dev->irq);
2213 #endif
2214
2215 return -EAGAIN;
2216 }
2217 }
2218
2219 HMD(("to happy_meal_init\n"));
2220
2221 spin_lock_irq(&hp->happy_lock);
2222 res = happy_meal_init(hp);
2223 spin_unlock_irq(&hp->happy_lock);
2224
2225 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2226 free_irq(dev->irq, dev);
2227 return res;
2228 }
2229
2230 static int happy_meal_close(struct net_device *dev)
2231 {
2232 struct happy_meal *hp = dev->priv;
2233
2234 spin_lock_irq(&hp->happy_lock);
2235 happy_meal_stop(hp, hp->gregs);
2236 happy_meal_clean_rings(hp);
2237
2238 /* If auto-negotiation timer is running, kill it. */
2239 del_timer(&hp->happy_timer);
2240
2241 spin_unlock_irq(&hp->happy_lock);
2242
2243 /* On Quattro QFE cards, all hme interrupts are concentrated
2244 * into a single source which we register handling at probe
2245 * time and never unregister.
2246 */
2247 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2248 free_irq(dev->irq, dev);
2249
2250 return 0;
2251 }
2252
2253 #ifdef SXDEBUG
2254 #define SXD(x) printk x
2255 #else
2256 #define SXD(x)
2257 #endif
2258
2259 static void happy_meal_tx_timeout(struct net_device *dev)
2260 {
2261 struct happy_meal *hp = dev->priv;
2262
2263 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2264 tx_dump_log();
2265 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2266 hme_read32(hp, hp->gregs + GREG_STAT),
2267 hme_read32(hp, hp->etxregs + ETX_CFG),
2268 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2269
2270 spin_lock_irq(&hp->happy_lock);
2271 happy_meal_init(hp);
2272 spin_unlock_irq(&hp->happy_lock);
2273
2274 netif_wake_queue(dev);
2275 }
2276
2277 static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2278 {
2279 struct happy_meal *hp = dev->priv;
2280 int entry;
2281 u32 tx_flags;
2282
2283 tx_flags = TXFLAG_OWN;
2284 if (skb->ip_summed == CHECKSUM_HW) {
2285 u32 csum_start_off, csum_stuff_off;
2286
2287 csum_start_off = (u32) (skb->h.raw - skb->data);
2288 csum_stuff_off = (u32) ((skb->h.raw + skb->csum) - skb->data);
2289
2290 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2291 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2292 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2293 }
2294
2295 spin_lock_irq(&hp->happy_lock);
2296
2297 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2298 netif_stop_queue(dev);
2299 spin_unlock_irq(&hp->happy_lock);
2300 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2301 dev->name);
2302 return 1;
2303 }
2304
2305 entry = hp->tx_new;
2306 SXD(("SX<l[%d]e[%d]>", len, entry));
2307 hp->tx_skbs[entry] = skb;
2308
2309 if (skb_shinfo(skb)->nr_frags == 0) {
2310 u32 mapping, len;
2311
2312 len = skb->len;
2313 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2314 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2315 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2316 (tx_flags | (len & TXFLAG_SIZE)),
2317 mapping);
2318 entry = NEXT_TX(entry);
2319 } else {
2320 u32 first_len, first_mapping;
2321 int frag, first_entry = entry;
2322
2323 /* We must give this initial chunk to the device last.
2324 * Otherwise we could race with the device.
2325 */
2326 first_len = skb_headlen(skb);
2327 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE);
2328 entry = NEXT_TX(entry);
2329
2330 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2331 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2332 u32 len, mapping, this_txflags;
2333
2334 len = this_frag->size;
2335 mapping = hme_dma_map(hp,
2336 ((void *) page_address(this_frag->page) +
2337 this_frag->page_offset),
2338 len, DMA_TODEVICE);
2339 this_txflags = tx_flags;
2340 if (frag == skb_shinfo(skb)->nr_frags - 1)
2341 this_txflags |= TXFLAG_EOP;
2342 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2343 (this_txflags | (len & TXFLAG_SIZE)),
2344 mapping);
2345 entry = NEXT_TX(entry);
2346 }
2347 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2348 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2349 first_mapping);
2350 }
2351
2352 hp->tx_new = entry;
2353
2354 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2355 netif_stop_queue(dev);
2356
2357 /* Get it going. */
2358 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2359
2360 spin_unlock_irq(&hp->happy_lock);
2361
2362 dev->trans_start = jiffies;
2363
2364 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2365 return 0;
2366 }
2367
2368 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2369 {
2370 struct happy_meal *hp = dev->priv;
2371
2372 spin_lock_irq(&hp->happy_lock);
2373 happy_meal_get_counters(hp, hp->bigmacregs);
2374 spin_unlock_irq(&hp->happy_lock);
2375
2376 return &hp->net_stats;
2377 }
2378
2379 static void happy_meal_set_multicast(struct net_device *dev)
2380 {
2381 struct happy_meal *hp = dev->priv;
2382 unsigned long bregs = hp->bigmacregs;
2383 struct dev_mc_list *dmi = dev->mc_list;
2384 char *addrs;
2385 int i;
2386 u32 crc;
2387
2388 spin_lock_irq(&hp->happy_lock);
2389
2390 netif_stop_queue(dev);
2391
2392 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2393 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2394 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2395 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2396 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2397 } else if (dev->flags & IFF_PROMISC) {
2398 hme_write32(hp, bregs + BMAC_RXCFG,
2399 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2400 } else {
2401 u16 hash_table[4];
2402
2403 for (i = 0; i < 4; i++)
2404 hash_table[i] = 0;
2405
2406 for (i = 0; i < dev->mc_count; i++) {
2407 addrs = dmi->dmi_addr;
2408 dmi = dmi->next;
2409
2410 if (!(*addrs & 1))
2411 continue;
2412
2413 crc = ether_crc_le(6, addrs);
2414 crc >>= 26;
2415 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2416 }
2417 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2418 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2419 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2420 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2421 }
2422
2423 netif_wake_queue(dev);
2424
2425 spin_unlock_irq(&hp->happy_lock);
2426 }
2427
2428 /* Ethtool support... */
2429 static int happy_meal_ioctl(struct net_device *dev,
2430 struct ifreq *rq, int cmd)
2431 {
2432 struct happy_meal *hp = dev->priv;
2433 struct ethtool_cmd *ep_user = (struct ethtool_cmd *) rq->ifr_data;
2434 struct ethtool_cmd ecmd;
2435
2436 if (cmd != SIOCETHTOOL)
2437 return -EOPNOTSUPP;
2438 if (copy_from_user(&ecmd, ep_user, sizeof(ecmd)))
2439 return -EFAULT;
2440
2441 if (ecmd.cmd == ETHTOOL_GSET) {
2442 ecmd.supported =
2443 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2444 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2445 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2446
2447 /* XXX hardcoded stuff for now */
2448 ecmd.port = PORT_TP; /* XXX no MII support */
2449 ecmd.transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2450 ecmd.phy_address = 0; /* XXX fixed PHYAD */
2451
2452 /* Record PHY settings. */
2453 spin_lock_irq(&hp->happy_lock);
2454 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2455 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2456 spin_unlock_irq(&hp->happy_lock);
2457
2458 if (hp->sw_bmcr & BMCR_ANENABLE) {
2459 ecmd.autoneg = AUTONEG_ENABLE;
2460 ecmd.speed =
2461 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2462 SPEED_100 : SPEED_10;
2463 if (ecmd.speed == SPEED_100)
2464 ecmd.duplex =
2465 (hp->sw_lpa & (LPA_100FULL)) ?
2466 DUPLEX_FULL : DUPLEX_HALF;
2467 else
2468 ecmd.duplex =
2469 (hp->sw_lpa & (LPA_10FULL)) ?
2470 DUPLEX_FULL : DUPLEX_HALF;
2471 } else {
2472 ecmd.autoneg = AUTONEG_DISABLE;
2473 ecmd.speed =
2474 (hp->sw_bmcr & BMCR_SPEED100) ?
2475 SPEED_100 : SPEED_10;
2476 ecmd.duplex =
2477 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2478 DUPLEX_FULL : DUPLEX_HALF;
2479 }
2480 if (copy_to_user(ep_user, &ecmd, sizeof(ecmd)))
2481 return -EFAULT;
2482 return 0;
2483 } else if (ecmd.cmd == ETHTOOL_SSET) {
2484 if (!capable(CAP_NET_ADMIN))
2485 return -EPERM;
2486
2487 /* Verify the settings we care about. */
2488 if (ecmd.autoneg != AUTONEG_ENABLE &&
2489 ecmd.autoneg != AUTONEG_DISABLE)
2490 return -EINVAL;
2491 if (ecmd.autoneg == AUTONEG_DISABLE &&
2492 ((ecmd.speed != SPEED_100 &&
2493 ecmd.speed != SPEED_10) ||
2494 (ecmd.duplex != DUPLEX_HALF &&
2495 ecmd.duplex != DUPLEX_FULL)))
2496 return -EINVAL;
2497
2498 /* Ok, do it to it. */
2499 spin_lock_irq(&hp->happy_lock);
2500 del_timer(&hp->happy_timer);
2501 happy_meal_begin_auto_negotiation(hp,
2502 hp->tcvregs,
2503 &ecmd);
2504 spin_unlock_irq(&hp->happy_lock);
2505
2506 return 0;
2507 } else
2508 return -EOPNOTSUPP;
2509 }
2510
2511 static int hme_version_printed;
2512
2513 #ifdef CONFIG_SBUS
2514 void __init quattro_get_ranges(struct quattro *qp)
2515 {
2516 struct sbus_dev *sdev = qp->quattro_dev;
2517 int err;
2518
2519 err = prom_getproperty(sdev->prom_node,
2520 "ranges",
2521 (char *)&qp->ranges[0],
2522 sizeof(qp->ranges));
2523 if (err == 0 || err == -1) {
2524 qp->nranges = 0;
2525 return;
2526 }
2527 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2528 }
2529
2530 static void __init quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
2531 {
2532 struct sbus_dev *sdev = hp->happy_dev;
2533 int rng;
2534
2535 for (rng = 0; rng < qp->nranges; rng++) {
2536 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2537 int reg;
2538
2539 for (reg = 0; reg < 5; reg++) {
2540 if (sdev->reg_addrs[reg].which_io ==
2541 rngp->ot_child_space)
2542 break;
2543 }
2544 if (reg == 5)
2545 continue;
2546
2547 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2548 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2549 }
2550 }
2551
2552 /* Given a happy meal sbus device, find it's quattro parent.
2553 * If none exist, allocate and return a new one.
2554 *
2555 * Return NULL on failure.
2556 */
2557 static struct quattro * __init quattro_sbus_find(struct sbus_dev *goal_sdev)
2558 {
2559 struct sbus_bus *sbus;
2560 struct sbus_dev *sdev;
2561 struct quattro *qp;
2562 int i;
2563
2564 if (qfe_sbus_list == NULL)
2565 goto found;
2566
2567 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2568 for (i = 0, sdev = qp->quattro_dev;
2569 (sdev != NULL) && (i < 4);
2570 sdev = sdev->next, i++) {
2571 if (sdev == goal_sdev)
2572 return qp;
2573 }
2574 }
2575 for_each_sbus(sbus) {
2576 for_each_sbusdev(sdev, sbus) {
2577 if (sdev == goal_sdev)
2578 goto found;
2579 }
2580 }
2581
2582 /* Cannot find quattro parent, fail. */
2583 return NULL;
2584
2585 found:
2586 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2587 if (qp != NULL) {
2588 int i;
2589
2590 for (i = 0; i < 4; i++)
2591 qp->happy_meals[i] = NULL;
2592
2593 qp->quattro_dev = goal_sdev;
2594 qp->next = qfe_sbus_list;
2595 qfe_sbus_list = qp;
2596 quattro_get_ranges(qp);
2597 }
2598 return qp;
2599 }
2600
2601 /* After all quattro cards have been probed, we call these functions
2602 * to register the IRQ handlers.
2603 */
2604 static void __init quattro_sbus_register_irqs(void)
2605 {
2606 struct quattro *qp;
2607
2608 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2609 struct sbus_dev *sdev = qp->quattro_dev;
2610 int err;
2611
2612 err = request_irq(sdev->irqs[0],
2613 quattro_sbus_interrupt,
2614 SA_SHIRQ, "Quattro",
2615 qp);
2616 if (err != 0) {
2617 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2618 panic("QFE request irq");
2619 }
2620 }
2621 }
2622 #endif /* CONFIG_SBUS */
2623
2624 #ifdef CONFIG_PCI
2625 static struct quattro * __init quattro_pci_find(struct pci_dev *pdev)
2626 {
2627 struct pci_dev *bdev = pdev->bus->self;
2628 struct quattro *qp;
2629
2630 if (!bdev) return NULL;
2631 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2632 struct pci_dev *qpdev = qp->quattro_dev;
2633
2634 if (qpdev == bdev)
2635 return qp;
2636 }
2637 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2638 if (qp != NULL) {
2639 int i;
2640
2641 for (i = 0; i < 4; i++)
2642 qp->happy_meals[i] = NULL;
2643
2644 qp->quattro_dev = bdev;
2645 qp->next = qfe_pci_list;
2646 qfe_pci_list = qp;
2647
2648 /* No range tricks necessary on PCI. */
2649 qp->nranges = 0;
2650 }
2651 return qp;
2652 }
2653 #endif /* CONFIG_PCI */
2654
2655 #ifdef CONFIG_SBUS
2656 static int __init happy_meal_sbus_init(struct sbus_dev *sdev, int is_qfe)
2657 {
2658 struct quattro *qp = NULL;
2659 struct happy_meal *hp;
2660 struct net_device *dev;
2661 int i, qfe_slot = -1;
2662 int err = -ENODEV;
2663
2664 if (is_qfe) {
2665 qp = quattro_sbus_find(sdev);
2666 if (qp == NULL)
2667 goto err_out;
2668 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2669 if (qp->happy_meals[qfe_slot] == NULL)
2670 break;
2671 if (qfe_slot == 4)
2672 goto err_out;
2673 }
2674
2675 err = -ENOMEM;
2676 dev = alloc_etherdev(sizeof(struct happy_meal));
2677 if (!dev)
2678 goto err_out;
2679 SET_MODULE_OWNER(dev);
2680
2681 if (hme_version_printed++ == 0)
2682 printk(KERN_INFO "%s", version);
2683
2684 /* If user did not specify a MAC address specifically, use
2685 * the Quattro local-mac-address property...
2686 */
2687 for (i = 0; i < 6; i++) {
2688 if (macaddr[i] != 0)
2689 break;
2690 }
2691 if (i < 6) { /* a mac address was given */
2692 for (i = 0; i < 6; i++)
2693 dev->dev_addr[i] = macaddr[i];
2694 macaddr[5]++;
2695 } else if (qfe_slot != -1 &&
2696 prom_getproplen(sdev->prom_node,
2697 "local-mac-address") == 6) {
2698 prom_getproperty(sdev->prom_node, "local-mac-address",
2699 dev->dev_addr, 6);
2700 } else {
2701 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2702 }
2703
2704 hp = dev->priv;
2705
2706 hp->happy_dev = sdev;
2707
2708 spin_lock_init(&hp->happy_lock);
2709
2710 err = -ENODEV;
2711 if (sdev->num_registers != 5) {
2712 printk(KERN_ERR "happymeal: Device does not have 5 regs, it has %d.\n",
2713 sdev->num_registers);
2714 printk(KERN_ERR "happymeal: Would you like that for here or to go?\n");
2715 goto err_out_free_netdev;
2716 }
2717
2718 if (qp != NULL) {
2719 hp->qfe_parent = qp;
2720 hp->qfe_ent = qfe_slot;
2721 qp->happy_meals[qfe_slot] = dev;
2722 quattro_apply_ranges(qp, hp);
2723 }
2724
2725 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2726 GREG_REG_SIZE, "HME Global Regs");
2727 if (!hp->gregs) {
2728 printk(KERN_ERR "happymeal: Cannot map Happy Meal global registers.\n");
2729 goto err_out_free_netdev;
2730 }
2731
2732 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2733 ETX_REG_SIZE, "HME TX Regs");
2734 if (!hp->etxregs) {
2735 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Transmit registers.\n");
2736 goto err_out_iounmap;
2737 }
2738
2739 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2740 ERX_REG_SIZE, "HME RX Regs");
2741 if (!hp->erxregs) {
2742 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Receive registers.\n");
2743 goto err_out_iounmap;
2744 }
2745
2746 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2747 BMAC_REG_SIZE, "HME BIGMAC Regs");
2748 if (!hp->bigmacregs) {
2749 printk(KERN_ERR "happymeal: Cannot map Happy Meal BIGMAC registers.\n");
2750 goto err_out_iounmap;
2751 }
2752
2753 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2754 TCVR_REG_SIZE, "HME Tranceiver Regs");
2755 if (!hp->tcvregs) {
2756 printk(KERN_ERR "happymeal: Cannot map Happy Meal Tranceiver registers.\n");
2757 goto err_out_iounmap;
2758 }
2759
2760 hp->hm_revision = prom_getintdefault(sdev->prom_node, "hm-rev", 0xff);
2761 if (hp->hm_revision == 0xff)
2762 hp->hm_revision = 0xa0;
2763
2764 /* Now enable the feature flags we can. */
2765 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2766 hp->happy_flags = HFLAG_20_21;
2767 else if (hp->hm_revision != 0xa0)
2768 hp->happy_flags = HFLAG_NOT_A0;
2769
2770 if (qp != NULL)
2771 hp->happy_flags |= HFLAG_QUATTRO;
2772
2773 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2774 hp->happy_bursts = prom_getintdefault(sdev->bus->prom_node,
2775 "burst-sizes", 0x00);
2776
2777 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2778 PAGE_SIZE,
2779 &hp->hblock_dvma);
2780 err = -ENOMEM;
2781 if (!hp->happy_block) {
2782 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2783 goto err_out_iounmap;
2784 }
2785
2786 /* Force check of the link first time we are brought up. */
2787 hp->linkcheck = 0;
2788
2789 /* Force timer state to 'asleep' with count of zero. */
2790 hp->timer_state = asleep;
2791 hp->timer_ticks = 0;
2792
2793 init_timer(&hp->happy_timer);
2794
2795 hp->dev = dev;
2796 dev->open = &happy_meal_open;
2797 dev->stop = &happy_meal_close;
2798 dev->hard_start_xmit = &happy_meal_start_xmit;
2799 dev->get_stats = &happy_meal_get_stats;
2800 dev->set_multicast_list = &happy_meal_set_multicast;
2801 dev->tx_timeout = &happy_meal_tx_timeout;
2802 dev->watchdog_timeo = 5*HZ;
2803 dev->do_ioctl = &happy_meal_ioctl;
2804
2805 /* Happy Meal can do it all... */
2806 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
2807
2808 dev->irq = sdev->irqs[0];
2809
2810 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2811 /* Hook up PCI register/dma accessors. */
2812 hp->read_desc32 = sbus_hme_read_desc32;
2813 hp->write_txd = sbus_hme_write_txd;
2814 hp->write_rxd = sbus_hme_write_rxd;
2815 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2816 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2817 hp->dma_sync = (void (*)(void *, u32, long, int))sbus_dma_sync_single;
2818 hp->read32 = sbus_hme_read32;
2819 hp->write32 = sbus_hme_write32;
2820 #endif
2821
2822 /* Grrr, Happy Meal comes up by default not advertising
2823 * full duplex 100baseT capabilities, fix this.
2824 */
2825 spin_lock_irq(&hp->happy_lock);
2826 happy_meal_set_initial_advertisement(hp);
2827 spin_unlock_irq(&hp->happy_lock);
2828
2829 if (register_netdev(hp->dev)) {
2830 printk(KERN_ERR "happymeal: Cannot register net device, "
2831 "aborting.\n");
2832 goto err_out_free_consistent;
2833 }
2834
2835 if (qfe_slot != -1)
2836 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2837 dev->name, qfe_slot);
2838 else
2839 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2840 dev->name);
2841
2842 for (i = 0; i < 6; i++)
2843 printk("%2.2x%c",
2844 dev->dev_addr[i], i == 5 ? ' ' : ':');
2845 printk("\n");
2846
2847 /* We are home free at this point, link us in to the happy
2848 * device list.
2849 */
2850 hp->next_module = root_happy_dev;
2851 root_happy_dev = hp;
2852
2853 return 0;
2854
2855 err_out_free_consistent:
2856 sbus_free_consistent(hp->happy_dev,
2857 PAGE_SIZE,
2858 hp->happy_block,
2859 hp->hblock_dvma);
2860
2861 err_out_iounmap:
2862 if (hp->gregs)
2863 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
2864 if (hp->etxregs)
2865 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
2866 if (hp->erxregs)
2867 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
2868 if (hp->bigmacregs)
2869 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
2870 if (hp->tcvregs)
2871 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
2872
2873 err_out_free_netdev:
2874 kfree(dev);
2875
2876 err_out:
2877 return err;
2878 }
2879 #endif
2880
2881 #ifdef CONFIG_PCI
2882 #ifndef __sparc__
2883 static int is_quattro_p(struct pci_dev *pdev)
2884 {
2885 struct pci_dev *busdev = pdev->bus->self;
2886 struct list_head *tmp;
2887 int n_hmes;
2888
2889 if (busdev->vendor != PCI_VENDOR_ID_DEC ||
2890 busdev->device != PCI_DEVICE_ID_DEC_21153)
2891 return 0;
2892
2893 n_hmes = 0;
2894 tmp = pdev->bus->devices.next;
2895 while (tmp != &pdev->bus->devices) {
2896 struct pci_dev *this_pdev = pci_dev_b(tmp);
2897
2898 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2899 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2900 n_hmes++;
2901
2902 tmp = tmp->next;
2903 }
2904
2905 if (n_hmes != 4)
2906 return 0;
2907
2908 return 1;
2909 }
2910
2911 /* Fetch MAC address from vital product data of PCI ROM. */
2912 static void find_eth_addr_in_vpd(void *rom_base, int len, int index, unsigned char *dev_addr)
2913 {
2914 int this_offset;
2915
2916 for (this_offset = 0x20; this_offset < len; this_offset++) {
2917 void *p = rom_base + this_offset;
2918
2919 if (readb(p + 0) != 0x90 ||
2920 readb(p + 1) != 0x00 ||
2921 readb(p + 2) != 0x09 ||
2922 readb(p + 3) != 0x4e ||
2923 readb(p + 4) != 0x41 ||
2924 readb(p + 5) != 0x06)
2925 continue;
2926
2927 this_offset += 6;
2928 p += 6;
2929
2930 if (index == 0) {
2931 int i;
2932
2933 for (i = 0; i < 6; i++)
2934 dev_addr[i] = readb(p + i);
2935 break;
2936 }
2937 index--;
2938 }
2939 }
2940
2941 static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2942 {
2943 u32 rom_reg_orig;
2944 void *p;
2945 int index;
2946
2947 index = 0;
2948 if (is_quattro_p(pdev))
2949 index = PCI_SLOT(pdev->devfn);
2950
2951 if (pdev->resource[PCI_ROM_RESOURCE].parent == NULL) {
2952 if (pci_assign_resource(pdev, PCI_ROM_RESOURCE) < 0)
2953 goto use_random;
2954 }
2955
2956 pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_reg_orig);
2957 pci_write_config_dword(pdev, pdev->rom_base_reg,
2958 rom_reg_orig | PCI_ROM_ADDRESS_ENABLE);
2959
2960 p = ioremap(pci_resource_start(pdev, PCI_ROM_RESOURCE), (64 * 1024));
2961 if (p != NULL && readb(p) == 0x55 && readb(p + 1) == 0xaa)
2962 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2963
2964 if (p != NULL)
2965 iounmap(p);
2966
2967 pci_write_config_dword(pdev, pdev->rom_base_reg, rom_reg_orig);
2968 return;
2969
2970 use_random:
2971 /* Sun MAC prefix then 3 random bytes. */
2972 dev_addr[0] = 0x08;
2973 dev_addr[1] = 0x00;
2974 dev_addr[2] = 0x20;
2975 get_random_bytes(dev_addr, 3);
2976 return;
2977 }
2978 #endif /* !(__sparc__) */
2979
2980 static int __init happy_meal_pci_init(struct pci_dev *pdev)
2981 {
2982 struct quattro *qp = NULL;
2983 #ifdef __sparc__
2984 struct pcidev_cookie *pcp;
2985 int node;
2986 #endif
2987 struct happy_meal *hp;
2988 struct net_device *dev;
2989 unsigned long hpreg_base;
2990 int i, qfe_slot = -1;
2991 char prom_name[64];
2992 int err;
2993
2994 /* Now make sure pci_dev cookie is there. */
2995 #ifdef __sparc__
2996 pcp = pdev->sysdata;
2997 if (pcp == NULL || pcp->prom_node == -1) {
2998 printk(KERN_ERR "happymeal(PCI): Some PCI device info missing\n");
2999 return -ENODEV;
3000 }
3001 node = pcp->prom_node;
3002
3003 prom_getstring(node, "name", prom_name, sizeof(prom_name));
3004 #else
3005 if (is_quattro_p(pdev))
3006 strcpy(prom_name, "SUNW,qfe");
3007 else
3008 strcpy(prom_name, "SUNW,hme");
3009 #endif
3010
3011 err = -ENODEV;
3012 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
3013 qp = quattro_pci_find(pdev);
3014 if (qp == NULL)
3015 goto err_out;
3016 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
3017 if (qp->happy_meals[qfe_slot] == NULL)
3018 break;
3019 if (qfe_slot == 4)
3020 goto err_out;
3021 }
3022
3023 dev = alloc_etherdev(sizeof(struct happy_meal));
3024 err = -ENOMEM;
3025 if (!dev)
3026 goto err_out;
3027 SET_MODULE_OWNER(dev);
3028 SET_NETDEV_DEV(dev, &pdev->dev);
3029
3030 if (hme_version_printed++ == 0)
3031 printk(KERN_INFO "%s", version);
3032
3033 dev->base_addr = (long) pdev;
3034
3035 hp = (struct happy_meal *)dev->priv;
3036 memset(hp, 0, sizeof(*hp));
3037
3038 hp->happy_dev = pdev;
3039
3040 spin_lock_init(&hp->happy_lock);
3041
3042 if (qp != NULL) {
3043 hp->qfe_parent = qp;
3044 hp->qfe_ent = qfe_slot;
3045 qp->happy_meals[qfe_slot] = dev;
3046 }
3047
3048 hpreg_base = pci_resource_start(pdev, 0);
3049 err = -ENODEV;
3050 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3051 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
3052 goto err_out_clear_quattro;
3053 }
3054 if (pci_request_regions(pdev, dev->name)) {
3055 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3056 "aborting.\n");
3057 goto err_out_clear_quattro;
3058 }
3059
3060 if ((hpreg_base = (unsigned long) ioremap(hpreg_base, 0x8000)) == 0) {
3061 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3062 goto err_out_free_res;
3063 }
3064
3065 for (i = 0; i < 6; i++) {
3066 if (macaddr[i] != 0)
3067 break;
3068 }
3069 if (i < 6) { /* a mac address was given */
3070 for (i = 0; i < 6; i++)
3071 dev->dev_addr[i] = macaddr[i];
3072 macaddr[5]++;
3073 } else {
3074 #ifdef __sparc__
3075 if (qfe_slot != -1 &&
3076 prom_getproplen(node, "local-mac-address") == 6) {
3077 prom_getproperty(node, "local-mac-address",
3078 dev->dev_addr, 6);
3079 } else {
3080 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3081 }
3082 #else
3083 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3084 #endif
3085 }
3086
3087 /* Layout registers. */
3088 hp->gregs = (hpreg_base + 0x0000UL);
3089 hp->etxregs = (hpreg_base + 0x2000UL);
3090 hp->erxregs = (hpreg_base + 0x4000UL);
3091 hp->bigmacregs = (hpreg_base + 0x6000UL);
3092 hp->tcvregs = (hpreg_base + 0x7000UL);
3093
3094 #ifdef __sparc__
3095 hp->hm_revision = prom_getintdefault(node, "hm-rev", 0xff);
3096 if (hp->hm_revision == 0xff) {
3097 unsigned char prev;
3098
3099 pci_read_config_byte(pdev, PCI_REVISION_ID, &prev);
3100 hp->hm_revision = 0xc0 | (prev & 0x0f);
3101 }
3102 #else
3103 /* works with this on non-sparc hosts */
3104 hp->hm_revision = 0x20;
3105 #endif
3106
3107 /* Now enable the feature flags we can. */
3108 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3109 hp->happy_flags = HFLAG_20_21;
3110 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3111 hp->happy_flags = HFLAG_NOT_A0;
3112
3113 if (qp != NULL)
3114 hp->happy_flags |= HFLAG_QUATTRO;
3115
3116 /* And of course, indicate this is PCI. */
3117 hp->happy_flags |= HFLAG_PCI;
3118
3119 #ifdef __sparc__
3120 /* Assume PCI happy meals can handle all burst sizes. */
3121 hp->happy_bursts = DMA_BURSTBITS;
3122 #endif
3123
3124 hp->happy_block = (struct hmeal_init_block *)
3125 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
3126
3127 err = -ENODEV;
3128 if (!hp->happy_block) {
3129 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3130 goto err_out_iounmap;
3131 }
3132
3133 hp->linkcheck = 0;
3134 hp->timer_state = asleep;
3135 hp->timer_ticks = 0;
3136
3137 init_timer(&hp->happy_timer);
3138
3139 hp->dev = dev;
3140 dev->open = &happy_meal_open;
3141 dev->stop = &happy_meal_close;
3142 dev->hard_start_xmit = &happy_meal_start_xmit;
3143 dev->get_stats = &happy_meal_get_stats;
3144 dev->set_multicast_list = &happy_meal_set_multicast;
3145 dev->tx_timeout = &happy_meal_tx_timeout;
3146 dev->watchdog_timeo = 5*HZ;
3147 dev->do_ioctl = &happy_meal_ioctl;
3148 dev->irq = pdev->irq;
3149 dev->dma = 0;
3150
3151 /* Happy Meal can do it all... */
3152 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3153
3154 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3155 /* Hook up PCI register/dma accessors. */
3156 hp->read_desc32 = pci_hme_read_desc32;
3157 hp->write_txd = pci_hme_write_txd;
3158 hp->write_rxd = pci_hme_write_rxd;
3159 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
3160 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
3161 hp->dma_sync = (void (*)(void *, u32, long, int))pci_dma_sync_single;
3162 hp->read32 = pci_hme_read32;
3163 hp->write32 = pci_hme_write32;
3164 #endif
3165
3166 /* Grrr, Happy Meal comes up by default not advertising
3167 * full duplex 100baseT capabilities, fix this.
3168 */
3169 spin_lock_irq(&hp->happy_lock);
3170 happy_meal_set_initial_advertisement(hp);
3171 spin_unlock_irq(&hp->happy_lock);
3172
3173 if (register_netdev(hp->dev)) {
3174 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3175 "aborting.\n");
3176 goto err_out_iounmap;
3177 }
3178
3179 if (!qfe_slot) {
3180 struct pci_dev *qpdev = qp->quattro_dev;
3181
3182 prom_name[0] = 0;
3183 if (!strncmp(dev->name, "eth", 3)) {
3184 int i = simple_strtoul(dev->name + 3, NULL, 10);
3185 sprintf(prom_name, "-%d", i + 3);
3186 }
3187 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3188 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3189 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3190 printk("DEC 21153 PCI Bridge\n");
3191 else
3192 printk("unknown bridge %04x.%04x\n",
3193 qpdev->vendor, qpdev->device);
3194 }
3195
3196 if (qfe_slot != -1)
3197 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3198 dev->name, qfe_slot);
3199 else
3200 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3201 dev->name);
3202
3203 for (i = 0; i < 6; i++)
3204 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
3205
3206 printk("\n");
3207
3208 /* We are home free at this point, link us in to the happy
3209 * device list.
3210 */
3211 hp->next_module = root_happy_dev;
3212 root_happy_dev = hp;
3213
3214 return 0;
3215
3216 err_out_iounmap:
3217 iounmap((void *)hp->gregs);
3218
3219 err_out_free_res:
3220 pci_release_regions(pdev);
3221
3222 err_out_clear_quattro:
3223 if (qp != NULL)
3224 qp->happy_meals[qfe_slot] = NULL;
3225
3226 kfree(dev);
3227
3228 err_out:
3229 return err;
3230 }
3231 #endif
3232
3233 #ifdef CONFIG_SBUS
3234 static int __init happy_meal_sbus_probe(void)
3235 {
3236 struct sbus_bus *sbus;
3237 struct sbus_dev *sdev;
3238 int cards = 0;
3239 char model[128];
3240
3241 for_each_sbus(sbus) {
3242 for_each_sbusdev(sdev, sbus) {
3243 char *name = sdev->prom_name;
3244
3245 if (!strcmp(name, "SUNW,hme")) {
3246 cards++;
3247 prom_getstring(sdev->prom_node, "model",
3248 model, sizeof(model));
3249 if (!strcmp(model, "SUNW,sbus-qfe"))
3250 happy_meal_sbus_init(sdev, 1);
3251 else
3252 happy_meal_sbus_init(sdev, 0);
3253 } else if (!strcmp(name, "qfe") ||
3254 !strcmp(name, "SUNW,qfe")) {
3255 cards++;
3256 happy_meal_sbus_init(sdev, 1);
3257 }
3258 }
3259 }
3260 if (cards != 0)
3261 quattro_sbus_register_irqs();
3262 return cards;
3263 }
3264 #endif
3265
3266 #ifdef CONFIG_PCI
3267 static int __init happy_meal_pci_probe(void)
3268 {
3269 struct pci_dev *pdev = NULL;
3270 int cards = 0;
3271
3272 while ((pdev = pci_find_device(PCI_VENDOR_ID_SUN,
3273 PCI_DEVICE_ID_SUN_HAPPYMEAL, pdev)) != NULL) {
3274 if (pci_enable_device(pdev))
3275 continue;
3276 pci_set_master(pdev);
3277 cards++;
3278 happy_meal_pci_init(pdev);
3279 }
3280 return cards;
3281 }
3282 #endif
3283
3284 static int __init happy_meal_probe(void)
3285 {
3286 static int called = 0;
3287 int cards;
3288
3289 root_happy_dev = NULL;
3290
3291 if (called)
3292 return -ENODEV;
3293 called++;
3294
3295 cards = 0;
3296 #ifdef CONFIG_SBUS
3297 cards += happy_meal_sbus_probe();
3298 #endif
3299 #ifdef CONFIG_PCI
3300 cards += happy_meal_pci_probe();
3301 #endif
3302 if (!cards)
3303 return -ENODEV;
3304 return 0;
3305 }
3306
3307
3308 static void __exit happy_meal_cleanup_module(void)
3309 {
3310 #ifdef CONFIG_SBUS
3311 struct quattro *last_seen_qfe = NULL;
3312 #endif
3313
3314 while (root_happy_dev) {
3315 struct happy_meal *hp = root_happy_dev;
3316 struct happy_meal *next = root_happy_dev->next_module;
3317 struct net_device *dev = hp->dev;
3318
3319 /* Unregister netdev before unmapping registers as this
3320 * call can end up trying to access those registers.
3321 */
3322 unregister_netdev(dev);
3323
3324 #ifdef CONFIG_SBUS
3325 if (!(hp->happy_flags & HFLAG_PCI)) {
3326 if (hp->happy_flags & HFLAG_QUATTRO) {
3327 if (hp->qfe_parent != last_seen_qfe) {
3328 free_irq(dev->irq, hp->qfe_parent);
3329 last_seen_qfe = hp->qfe_parent;
3330 }
3331 }
3332
3333 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3334 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3335 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3336 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3337 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3338 sbus_free_consistent(hp->happy_dev,
3339 PAGE_SIZE,
3340 hp->happy_block,
3341 hp->hblock_dvma);
3342 }
3343 #endif
3344 #ifdef CONFIG_PCI
3345 if ((hp->happy_flags & HFLAG_PCI)) {
3346 pci_free_consistent(hp->happy_dev,
3347 PAGE_SIZE,
3348 hp->happy_block,
3349 hp->hblock_dvma);
3350 iounmap((void *)hp->gregs);
3351 pci_release_regions(hp->happy_dev);
3352 }
3353 #endif
3354 kfree(dev);
3355
3356 root_happy_dev = next;
3357 }
3358
3359 /* Now cleanup the quattro lists. */
3360 #ifdef CONFIG_SBUS
3361 while (qfe_sbus_list) {
3362 struct quattro *qfe = qfe_sbus_list;
3363 struct quattro *next = qfe->next;
3364
3365 kfree(qfe);
3366
3367 qfe_sbus_list = next;
3368 }
3369 #endif
3370 #ifdef CONFIG_PCI
3371 while (qfe_pci_list) {
3372 struct quattro *qfe = qfe_pci_list;
3373 struct quattro *next = qfe->next;
3374
3375 kfree(qfe);
3376
3377 qfe_pci_list = next;
3378 }
3379 #endif
3380 }
3381
3382 module_init(happy_meal_probe);
3383 module_exit(happy_meal_cleanup_module);
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