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[linux-2.6/linux-mips.git] / drivers / net / sungem.c
bloba005eb8d53add03a350f55d435fd79e6912f322d
1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs by
7 * Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 *
9 * TODO:
10 * - Get rid of all those nasty mdelay's and replace them
11 * with schedule_timeout.
12 * - Implement WOL
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/fcntl.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/in.h>
22 #include <linux/slab.h>
23 #include <linux/string.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/errno.h>
27 #include <linux/pci.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/skbuff.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/crc32.h>
34 #include <linux/random.h>
35 #include <linux/workqueue.h>
36
37 #include <asm/system.h>
38 #include <asm/bitops.h>
39 #include <asm/io.h>
40 #include <asm/byteorder.h>
41 #include <asm/uaccess.h>
42 #include <asm/irq.h>
43
44 #ifdef __sparc__
45 #include <asm/idprom.h>
46 #include <asm/openprom.h>
47 #include <asm/oplib.h>
48 #include <asm/pbm.h>
49 #endif
50
51 #ifdef CONFIG_PPC_PMAC
52 #include <asm/pci-bridge.h>
53 #include <asm/prom.h>
54 #include <asm/machdep.h>
55 #include <asm/pmac_feature.h>
56 #endif
57
58 #include "sungem_phy.h"
59 #include "sungem.h"
60
61 /* Stripping FCS is causing problems, disabled for now */
62 #undef STRIP_FCS
63
64 #define DEFAULT_MSG (NETIF_MSG_DRV | \
65 NETIF_MSG_PROBE | \
66 NETIF_MSG_LINK)
67
68 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
69 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
70 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
71
72 #define DRV_NAME "sungem"
73 #define DRV_VERSION "0.97"
74 #define DRV_RELDATE "3/20/02"
75 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
76
77 static char version[] __devinitdata =
78 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
79
80 MODULE_AUTHOR(DRV_AUTHOR);
81 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
82 MODULE_LICENSE("GPL");
83
84 #define GEM_MODULE_NAME "gem"
85 #define PFX GEM_MODULE_NAME ": "
86
87 static struct pci_device_id gem_pci_tbl[] __devinitdata = {
88 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
89 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
90
91 /* These models only differ from the original GEM in
92 * that their tx/rx fifos are of a different size and
93 * they only support 10/100 speeds. -DaveM
94 *
95 * Apple's GMAC does support gigabit on machines with
96 * the BCM54xx PHYs. -BenH
97 */
98 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
99 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
100 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
102 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
104 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
106 {0, }
107 };
108
109 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
110
111 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
112 {
113 u32 cmd;
114 int limit = 10000;
115
116 cmd = (1 << 30);
117 cmd |= (2 << 28);
118 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
119 cmd |= (reg << 18) & MIF_FRAME_REGAD;
120 cmd |= (MIF_FRAME_TAMSB);
121 writel(cmd, gp->regs + MIF_FRAME);
122
123 while (limit--) {
124 cmd = readl(gp->regs + MIF_FRAME);
125 if (cmd & MIF_FRAME_TALSB)
126 break;
127
128 udelay(10);
129 }
130
131 if (!limit)
132 cmd = 0xffff;
133
134 return cmd & MIF_FRAME_DATA;
135 }
136
137 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
138 {
139 struct gem *gp = dev->priv;
140 return __phy_read(gp, mii_id, reg);
141 }
142
143 static inline u16 phy_read(struct gem *gp, int reg)
144 {
145 return __phy_read(gp, gp->mii_phy_addr, reg);
146 }
147
148 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
149 {
150 u32 cmd;
151 int limit = 10000;
152
153 cmd = (1 << 30);
154 cmd |= (1 << 28);
155 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
156 cmd |= (reg << 18) & MIF_FRAME_REGAD;
157 cmd |= (MIF_FRAME_TAMSB);
158 cmd |= (val & MIF_FRAME_DATA);
159 writel(cmd, gp->regs + MIF_FRAME);
160
161 while (limit--) {
162 cmd = readl(gp->regs + MIF_FRAME);
163 if (cmd & MIF_FRAME_TALSB)
164 break;
165
166 udelay(10);
167 }
168 }
169
170 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
171 {
172 struct gem *gp = dev->priv;
173 __phy_write(gp, mii_id, reg, val & 0xffff);
174 }
175
176 static inline void phy_write(struct gem *gp, int reg, u16 val)
177 {
178 __phy_write(gp, gp->mii_phy_addr, reg, val);
179 }
180
181 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
182 {
183 if (netif_msg_intr(gp))
184 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
185 }
186
187 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
188 {
189 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
190 u32 pcs_miistat;
191
192 if (netif_msg_intr(gp))
193 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
194 gp->dev->name, pcs_istat);
195
196 if (!(pcs_istat & PCS_ISTAT_LSC)) {
197 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
198 dev->name);
199 return 0;
200 }
201
202 /* The link status bit latches on zero, so you must
203 * read it twice in such a case to see a transition
204 * to the link being up.
205 */
206 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
207 if (!(pcs_miistat & PCS_MIISTAT_LS))
208 pcs_miistat |=
209 (readl(gp->regs + PCS_MIISTAT) &
210 PCS_MIISTAT_LS);
211
212 if (pcs_miistat & PCS_MIISTAT_ANC) {
213 /* The remote-fault indication is only valid
214 * when autoneg has completed.
215 */
216 if (pcs_miistat & PCS_MIISTAT_RF)
217 printk(KERN_INFO "%s: PCS AutoNEG complete, "
218 "RemoteFault\n", dev->name);
219 else
220 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
221 dev->name);
222 }
223
224 if (pcs_miistat & PCS_MIISTAT_LS) {
225 printk(KERN_INFO "%s: PCS link is now up.\n",
226 dev->name);
227 netif_carrier_on(gp->dev);
228 } else {
229 printk(KERN_INFO "%s: PCS link is now down.\n",
230 dev->name);
231 netif_carrier_off(gp->dev);
232 /* If this happens and the link timer is not running,
233 * reset so we re-negotiate.
234 */
235 if (!timer_pending(&gp->link_timer))
236 return 1;
237 }
238
239 return 0;
240 }
241
242 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
243 {
244 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
245
246 if (netif_msg_intr(gp))
247 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
248 gp->dev->name, txmac_stat);
249
250 /* Defer timer expiration is quite normal,
251 * don't even log the event.
252 */
253 if ((txmac_stat & MAC_TXSTAT_DTE) &&
254 !(txmac_stat & ~MAC_TXSTAT_DTE))
255 return 0;
256
257 if (txmac_stat & MAC_TXSTAT_URUN) {
258 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
259 dev->name);
260 gp->net_stats.tx_fifo_errors++;
261 }
262
263 if (txmac_stat & MAC_TXSTAT_MPE) {
264 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
265 dev->name);
266 gp->net_stats.tx_errors++;
267 }
268
269 /* The rest are all cases of one of the 16-bit TX
270 * counters expiring.
271 */
272 if (txmac_stat & MAC_TXSTAT_NCE)
273 gp->net_stats.collisions += 0x10000;
274
275 if (txmac_stat & MAC_TXSTAT_ECE) {
276 gp->net_stats.tx_aborted_errors += 0x10000;
277 gp->net_stats.collisions += 0x10000;
278 }
279
280 if (txmac_stat & MAC_TXSTAT_LCE) {
281 gp->net_stats.tx_aborted_errors += 0x10000;
282 gp->net_stats.collisions += 0x10000;
283 }
284
285 /* We do not keep track of MAC_TXSTAT_FCE and
286 * MAC_TXSTAT_PCE events.
287 */
288 return 0;
289 }
290
291 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
292 * so we do the following.
293 *
294 * If any part of the reset goes wrong, we return 1 and that causes the
295 * whole chip to be reset.
296 */
297 static int gem_rxmac_reset(struct gem *gp)
298 {
299 struct net_device *dev = gp->dev;
300 int limit, i;
301 u64 desc_dma;
302 u32 val;
303
304 /* First, reset MAC RX. */
305 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
306 gp->regs + MAC_RXCFG);
307 for (limit = 0; limit < 5000; limit++) {
308 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
309 break;
310 udelay(10);
311 }
312 if (limit == 5000) {
313 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
314 "chip.\n", dev->name);
315 return 1;
316 }
317
318 /* Second, disable RX DMA. */
319 writel(0, gp->regs + RXDMA_CFG);
320 for (limit = 0; limit < 5000; limit++) {
321 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
322 break;
323 udelay(10);
324 }
325 if (limit == 5000) {
326 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
327 "chip.\n", dev->name);
328 return 1;
329 }
330
331 udelay(5000);
332
333 /* Execute RX reset command. */
334 writel(gp->swrst_base | GREG_SWRST_RXRST,
335 gp->regs + GREG_SWRST);
336 for (limit = 0; limit < 5000; limit++) {
337 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
338 break;
339 udelay(10);
340 }
341 if (limit == 5000) {
342 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
343 "whole chip.\n", dev->name);
344 return 1;
345 }
346
347 /* Refresh the RX ring. */
348 for (i = 0; i < RX_RING_SIZE; i++) {
349 struct gem_rxd *rxd = &gp->init_block->rxd[i];
350
351 if (gp->rx_skbs[i] == NULL) {
352 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
353 "whole chip.\n", dev->name);
354 return 1;
355 }
356
357 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
358 }
359 gp->rx_new = gp->rx_old = 0;
360
361 /* Now we must reprogram the rest of RX unit. */
362 desc_dma = (u64) gp->gblock_dvma;
363 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
364 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
365 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
366 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
367 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
368 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
369 writel(val, gp->regs + RXDMA_CFG);
370 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
371 writel(((5 & RXDMA_BLANK_IPKTS) |
372 ((8 << 12) & RXDMA_BLANK_ITIME)),
373 gp->regs + RXDMA_BLANK);
374 else
375 writel(((5 & RXDMA_BLANK_IPKTS) |
376 ((4 << 12) & RXDMA_BLANK_ITIME)),
377 gp->regs + RXDMA_BLANK);
378 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
379 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
380 writel(val, gp->regs + RXDMA_PTHRESH);
381 val = readl(gp->regs + RXDMA_CFG);
382 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
383 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
384 val = readl(gp->regs + MAC_RXCFG);
385 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
386
387 return 0;
388 }
389
390 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
391 {
392 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
393 int ret = 0;
394
395 if (netif_msg_intr(gp))
396 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
397 gp->dev->name, rxmac_stat);
398
399 if (rxmac_stat & MAC_RXSTAT_OFLW) {
400 u32 smac = readl(gp->regs + MAC_SMACHINE);
401
402 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
403 dev->name, smac);
404 gp->net_stats.rx_over_errors++;
405 gp->net_stats.rx_fifo_errors++;
406
407 ret = gem_rxmac_reset(gp);
408 }
409
410 if (rxmac_stat & MAC_RXSTAT_ACE)
411 gp->net_stats.rx_frame_errors += 0x10000;
412
413 if (rxmac_stat & MAC_RXSTAT_CCE)
414 gp->net_stats.rx_crc_errors += 0x10000;
415
416 if (rxmac_stat & MAC_RXSTAT_LCE)
417 gp->net_stats.rx_length_errors += 0x10000;
418
419 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
420 * events.
421 */
422 return ret;
423 }
424
425 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
426 {
427 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
428
429 if (netif_msg_intr(gp))
430 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
431 gp->dev->name, mac_cstat);
432
433 /* This interrupt is just for pause frame and pause
434 * tracking. It is useful for diagnostics and debug
435 * but probably by default we will mask these events.
436 */
437 if (mac_cstat & MAC_CSTAT_PS)
438 gp->pause_entered++;
439
440 if (mac_cstat & MAC_CSTAT_PRCV)
441 gp->pause_last_time_recvd = (mac_cstat >> 16);
442
443 return 0;
444 }
445
446 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
447 {
448 u32 mif_status = readl(gp->regs + MIF_STATUS);
449 u32 reg_val, changed_bits;
450
451 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
452 changed_bits = (mif_status & MIF_STATUS_STAT);
453
454 gem_handle_mif_event(gp, reg_val, changed_bits);
455
456 return 0;
457 }
458
459 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
460 {
461 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
462
463 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
464 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
465 printk(KERN_ERR "%s: PCI error [%04x] ",
466 dev->name, pci_estat);
467
468 if (pci_estat & GREG_PCIESTAT_BADACK)
469 printk("<No ACK64# during ABS64 cycle> ");
470 if (pci_estat & GREG_PCIESTAT_DTRTO)
471 printk("<Delayed transaction timeout> ");
472 if (pci_estat & GREG_PCIESTAT_OTHER)
473 printk("<other>");
474 printk("\n");
475 } else {
476 pci_estat |= GREG_PCIESTAT_OTHER;
477 printk(KERN_ERR "%s: PCI error\n", dev->name);
478 }
479
480 if (pci_estat & GREG_PCIESTAT_OTHER) {
481 u16 pci_cfg_stat;
482
483 /* Interrogate PCI config space for the
484 * true cause.
485 */
486 pci_read_config_word(gp->pdev, PCI_STATUS,
487 &pci_cfg_stat);
488 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
489 dev->name, pci_cfg_stat);
490 if (pci_cfg_stat & PCI_STATUS_PARITY)
491 printk(KERN_ERR "%s: PCI parity error detected.\n",
492 dev->name);
493 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
494 printk(KERN_ERR "%s: PCI target abort.\n",
495 dev->name);
496 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
497 printk(KERN_ERR "%s: PCI master acks target abort.\n",
498 dev->name);
499 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
500 printk(KERN_ERR "%s: PCI master abort.\n",
501 dev->name);
502 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
503 printk(KERN_ERR "%s: PCI system error SERR#.\n",
504 dev->name);
505 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
506 printk(KERN_ERR "%s: PCI parity error.\n",
507 dev->name);
508
509 /* Write the error bits back to clear them. */
510 pci_cfg_stat &= (PCI_STATUS_PARITY |
511 PCI_STATUS_SIG_TARGET_ABORT |
512 PCI_STATUS_REC_TARGET_ABORT |
513 PCI_STATUS_REC_MASTER_ABORT |
514 PCI_STATUS_SIG_SYSTEM_ERROR |
515 PCI_STATUS_DETECTED_PARITY);
516 pci_write_config_word(gp->pdev,
517 PCI_STATUS, pci_cfg_stat);
518 }
519
520 /* For all PCI errors, we should reset the chip. */
521 return 1;
522 }
523
524 /* All non-normal interrupt conditions get serviced here.
525 * Returns non-zero if we should just exit the interrupt
526 * handler right now (ie. if we reset the card which invalidates
527 * all of the other original irq status bits).
528 */
529 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
530 {
531 if (gem_status & GREG_STAT_RXNOBUF) {
532 /* Frame arrived, no free RX buffers available. */
533 if (netif_msg_rx_err(gp))
534 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
535 gp->dev->name);
536 gp->net_stats.rx_dropped++;
537 }
538
539 if (gem_status & GREG_STAT_RXTAGERR) {
540 /* corrupt RX tag framing */
541 if (netif_msg_rx_err(gp))
542 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
543 gp->dev->name);
544 gp->net_stats.rx_errors++;
545
546 goto do_reset;
547 }
548
549 if (gem_status & GREG_STAT_PCS) {
550 if (gem_pcs_interrupt(dev, gp, gem_status))
551 goto do_reset;
552 }
553
554 if (gem_status & GREG_STAT_TXMAC) {
555 if (gem_txmac_interrupt(dev, gp, gem_status))
556 goto do_reset;
557 }
558
559 if (gem_status & GREG_STAT_RXMAC) {
560 if (gem_rxmac_interrupt(dev, gp, gem_status))
561 goto do_reset;
562 }
563
564 if (gem_status & GREG_STAT_MAC) {
565 if (gem_mac_interrupt(dev, gp, gem_status))
566 goto do_reset;
567 }
568
569 if (gem_status & GREG_STAT_MIF) {
570 if (gem_mif_interrupt(dev, gp, gem_status))
571 goto do_reset;
572 }
573
574 if (gem_status & GREG_STAT_PCIERR) {
575 if (gem_pci_interrupt(dev, gp, gem_status))
576 goto do_reset;
577 }
578
579 return 0;
580
581 do_reset:
582 gp->reset_task_pending = 2;
583 schedule_work(&gp->reset_task);
584
585 return 1;
586 }
587
588 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
589 {
590 int entry, limit;
591
592 if (netif_msg_intr(gp))
593 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
594 gp->dev->name, gem_status);
595
596 entry = gp->tx_old;
597 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
598 while (entry != limit) {
599 struct sk_buff *skb;
600 struct gem_txd *txd;
601 dma_addr_t dma_addr;
602 u32 dma_len;
603 int frag;
604
605 if (netif_msg_tx_done(gp))
606 printk(KERN_DEBUG "%s: tx done, slot %d\n",
607 gp->dev->name, entry);
608 skb = gp->tx_skbs[entry];
609 if (skb_shinfo(skb)->nr_frags) {
610 int last = entry + skb_shinfo(skb)->nr_frags;
611 int walk = entry;
612 int incomplete = 0;
613
614 last &= (TX_RING_SIZE - 1);
615 for (;;) {
616 walk = NEXT_TX(walk);
617 if (walk == limit)
618 incomplete = 1;
619 if (walk == last)
620 break;
621 }
622 if (incomplete)
623 break;
624 }
625 gp->tx_skbs[entry] = NULL;
626 gp->net_stats.tx_bytes += skb->len;
627
628 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
629 txd = &gp->init_block->txd[entry];
630
631 dma_addr = le64_to_cpu(txd->buffer);
632 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
633
634 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
635 entry = NEXT_TX(entry);
636 }
637
638 gp->net_stats.tx_packets++;
639 dev_kfree_skb_irq(skb);
640 }
641 gp->tx_old = entry;
642
643 if (netif_queue_stopped(dev) &&
644 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
645 netif_wake_queue(dev);
646 }
647
648 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
649 {
650 int cluster_start, curr, count, kick;
651
652 cluster_start = curr = (gp->rx_new & ~(4 - 1));
653 count = 0;
654 kick = -1;
655 while (curr != limit) {
656 curr = NEXT_RX(curr);
657 if (++count == 4) {
658 struct gem_rxd *rxd =
659 &gp->init_block->rxd[cluster_start];
660 for (;;) {
661 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
662 rxd++;
663 cluster_start = NEXT_RX(cluster_start);
664 if (cluster_start == curr)
665 break;
666 }
667 kick = curr;
668 count = 0;
669 }
670 }
671 if (kick >= 0)
672 writel(kick, gp->regs + RXDMA_KICK);
673 }
674
675 static void gem_rx(struct gem *gp)
676 {
677 int entry, drops;
678
679 if (netif_msg_intr(gp))
680 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
681 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
682
683 entry = gp->rx_new;
684 drops = 0;
685 for (;;) {
686 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
687 struct sk_buff *skb;
688 u64 status = cpu_to_le64(rxd->status_word);
689 dma_addr_t dma_addr;
690 int len;
691
692 if ((status & RXDCTRL_OWN) != 0)
693 break;
694
695 skb = gp->rx_skbs[entry];
696
697 len = (status & RXDCTRL_BUFSZ) >> 16;
698 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
699 gp->net_stats.rx_errors++;
700 if (len < ETH_ZLEN)
701 gp->net_stats.rx_length_errors++;
702 if (len & RXDCTRL_BAD)
703 gp->net_stats.rx_crc_errors++;
704
705 /* We'll just return it to GEM. */
706 drop_it:
707 gp->net_stats.rx_dropped++;
708 goto next;
709 }
710
711 dma_addr = cpu_to_le64(rxd->buffer);
712 if (len > RX_COPY_THRESHOLD) {
713 struct sk_buff *new_skb;
714
715 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
716 if (new_skb == NULL) {
717 drops++;
718 goto drop_it;
719 }
720 pci_unmap_page(gp->pdev, dma_addr,
721 RX_BUF_ALLOC_SIZE(gp),
722 PCI_DMA_FROMDEVICE);
723 gp->rx_skbs[entry] = new_skb;
724 new_skb->dev = gp->dev;
725 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
726 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
727 virt_to_page(new_skb->data),
728 ((unsigned long) new_skb->data &
729 ~PAGE_MASK),
730 RX_BUF_ALLOC_SIZE(gp),
731 PCI_DMA_FROMDEVICE));
732 skb_reserve(new_skb, RX_OFFSET);
733
734 /* Trim the original skb for the netif. */
735 skb_trim(skb, len);
736 } else {
737 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
738
739 if (copy_skb == NULL) {
740 drops++;
741 goto drop_it;
742 }
743
744 copy_skb->dev = gp->dev;
745 skb_reserve(copy_skb, 2);
746 skb_put(copy_skb, len);
747 pci_dma_sync_single(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
748 memcpy(copy_skb->data, skb->data, len);
749
750 /* We'll reuse the original ring buffer. */
751 skb = copy_skb;
752 }
753
754 skb->csum = ntohs((status & RXDCTRL_TCPCSUM) ^ 0xffff);
755 skb->ip_summed = CHECKSUM_HW;
756 skb->protocol = eth_type_trans(skb, gp->dev);
757 netif_rx(skb);
758
759 gp->net_stats.rx_packets++;
760 gp->net_stats.rx_bytes += len;
761 gp->dev->last_rx = jiffies;
762
763 next:
764 entry = NEXT_RX(entry);
765 }
766
767 gem_post_rxds(gp, entry);
768
769 gp->rx_new = entry;
770
771 if (drops)
772 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
773 gp->dev->name);
774 }
775
776 static irqreturn_t gem_interrupt(int irq, void *dev_id, struct pt_regs *regs)
777 {
778 struct net_device *dev = dev_id;
779 struct gem *gp = dev->priv;
780 u32 gem_status = readl(gp->regs + GREG_STAT);
781
782 spin_lock(&gp->lock);
783
784 if (gem_status & GREG_STAT_ABNORMAL) {
785 if (gem_abnormal_irq(dev, gp, gem_status))
786 goto out;
787 }
788 if (gem_status & (GREG_STAT_TXALL | GREG_STAT_TXINTME))
789 gem_tx(dev, gp, gem_status);
790 if (gem_status & GREG_STAT_RXDONE)
791 gem_rx(gp);
792
793 out:
794 spin_unlock(&gp->lock);
795
796 return IRQ_HANDLED;
797 }
798
799 static void gem_tx_timeout(struct net_device *dev)
800 {
801 struct gem *gp = dev->priv;
802
803 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
804 if (!gp->hw_running) {
805 printk("%s: hrm.. hw not running !\n", dev->name);
806 return;
807 }
808 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
809 dev->name,
810 readl(gp->regs + TXDMA_CFG),
811 readl(gp->regs + MAC_TXSTAT),
812 readl(gp->regs + MAC_TXCFG));
813 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
814 dev->name,
815 readl(gp->regs + RXDMA_CFG),
816 readl(gp->regs + MAC_RXSTAT),
817 readl(gp->regs + MAC_RXCFG));
818
819 spin_lock_irq(&gp->lock);
820
821 gp->reset_task_pending = 2;
822 schedule_work(&gp->reset_task);
823
824 spin_unlock_irq(&gp->lock);
825 }
826
827 static __inline__ int gem_intme(int entry)
828 {
829 /* Algorithm: IRQ every 1/2 of descriptors. */
830 if (!(entry & ((TX_RING_SIZE>>1)-1)))
831 return 1;
832
833 return 0;
834 }
835
836 static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
837 {
838 struct gem *gp = dev->priv;
839 int entry;
840 u64 ctrl;
841
842 ctrl = 0;
843 if (skb->ip_summed == CHECKSUM_HW) {
844 u64 csum_start_off, csum_stuff_off;
845
846 csum_start_off = (u64) (skb->h.raw - skb->data);
847 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
848
849 ctrl = (TXDCTRL_CENAB |
850 (csum_start_off << 15) |
851 (csum_stuff_off << 21));
852 }
853
854 spin_lock_irq(&gp->lock);
855
856 /* This is a hard error, log it. */
857 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
858 netif_stop_queue(dev);
859 spin_unlock_irq(&gp->lock);
860 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
861 dev->name);
862 return 1;
863 }
864
865 entry = gp->tx_new;
866 gp->tx_skbs[entry] = skb;
867
868 if (skb_shinfo(skb)->nr_frags == 0) {
869 struct gem_txd *txd = &gp->init_block->txd[entry];
870 dma_addr_t mapping;
871 u32 len;
872
873 len = skb->len;
874 mapping = pci_map_page(gp->pdev,
875 virt_to_page(skb->data),
876 ((unsigned long) skb->data &
877 ~PAGE_MASK),
878 len, PCI_DMA_TODEVICE);
879 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
880 if (gem_intme(entry))
881 ctrl |= TXDCTRL_INTME;
882 txd->buffer = cpu_to_le64(mapping);
883 txd->control_word = cpu_to_le64(ctrl);
884 entry = NEXT_TX(entry);
885 } else {
886 struct gem_txd *txd;
887 u32 first_len;
888 u64 intme;
889 dma_addr_t first_mapping;
890 int frag, first_entry = entry;
891
892 intme = 0;
893 if (gem_intme(entry))
894 intme |= TXDCTRL_INTME;
895
896 /* We must give this initial chunk to the device last.
897 * Otherwise we could race with the device.
898 */
899 first_len = skb_headlen(skb);
900 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
901 ((unsigned long) skb->data & ~PAGE_MASK),
902 first_len, PCI_DMA_TODEVICE);
903 entry = NEXT_TX(entry);
904
905 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
906 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
907 u32 len;
908 dma_addr_t mapping;
909 u64 this_ctrl;
910
911 len = this_frag->size;
912 mapping = pci_map_page(gp->pdev,
913 this_frag->page,
914 this_frag->page_offset,
915 len, PCI_DMA_TODEVICE);
916 this_ctrl = ctrl;
917 if (frag == skb_shinfo(skb)->nr_frags - 1)
918 this_ctrl |= TXDCTRL_EOF;
919
920 txd = &gp->init_block->txd[entry];
921 txd->buffer = cpu_to_le64(mapping);
922 txd->control_word = cpu_to_le64(this_ctrl | len);
923
924 if (gem_intme(entry))
925 intme |= TXDCTRL_INTME;
926
927 entry = NEXT_TX(entry);
928 }
929 txd = &gp->init_block->txd[first_entry];
930 txd->buffer = cpu_to_le64(first_mapping);
931 txd->control_word =
932 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
933 }
934
935 gp->tx_new = entry;
936 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
937 netif_stop_queue(dev);
938
939 if (netif_msg_tx_queued(gp))
940 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
941 dev->name, entry, skb->len);
942 writel(gp->tx_new, gp->regs + TXDMA_KICK);
943 spin_unlock_irq(&gp->lock);
944
945 dev->trans_start = jiffies;
946
947 return 0;
948 }
949
950 /* Jumbo-grams don't seem to work :-( */
951 #define GEM_MIN_MTU 68
952 #if 1
953 #define GEM_MAX_MTU 1500
954 #else
955 #define GEM_MAX_MTU 9000
956 #endif
957
958 static int gem_change_mtu(struct net_device *dev, int new_mtu)
959 {
960 struct gem *gp = dev->priv;
961
962 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
963 return -EINVAL;
964
965 if (!netif_running(dev) || !netif_device_present(dev)) {
966 /* We'll just catch it later when the
967 * device is up'd or resumed.
968 */
969 dev->mtu = new_mtu;
970 return 0;
971 }
972
973 spin_lock_irq(&gp->lock);
974 dev->mtu = new_mtu;
975 gp->reset_task_pending = 1;
976 schedule_work(&gp->reset_task);
977 spin_unlock_irq(&gp->lock);
978
979 flush_scheduled_work();
980
981 return 0;
982 }
983
984 #define STOP_TRIES 32
985
986 /* Must be invoked under gp->lock. */
987 static void gem_stop(struct gem *gp)
988 {
989 int limit;
990 u32 val;
991
992 /* Make sure we won't get any more interrupts */
993 writel(0xffffffff, gp->regs + GREG_IMASK);
994
995 /* Reset the chip */
996 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
997 gp->regs + GREG_SWRST);
998
999 limit = STOP_TRIES;
1000
1001 do {
1002 udelay(20);
1003 val = readl(gp->regs + GREG_SWRST);
1004 if (limit-- <= 0)
1005 break;
1006 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1007
1008 if (limit <= 0)
1009 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1010 }
1011
1012 /* Must be invoked under gp->lock. */
1013 static void gem_start_dma(struct gem *gp)
1014 {
1015 unsigned long val;
1016
1017 /* We are ready to rock, turn everything on. */
1018 val = readl(gp->regs + TXDMA_CFG);
1019 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1020 val = readl(gp->regs + RXDMA_CFG);
1021 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1022 val = readl(gp->regs + MAC_TXCFG);
1023 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1024 val = readl(gp->regs + MAC_RXCFG);
1025 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1026
1027 (void) readl(gp->regs + MAC_RXCFG);
1028 udelay(100);
1029
1030 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
1031
1032 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1033
1034 }
1035
1036
1037 /* Must be invoked under gp->lock. */
1038 // XXX dbl check what that function should do when called on PCS PHY
1039 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1040 {
1041 u32 advertise, features;
1042 int autoneg;
1043 int speed;
1044 int duplex;
1045
1046 if (gp->phy_type != phy_mii_mdio0 &&
1047 gp->phy_type != phy_mii_mdio1)
1048 goto non_mii;
1049
1050 /* Setup advertise */
1051 if (found_mii_phy(gp))
1052 features = gp->phy_mii.def->features;
1053 else
1054 features = 0;
1055
1056 advertise = features & ADVERTISE_MASK;
1057 if (gp->phy_mii.advertising != 0)
1058 advertise &= gp->phy_mii.advertising;
1059
1060 autoneg = gp->want_autoneg;
1061 speed = gp->phy_mii.speed;
1062 duplex = gp->phy_mii.duplex;
1063
1064 /* Setup link parameters */
1065 if (!ep)
1066 goto start_aneg;
1067 if (ep->autoneg == AUTONEG_ENABLE) {
1068 advertise = ep->advertising;
1069 autoneg = 1;
1070 } else {
1071 autoneg = 0;
1072 speed = ep->speed;
1073 duplex = ep->duplex;
1074 }
1075
1076 start_aneg:
1077 /* Sanitize settings based on PHY capabilities */
1078 if ((features & SUPPORTED_Autoneg) == 0)
1079 autoneg = 0;
1080 if (speed == SPEED_1000 &&
1081 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1082 speed = SPEED_100;
1083 if (speed == SPEED_100 &&
1084 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1085 speed = SPEED_10;
1086 if (duplex == DUPLEX_FULL &&
1087 !(features & (SUPPORTED_1000baseT_Full |
1088 SUPPORTED_100baseT_Full |
1089 SUPPORTED_10baseT_Full)))
1090 duplex = DUPLEX_HALF;
1091 if (speed == 0)
1092 speed = SPEED_10;
1093
1094 /* If HW is down, we don't try to actually setup the PHY, we
1095 * just store the settings
1096 */
1097 if (!gp->hw_running) {
1098 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1099 gp->phy_mii.speed = speed;
1100 gp->phy_mii.duplex = duplex;
1101 return;
1102 }
1103
1104 /* Configure PHY & start aneg */
1105 gp->want_autoneg = autoneg;
1106 if (autoneg) {
1107 if (found_mii_phy(gp))
1108 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1109 gp->lstate = link_aneg;
1110 } else {
1111 if (found_mii_phy(gp))
1112 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1113 gp->lstate = link_force_ok;
1114 }
1115
1116 non_mii:
1117 gp->timer_ticks = 0;
1118 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1119 }
1120
1121 /* A link-up condition has occurred, initialize and enable the
1122 * rest of the chip.
1123 *
1124 * Must be invoked under gp->lock.
1125 */
1126 static int gem_set_link_modes(struct gem *gp)
1127 {
1128 u32 val;
1129 int full_duplex, speed, pause;
1130
1131 full_duplex = 0;
1132 speed = SPEED_10;
1133 pause = 0;
1134
1135 if (found_mii_phy(gp)) {
1136 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1137 return 1;
1138 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1139 speed = gp->phy_mii.speed;
1140 pause = gp->phy_mii.pause;
1141 } else if (gp->phy_type == phy_serialink ||
1142 gp->phy_type == phy_serdes) {
1143 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1144
1145 if (pcs_lpa & PCS_MIIADV_FD)
1146 full_duplex = 1;
1147 speed = SPEED_1000;
1148 }
1149
1150 if (netif_msg_link(gp))
1151 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1152 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1153
1154 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1155 if (full_duplex) {
1156 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1157 } else {
1158 /* MAC_TXCFG_NBO must be zero. */
1159 }
1160 writel(val, gp->regs + MAC_TXCFG);
1161
1162 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1163 if (!full_duplex &&
1164 (gp->phy_type == phy_mii_mdio0 ||
1165 gp->phy_type == phy_mii_mdio1)) {
1166 val |= MAC_XIFCFG_DISE;
1167 } else if (full_duplex) {
1168 val |= MAC_XIFCFG_FLED;
1169 }
1170
1171 if (speed == SPEED_1000)
1172 val |= (MAC_XIFCFG_GMII);
1173
1174 writel(val, gp->regs + MAC_XIFCFG);
1175
1176 /* If gigabit and half-duplex, enable carrier extension
1177 * mode. Else, disable it.
1178 */
1179 if (speed == SPEED_1000 && !full_duplex) {
1180 val = readl(gp->regs + MAC_TXCFG);
1181 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1182
1183 val = readl(gp->regs + MAC_RXCFG);
1184 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1185 } else {
1186 val = readl(gp->regs + MAC_TXCFG);
1187 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1188
1189 val = readl(gp->regs + MAC_RXCFG);
1190 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1191 }
1192
1193 if (gp->phy_type == phy_serialink ||
1194 gp->phy_type == phy_serdes) {
1195 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1196
1197 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1198 pause = 1;
1199 }
1200
1201 if (netif_msg_link(gp)) {
1202 if (pause) {
1203 printk(KERN_INFO "%s: Pause is enabled "
1204 "(rxfifo: %d off: %d on: %d)\n",
1205 gp->dev->name,
1206 gp->rx_fifo_sz,
1207 gp->rx_pause_off,
1208 gp->rx_pause_on);
1209 } else {
1210 printk(KERN_INFO "%s: Pause is disabled\n",
1211 gp->dev->name);
1212 }
1213 }
1214
1215 if (!full_duplex)
1216 writel(512, gp->regs + MAC_STIME);
1217 else
1218 writel(64, gp->regs + MAC_STIME);
1219 val = readl(gp->regs + MAC_MCCFG);
1220 if (pause)
1221 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1222 else
1223 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1224 writel(val, gp->regs + MAC_MCCFG);
1225
1226 gem_start_dma(gp);
1227
1228 return 0;
1229 }
1230
1231 /* Must be invoked under gp->lock. */
1232 static int gem_mdio_link_not_up(struct gem *gp)
1233 {
1234 switch (gp->lstate) {
1235 case link_force_ret:
1236 if (netif_msg_link(gp))
1237 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1238 " forced mode\n", gp->dev->name);
1239 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1240 gp->last_forced_speed, DUPLEX_HALF);
1241 gp->timer_ticks = 5;
1242 gp->lstate = link_force_ok;
1243 return 0;
1244 case link_aneg:
1245 if (netif_msg_link(gp))
1246 printk(KERN_INFO "%s: switching to forced 100bt\n",
1247 gp->dev->name);
1248 /* Try forced modes. */
1249 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1250 DUPLEX_HALF);
1251 gp->timer_ticks = 5;
1252 gp->lstate = link_force_try;
1253 return 0;
1254 case link_force_try:
1255 /* Downgrade from 100 to 10 Mbps if necessary.
1256 * If already at 10Mbps, warn user about the
1257 * situation every 10 ticks.
1258 */
1259 if (gp->phy_mii.speed == SPEED_100) {
1260 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1261 DUPLEX_HALF);
1262 gp->timer_ticks = 5;
1263 if (netif_msg_link(gp))
1264 printk(KERN_INFO "%s: switching to forced 10bt\n",
1265 gp->dev->name);
1266 return 0;
1267 } else
1268 return 1;
1269 default:
1270 return 0;
1271 }
1272 }
1273
1274 static void gem_init_rings(struct gem *);
1275 static void gem_init_hw(struct gem *, int);
1276
1277 static void gem_reset_task(void *data)
1278 {
1279 struct gem *gp = (struct gem *) data;
1280
1281 /* The link went down, we reset the ring, but keep
1282 * DMA stopped. Todo: Use this function for reset
1283 * on error as well.
1284 */
1285
1286 spin_lock_irq(&gp->lock);
1287
1288 if (gp->hw_running && gp->opened) {
1289 /* Make sure we don't get interrupts or tx packets */
1290 netif_stop_queue(gp->dev);
1291
1292 writel(0xffffffff, gp->regs + GREG_IMASK);
1293
1294 /* Reset the chip & rings */
1295 gem_stop(gp);
1296 gem_init_rings(gp);
1297
1298 gem_init_hw(gp,
1299 (gp->reset_task_pending == 2));
1300
1301 netif_wake_queue(gp->dev);
1302 }
1303 gp->reset_task_pending = 0;
1304
1305 spin_unlock_irq(&gp->lock);
1306 }
1307
1308 static void gem_link_timer(unsigned long data)
1309 {
1310 struct gem *gp = (struct gem *) data;
1311 int restart_aneg = 0;
1312
1313 if (!gp->hw_running)
1314 return;
1315
1316 spin_lock_irq(&gp->lock);
1317
1318 /* If the link of task is still pending, we just
1319 * reschedule the link timer
1320 */
1321 if (gp->reset_task_pending)
1322 goto restart;
1323
1324 if (gp->phy_type == phy_serialink ||
1325 gp->phy_type == phy_serdes) {
1326 u32 val = readl(gp->regs + PCS_MIISTAT);
1327
1328 if (!(val & PCS_MIISTAT_LS))
1329 val = readl(gp->regs + PCS_MIISTAT);
1330
1331 if ((val & PCS_MIISTAT_LS) != 0) {
1332 gp->lstate = link_up;
1333 netif_carrier_on(gp->dev);
1334 if (gp->opened)
1335 (void)gem_set_link_modes(gp);
1336 }
1337 goto restart;
1338 }
1339 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1340 /* Ok, here we got a link. If we had it due to a forced
1341 * fallback, and we were configured for autoneg, we do
1342 * retry a short autoneg pass. If you know your hub is
1343 * broken, use ethtool ;)
1344 */
1345 if (gp->lstate == link_force_try && gp->want_autoneg) {
1346 gp->lstate = link_force_ret;
1347 gp->last_forced_speed = gp->phy_mii.speed;
1348 gp->timer_ticks = 5;
1349 if (netif_msg_link(gp))
1350 printk(KERN_INFO "%s: Got link after fallback, retrying"
1351 " autoneg once...\n", gp->dev->name);
1352 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1353 } else if (gp->lstate != link_up) {
1354 gp->lstate = link_up;
1355 netif_carrier_on(gp->dev);
1356 if (gp->opened && gem_set_link_modes(gp))
1357 restart_aneg = 1;
1358 }
1359 } else {
1360 /* If the link was previously up, we restart the
1361 * whole process
1362 */
1363 if (gp->lstate == link_up) {
1364 gp->lstate = link_down;
1365 if (netif_msg_link(gp))
1366 printk(KERN_INFO "%s: Link down\n",
1367 gp->dev->name);
1368 netif_carrier_off(gp->dev);
1369 gp->reset_task_pending = 2;
1370 schedule_work(&gp->reset_task);
1371 restart_aneg = 1;
1372 } else if (++gp->timer_ticks > 10) {
1373 if (found_mii_phy(gp))
1374 restart_aneg = gem_mdio_link_not_up(gp);
1375 else
1376 restart_aneg = 1;
1377 }
1378 }
1379 if (restart_aneg) {
1380 gem_begin_auto_negotiation(gp, NULL);
1381 goto out_unlock;
1382 }
1383 restart:
1384 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1385 out_unlock:
1386 spin_unlock_irq(&gp->lock);
1387 }
1388
1389 /* Must be invoked under gp->lock. */
1390 static void gem_clean_rings(struct gem *gp)
1391 {
1392 struct gem_init_block *gb = gp->init_block;
1393 struct sk_buff *skb;
1394 int i;
1395 dma_addr_t dma_addr;
1396
1397 for (i = 0; i < RX_RING_SIZE; i++) {
1398 struct gem_rxd *rxd;
1399
1400 rxd = &gb->rxd[i];
1401 if (gp->rx_skbs[i] != NULL) {
1402 skb = gp->rx_skbs[i];
1403 dma_addr = le64_to_cpu(rxd->buffer);
1404 pci_unmap_page(gp->pdev, dma_addr,
1405 RX_BUF_ALLOC_SIZE(gp),
1406 PCI_DMA_FROMDEVICE);
1407 dev_kfree_skb_any(skb);
1408 gp->rx_skbs[i] = NULL;
1409 }
1410 rxd->status_word = 0;
1411 rxd->buffer = 0;
1412 }
1413
1414 for (i = 0; i < TX_RING_SIZE; i++) {
1415 if (gp->tx_skbs[i] != NULL) {
1416 struct gem_txd *txd;
1417 int frag;
1418
1419 skb = gp->tx_skbs[i];
1420 gp->tx_skbs[i] = NULL;
1421
1422 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1423 int ent = i & (TX_RING_SIZE - 1);
1424
1425 txd = &gb->txd[ent];
1426 dma_addr = le64_to_cpu(txd->buffer);
1427 pci_unmap_page(gp->pdev, dma_addr,
1428 le64_to_cpu(txd->control_word) &
1429 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1430
1431 if (frag != skb_shinfo(skb)->nr_frags)
1432 i++;
1433 }
1434 dev_kfree_skb_any(skb);
1435 }
1436 }
1437 }
1438
1439 /* Must be invoked under gp->lock. */
1440 static void gem_init_rings(struct gem *gp)
1441 {
1442 struct gem_init_block *gb = gp->init_block;
1443 struct net_device *dev = gp->dev;
1444 int i;
1445 dma_addr_t dma_addr;
1446
1447 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1448
1449 gem_clean_rings(gp);
1450
1451 for (i = 0; i < RX_RING_SIZE; i++) {
1452 struct sk_buff *skb;
1453 struct gem_rxd *rxd = &gb->rxd[i];
1454
1455 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1456 if (!skb) {
1457 rxd->buffer = 0;
1458 rxd->status_word = 0;
1459 continue;
1460 }
1461
1462 gp->rx_skbs[i] = skb;
1463 skb->dev = dev;
1464 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1465 dma_addr = pci_map_page(gp->pdev,
1466 virt_to_page(skb->data),
1467 ((unsigned long) skb->data &
1468 ~PAGE_MASK),
1469 RX_BUF_ALLOC_SIZE(gp),
1470 PCI_DMA_FROMDEVICE);
1471 rxd->buffer = cpu_to_le64(dma_addr);
1472 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1473 skb_reserve(skb, RX_OFFSET);
1474 }
1475
1476 for (i = 0; i < TX_RING_SIZE; i++) {
1477 struct gem_txd *txd = &gb->txd[i];
1478
1479 txd->control_word = 0;
1480 txd->buffer = 0;
1481 }
1482 }
1483
1484 /* Must be invoked under gp->lock. */
1485 static void gem_init_phy(struct gem *gp)
1486 {
1487 u32 mifcfg;
1488
1489 /* Revert MIF CFG setting done on stop_phy */
1490 mifcfg = readl(gp->regs + MIF_CFG);
1491 mifcfg &= ~MIF_CFG_BBMODE;
1492 writel(mifcfg, gp->regs + MIF_CFG);
1493
1494 #ifdef CONFIG_PPC_PMAC
1495 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1496 int i, j;
1497
1498 /* Those delay sucks, the HW seem to love them though, I'll
1499 * serisouly consider breaking some locks here to be able
1500 * to schedule instead
1501 */
1502 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1503 mdelay(10);
1504 for (j = 0; j < 3; j++) {
1505 /* Some PHYs used by apple have problem getting back to us,
1506 * we _know_ it's actually at addr 0, that's a hack, but
1507 * it helps to do that reset now. I suspect some motherboards
1508 * don't wire the PHY reset line properly, thus the PHY doesn't
1509 * come back with the above pmac_call_feature.
1510 */
1511 gp->mii_phy_addr = 0;
1512 phy_write(gp, MII_BMCR, BMCR_RESET);
1513 /* We should probably break some locks here and schedule... */
1514 mdelay(10);
1515 for (i = 0; i < 32; i++) {
1516 gp->mii_phy_addr = i;
1517 if (phy_read(gp, MII_BMCR) != 0xffff)
1518 break;
1519 }
1520 if (i == 32) {
1521 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1522 gp->dev->name);
1523 gp->mii_phy_addr = 0;
1524 } else
1525 break;
1526 }
1527 }
1528 #endif /* CONFIG_PPC_PMAC */
1529
1530 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1531 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1532 u32 val;
1533
1534 /* Init datapath mode register. */
1535 if (gp->phy_type == phy_mii_mdio0 ||
1536 gp->phy_type == phy_mii_mdio1) {
1537 val = PCS_DMODE_MGM;
1538 } else if (gp->phy_type == phy_serialink) {
1539 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1540 } else {
1541 val = PCS_DMODE_ESM;
1542 }
1543
1544 writel(val, gp->regs + PCS_DMODE);
1545 }
1546
1547 if (gp->phy_type == phy_mii_mdio0 ||
1548 gp->phy_type == phy_mii_mdio1) {
1549 // XXX check for errors
1550 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1551
1552 /* Init PHY */
1553 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1554 gp->phy_mii.def->ops->init(&gp->phy_mii);
1555 } else {
1556 u32 val;
1557 int limit;
1558
1559 /* Reset PCS unit. */
1560 val = readl(gp->regs + PCS_MIICTRL);
1561 val |= PCS_MIICTRL_RST;
1562 writeb(val, gp->regs + PCS_MIICTRL);
1563
1564 limit = 32;
1565 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1566 udelay(100);
1567 if (limit-- <= 0)
1568 break;
1569 }
1570 if (limit <= 0)
1571 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1572 gp->dev->name);
1573
1574 /* Make sure PCS is disabled while changing advertisement
1575 * configuration.
1576 */
1577 val = readl(gp->regs + PCS_CFG);
1578 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1579 writel(val, gp->regs + PCS_CFG);
1580
1581 /* Advertise all capabilities except assymetric
1582 * pause.
1583 */
1584 val = readl(gp->regs + PCS_MIIADV);
1585 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1586 PCS_MIIADV_SP | PCS_MIIADV_AP);
1587 writel(val, gp->regs + PCS_MIIADV);
1588
1589 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1590 * and re-enable PCS.
1591 */
1592 val = readl(gp->regs + PCS_MIICTRL);
1593 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1594 val &= ~PCS_MIICTRL_WB;
1595 writel(val, gp->regs + PCS_MIICTRL);
1596
1597 val = readl(gp->regs + PCS_CFG);
1598 val |= PCS_CFG_ENABLE;
1599 writel(val, gp->regs + PCS_CFG);
1600
1601 /* Make sure serialink loopback is off. The meaning
1602 * of this bit is logically inverted based upon whether
1603 * you are in Serialink or SERDES mode.
1604 */
1605 val = readl(gp->regs + PCS_SCTRL);
1606 if (gp->phy_type == phy_serialink)
1607 val &= ~PCS_SCTRL_LOOP;
1608 else
1609 val |= PCS_SCTRL_LOOP;
1610 writel(val, gp->regs + PCS_SCTRL);
1611 }
1612 }
1613
1614 /* Must be invoked under gp->lock. */
1615 static void gem_init_dma(struct gem *gp)
1616 {
1617 u64 desc_dma = (u64) gp->gblock_dvma;
1618 u32 val;
1619
1620 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1621 writel(val, gp->regs + TXDMA_CFG);
1622
1623 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1624 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1625 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1626
1627 writel(0, gp->regs + TXDMA_KICK);
1628
1629 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1630 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1631 writel(val, gp->regs + RXDMA_CFG);
1632
1633 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1634 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1635
1636 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1637
1638 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1639 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1640 writel(val, gp->regs + RXDMA_PTHRESH);
1641
1642 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1643 writel(((5 & RXDMA_BLANK_IPKTS) |
1644 ((8 << 12) & RXDMA_BLANK_ITIME)),
1645 gp->regs + RXDMA_BLANK);
1646 else
1647 writel(((5 & RXDMA_BLANK_IPKTS) |
1648 ((4 << 12) & RXDMA_BLANK_ITIME)),
1649 gp->regs + RXDMA_BLANK);
1650 }
1651
1652 /* Must be invoked under gp->lock. */
1653 static u32
1654 gem_setup_multicast(struct gem *gp)
1655 {
1656 u32 rxcfg = 0;
1657 int i;
1658
1659 if ((gp->dev->flags & IFF_ALLMULTI) ||
1660 (gp->dev->mc_count > 256)) {
1661 for (i=0; i<16; i++)
1662 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1663 rxcfg |= MAC_RXCFG_HFE;
1664 } else if (gp->dev->flags & IFF_PROMISC) {
1665 rxcfg |= MAC_RXCFG_PROM;
1666 } else {
1667 u16 hash_table[16];
1668 u32 crc;
1669 struct dev_mc_list *dmi = gp->dev->mc_list;
1670 int i;
1671
1672 for (i = 0; i < 16; i++)
1673 hash_table[i] = 0;
1674
1675 for (i = 0; i < gp->dev->mc_count; i++) {
1676 char *addrs = dmi->dmi_addr;
1677
1678 dmi = dmi->next;
1679
1680 if (!(*addrs & 1))
1681 continue;
1682
1683 crc = ether_crc_le(6, addrs);
1684 crc >>= 24;
1685 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1686 }
1687 for (i=0; i<16; i++)
1688 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1689 rxcfg |= MAC_RXCFG_HFE;
1690 }
1691
1692 return rxcfg;
1693 }
1694
1695 /* Must be invoked under gp->lock. */
1696 static void gem_init_mac(struct gem *gp)
1697 {
1698 unsigned char *e = &gp->dev->dev_addr[0];
1699
1700 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1701
1702 writel(0x00, gp->regs + MAC_IPG0);
1703 writel(0x08, gp->regs + MAC_IPG1);
1704 writel(0x04, gp->regs + MAC_IPG2);
1705 writel(0x40, gp->regs + MAC_STIME);
1706 writel(0x40, gp->regs + MAC_MINFSZ);
1707
1708 /* Ethernet payload + header + FCS + optional VLAN tag. */
1709 writel(0x20000000 | (gp->dev->mtu + ETH_HLEN + 4 + 4), gp->regs + MAC_MAXFSZ);
1710
1711 writel(0x07, gp->regs + MAC_PASIZE);
1712 writel(0x04, gp->regs + MAC_JAMSIZE);
1713 writel(0x10, gp->regs + MAC_ATTLIM);
1714 writel(0x8808, gp->regs + MAC_MCTYPE);
1715
1716 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1717
1718 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1719 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1720 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1721
1722 writel(0, gp->regs + MAC_ADDR3);
1723 writel(0, gp->regs + MAC_ADDR4);
1724 writel(0, gp->regs + MAC_ADDR5);
1725
1726 writel(0x0001, gp->regs + MAC_ADDR6);
1727 writel(0xc200, gp->regs + MAC_ADDR7);
1728 writel(0x0180, gp->regs + MAC_ADDR8);
1729
1730 writel(0, gp->regs + MAC_AFILT0);
1731 writel(0, gp->regs + MAC_AFILT1);
1732 writel(0, gp->regs + MAC_AFILT2);
1733 writel(0, gp->regs + MAC_AF21MSK);
1734 writel(0, gp->regs + MAC_AF0MSK);
1735
1736 gp->mac_rx_cfg = gem_setup_multicast(gp);
1737 #ifdef STRIP_FCS
1738 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1739 #endif
1740 writel(0, gp->regs + MAC_NCOLL);
1741 writel(0, gp->regs + MAC_FASUCC);
1742 writel(0, gp->regs + MAC_ECOLL);
1743 writel(0, gp->regs + MAC_LCOLL);
1744 writel(0, gp->regs + MAC_DTIMER);
1745 writel(0, gp->regs + MAC_PATMPS);
1746 writel(0, gp->regs + MAC_RFCTR);
1747 writel(0, gp->regs + MAC_LERR);
1748 writel(0, gp->regs + MAC_AERR);
1749 writel(0, gp->regs + MAC_FCSERR);
1750 writel(0, gp->regs + MAC_RXCVERR);
1751
1752 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1753 * them once a link is established.
1754 */
1755 writel(0, gp->regs + MAC_TXCFG);
1756 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1757 writel(0, gp->regs + MAC_MCCFG);
1758 writel(0, gp->regs + MAC_XIFCFG);
1759
1760 /* Setup MAC interrupts. We want to get all of the interesting
1761 * counter expiration events, but we do not want to hear about
1762 * normal rx/tx as the DMA engine tells us that.
1763 */
1764 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1765 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1766
1767 /* Don't enable even the PAUSE interrupts for now, we
1768 * make no use of those events other than to record them.
1769 */
1770 writel(0xffffffff, gp->regs + MAC_MCMASK);
1771 }
1772
1773 /* Must be invoked under gp->lock. */
1774 static void gem_init_pause_thresholds(struct gem *gp)
1775 {
1776 /* Calculate pause thresholds. Setting the OFF threshold to the
1777 * full RX fifo size effectively disables PAUSE generation which
1778 * is what we do for 10/100 only GEMs which have FIFOs too small
1779 * to make real gains from PAUSE.
1780 */
1781 if (gp->rx_fifo_sz <= (2 * 1024)) {
1782 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1783 } else {
1784 int max_frame = (gp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
1785 int off = (gp->rx_fifo_sz - (max_frame * 2));
1786 int on = off - max_frame;
1787
1788 gp->rx_pause_off = off;
1789 gp->rx_pause_on = on;
1790 }
1791
1792 {
1793 u32 cfg;
1794
1795 cfg = 0;
1796 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1797 cfg |= GREG_CFG_IBURST;
1798 #endif
1799 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1800 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1801 writel(cfg, gp->regs + GREG_CFG);
1802 }
1803 }
1804
1805 static int gem_check_invariants(struct gem *gp)
1806 {
1807 struct pci_dev *pdev = gp->pdev;
1808 u32 mif_cfg;
1809
1810 /* On Apple's sungem, we can't rely on registers as the chip
1811 * was been powered down by the firmware. The PHY is looked
1812 * up later on.
1813 */
1814 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1815 gp->phy_type = phy_mii_mdio0;
1816 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1817 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1818 gp->swrst_base = 0;
1819 return 0;
1820 }
1821
1822 mif_cfg = readl(gp->regs + MIF_CFG);
1823
1824 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1825 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1826 /* One of the MII PHYs _must_ be present
1827 * as this chip has no gigabit PHY.
1828 */
1829 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1830 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1831 mif_cfg);
1832 return -1;
1833 }
1834 }
1835
1836 /* Determine initial PHY interface type guess. MDIO1 is the
1837 * external PHY and thus takes precedence over MDIO0.
1838 */
1839
1840 if (mif_cfg & MIF_CFG_MDI1) {
1841 gp->phy_type = phy_mii_mdio1;
1842 mif_cfg |= MIF_CFG_PSELECT;
1843 writel(mif_cfg, gp->regs + MIF_CFG);
1844 } else if (mif_cfg & MIF_CFG_MDI0) {
1845 gp->phy_type = phy_mii_mdio0;
1846 mif_cfg &= ~MIF_CFG_PSELECT;
1847 writel(mif_cfg, gp->regs + MIF_CFG);
1848 } else {
1849 gp->phy_type = phy_serialink;
1850 }
1851 if (gp->phy_type == phy_mii_mdio1 ||
1852 gp->phy_type == phy_mii_mdio0) {
1853 int i;
1854
1855 for (i = 0; i < 32; i++) {
1856 gp->mii_phy_addr = i;
1857 if (phy_read(gp, MII_BMCR) != 0xffff)
1858 break;
1859 }
1860 if (i == 32) {
1861 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
1862 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
1863 return -1;
1864 }
1865 gp->phy_type = phy_serdes;
1866 }
1867 }
1868
1869 /* Fetch the FIFO configurations now too. */
1870 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1871 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1872
1873 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
1874 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1875 if (gp->tx_fifo_sz != (9 * 1024) ||
1876 gp->rx_fifo_sz != (20 * 1024)) {
1877 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
1878 gp->tx_fifo_sz, gp->rx_fifo_sz);
1879 return -1;
1880 }
1881 gp->swrst_base = 0;
1882 } else {
1883 if (gp->tx_fifo_sz != (2 * 1024) ||
1884 gp->rx_fifo_sz != (2 * 1024)) {
1885 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
1886 gp->tx_fifo_sz, gp->rx_fifo_sz);
1887 return -1;
1888 }
1889 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
1890 }
1891 }
1892
1893 return 0;
1894 }
1895
1896 /* Must be invoked under gp->lock. */
1897 static void gem_init_hw(struct gem *gp, int restart_link)
1898 {
1899 /* On Apple's gmac, I initialize the PHY only after
1900 * setting up the chip. It appears the gigabit PHYs
1901 * don't quite like beeing talked to on the GII when
1902 * the chip is not running, I suspect it might not
1903 * be clocked at that point. --BenH
1904 */
1905 if (restart_link)
1906 gem_init_phy(gp);
1907 gem_init_pause_thresholds(gp);
1908 gem_init_dma(gp);
1909 gem_init_mac(gp);
1910
1911 if (restart_link) {
1912 /* Default aneg parameters */
1913 gp->timer_ticks = 0;
1914 gp->lstate = link_down;
1915 netif_carrier_off(gp->dev);
1916
1917 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1918 gem_begin_auto_negotiation(gp, NULL);
1919 } else {
1920 if (gp->lstate == link_up) {
1921 netif_carrier_on(gp->dev);
1922 gem_set_link_modes(gp);
1923 }
1924 }
1925 }
1926
1927 #ifdef CONFIG_PPC_PMAC
1928 /* Enable the chip's clock and make sure it's config space is
1929 * setup properly. There appear to be no need to restore the
1930 * base addresses.
1931 */
1932 static void gem_apple_powerup(struct gem *gp)
1933 {
1934 u16 cmd;
1935 u32 mif_cfg;
1936
1937 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
1938
1939 current->state = TASK_UNINTERRUPTIBLE;
1940 schedule_timeout((21 * HZ) / 1000);
1941
1942 pci_read_config_word(gp->pdev, PCI_COMMAND, &cmd);
1943 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
1944 pci_write_config_word(gp->pdev, PCI_COMMAND, cmd);
1945 pci_write_config_byte(gp->pdev, PCI_LATENCY_TIMER, 6);
1946 pci_write_config_byte(gp->pdev, PCI_CACHE_LINE_SIZE, 8);
1947
1948 mdelay(1);
1949
1950 mif_cfg = readl(gp->regs + MIF_CFG);
1951 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1952 mif_cfg |= MIF_CFG_MDI0;
1953 writel(mif_cfg, gp->regs + MIF_CFG);
1954 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1955 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1956
1957 mdelay(1);
1958 }
1959
1960 /* Turn off the chip's clock */
1961 static void gem_apple_powerdown(struct gem *gp)
1962 {
1963 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
1964 }
1965
1966 #endif /* CONFIG_PPC_PMAC */
1967
1968 /* Must be invoked under gp->lock. */
1969 static void gem_stop_phy(struct gem *gp)
1970 {
1971 u32 mifcfg;
1972
1973 /* Make sure we aren't polling PHY status change. We
1974 * don't currently use that feature though
1975 */
1976 mifcfg = readl(gp->regs + MIF_CFG);
1977 mifcfg &= ~MIF_CFG_POLL;
1978 writel(mifcfg, gp->regs + MIF_CFG);
1979
1980 if (gp->wake_on_lan) {
1981 /* Setup wake-on-lan */
1982 } else
1983 writel(0, gp->regs + MAC_RXCFG);
1984 writel(0, gp->regs + MAC_TXCFG);
1985 writel(0, gp->regs + MAC_XIFCFG);
1986 writel(0, gp->regs + TXDMA_CFG);
1987 writel(0, gp->regs + RXDMA_CFG);
1988
1989 if (!gp->wake_on_lan) {
1990 gem_stop(gp);
1991 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
1992 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
1993 }
1994
1995 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
1996 gp->phy_mii.def->ops->suspend(&gp->phy_mii, 0 /* wake on lan options */);
1997
1998 if (!gp->wake_on_lan) {
1999 /* According to Apple, we must set the MDIO pins to this begnign
2000 * state or we may 1) eat more current, 2) damage some PHYs
2001 */
2002 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2003 writel(0, gp->regs + MIF_BBCLK);
2004 writel(0, gp->regs + MIF_BBDATA);
2005 writel(0, gp->regs + MIF_BBOENAB);
2006 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2007 (void) readl(gp->regs + MAC_XIFCFG);
2008 }
2009 }
2010
2011 /* Shut down the chip, must be called with pm_sem held. */
2012 static void gem_shutdown(struct gem *gp)
2013 {
2014 /* Make us not-running to avoid timers respawning */
2015 gp->hw_running = 0;
2016
2017 /* Stop the link timer */
2018 del_timer_sync(&gp->link_timer);
2019
2020 /* Stop the reset task */
2021 while (gp->reset_task_pending)
2022 schedule();
2023
2024 /* Actually stop the chip */
2025 spin_lock_irq(&gp->lock);
2026 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2027 gem_stop_phy(gp);
2028
2029 spin_unlock_irq(&gp->lock);
2030
2031 #ifdef CONFIG_PPC_PMAC
2032 /* Power down the chip */
2033 gem_apple_powerdown(gp);
2034 #endif /* CONFIG_PPC_PMAC */
2035 } else {
2036 gem_stop(gp);
2037
2038 spin_unlock_irq(&gp->lock);
2039 }
2040 }
2041
2042 static void gem_pm_task(void *data)
2043 {
2044 struct gem *gp = (struct gem *) data;
2045
2046 /* We assume if we can't lock the pm_sem, then open() was
2047 * called again (or suspend()), and we can safely ignore
2048 * the PM request
2049 */
2050 if (down_trylock(&gp->pm_sem))
2051 return;
2052
2053 /* Driver was re-opened or already shut down */
2054 if (gp->opened || !gp->hw_running) {
2055 up(&gp->pm_sem);
2056 return;
2057 }
2058
2059 gem_shutdown(gp);
2060
2061 up(&gp->pm_sem);
2062 }
2063
2064 static void gem_pm_timer(unsigned long data)
2065 {
2066 struct gem *gp = (struct gem *) data;
2067
2068 schedule_work(&gp->pm_task);
2069 }
2070
2071 static int gem_open(struct net_device *dev)
2072 {
2073 struct gem *gp = dev->priv;
2074 int hw_was_up;
2075
2076 down(&gp->pm_sem);
2077
2078 hw_was_up = gp->hw_running;
2079
2080 /* Stop the PM timer/task */
2081 del_timer(&gp->pm_timer);
2082 flush_scheduled_work();
2083
2084 /* The power-management semaphore protects the hw_running
2085 * etc. state so it is safe to do this bit without gp->lock
2086 */
2087 if (!gp->hw_running) {
2088 #ifdef CONFIG_PPC_PMAC
2089 /* First, we need to bring up the chip */
2090 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2091 gem_apple_powerup(gp);
2092 gem_check_invariants(gp);
2093 }
2094 #endif /* CONFIG_PPC_PMAC */
2095
2096 /* Reset the chip */
2097 spin_lock_irq(&gp->lock);
2098 gem_stop(gp);
2099 spin_unlock_irq(&gp->lock);
2100
2101 gp->hw_running = 1;
2102 }
2103
2104 spin_lock_irq(&gp->lock);
2105
2106 /* We can now request the interrupt as we know it's masked
2107 * on the controller
2108 */
2109 if (request_irq(gp->pdev->irq, gem_interrupt,
2110 SA_SHIRQ, dev->name, (void *)dev)) {
2111 spin_unlock_irq(&gp->lock);
2112
2113 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2114
2115 #ifdef CONFIG_PPC_PMAC
2116 if (!hw_was_up && gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2117 gem_apple_powerdown(gp);
2118 #endif /* CONFIG_PPC_PMAC */
2119 /* Fire the PM timer that will shut us down in about 10 seconds */
2120 gp->pm_timer.expires = jiffies + 10*HZ;
2121 add_timer(&gp->pm_timer);
2122 up(&gp->pm_sem);
2123
2124 return -EAGAIN;
2125 }
2126
2127 /* Allocate & setup ring buffers */
2128 gem_init_rings(gp);
2129
2130 /* Init & setup chip hardware */
2131 gem_init_hw(gp, !hw_was_up);
2132
2133 gp->opened = 1;
2134
2135 spin_unlock_irq(&gp->lock);
2136
2137 up(&gp->pm_sem);
2138
2139 return 0;
2140 }
2141
2142 static int gem_close(struct net_device *dev)
2143 {
2144 struct gem *gp = dev->priv;
2145
2146 /* Make sure we don't get distracted by suspend/resume */
2147 down(&gp->pm_sem);
2148
2149 /* Stop traffic, mark us closed */
2150 spin_lock_irq(&gp->lock);
2151
2152 gp->opened = 0;
2153 writel(0xffffffff, gp->regs + GREG_IMASK);
2154 netif_stop_queue(dev);
2155
2156 /* Stop chip */
2157 gem_stop(gp);
2158
2159 /* Get rid of rings */
2160 gem_clean_rings(gp);
2161
2162 /* Bye, the pm timer will finish the job */
2163 free_irq(gp->pdev->irq, (void *) dev);
2164
2165 spin_unlock_irq(&gp->lock);
2166
2167 /* Fire the PM timer that will shut us down in about 10 seconds */
2168 gp->pm_timer.expires = jiffies + 10*HZ;
2169 add_timer(&gp->pm_timer);
2170
2171 up(&gp->pm_sem);
2172
2173 return 0;
2174 }
2175
2176 #ifdef CONFIG_PM
2177 static int gem_suspend(struct pci_dev *pdev, u32 state)
2178 {
2179 struct net_device *dev = pci_get_drvdata(pdev);
2180 struct gem *gp = dev->priv;
2181
2182 /* We hold the PM semaphore during entire driver
2183 * sleep time
2184 */
2185 down(&gp->pm_sem);
2186
2187 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2188 dev->name, gp->wake_on_lan ? "enabled" : "disabled");
2189
2190 /* If the driver is opened, we stop the DMA */
2191 if (gp->opened) {
2192 spin_lock_irq(&gp->lock);
2193
2194 /* Stop traffic, mark us closed */
2195 netif_device_detach(dev);
2196
2197 writel(0xffffffff, gp->regs + GREG_IMASK);
2198
2199 /* Stop chip */
2200 gem_stop(gp);
2201
2202 /* Get rid of ring buffers */
2203 gem_clean_rings(gp);
2204
2205 spin_unlock_irq(&gp->lock);
2206
2207 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2208 disable_irq(gp->pdev->irq);
2209 }
2210
2211 if (gp->hw_running) {
2212 /* Kill PM timer if any */
2213 del_timer_sync(&gp->pm_timer);
2214 flush_scheduled_work();
2215
2216 gem_shutdown(gp);
2217 }
2218
2219 return 0;
2220 }
2221
2222 static int gem_resume(struct pci_dev *pdev)
2223 {
2224 struct net_device *dev = pci_get_drvdata(pdev);
2225 struct gem *gp = dev->priv;
2226
2227 printk(KERN_INFO "%s: resuming\n", dev->name);
2228
2229 if (gp->opened) {
2230 #ifdef CONFIG_PPC_PMAC
2231 /* First, we need to bring up the chip */
2232 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2233 gem_apple_powerup(gp);
2234 gem_check_invariants(gp);
2235 }
2236 #endif /* CONFIG_PPC_PMAC */
2237 spin_lock_irq(&gp->lock);
2238
2239 gem_stop(gp);
2240 gp->hw_running = 1;
2241 gem_init_rings(gp);
2242 gem_init_hw(gp, 1);
2243
2244 spin_unlock_irq(&gp->lock);
2245
2246 netif_device_attach(dev);
2247 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2248 enable_irq(gp->pdev->irq);
2249 }
2250 up(&gp->pm_sem);
2251
2252 return 0;
2253 }
2254 #endif /* CONFIG_PM */
2255
2256 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2257 {
2258 struct gem *gp = dev->priv;
2259 struct net_device_stats *stats = &gp->net_stats;
2260
2261 spin_lock_irq(&gp->lock);
2262
2263 if (gp->hw_running) {
2264 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2265 writel(0, gp->regs + MAC_FCSERR);
2266
2267 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2268 writel(0, gp->regs + MAC_AERR);
2269
2270 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2271 writel(0, gp->regs + MAC_LERR);
2272
2273 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2274 stats->collisions +=
2275 (readl(gp->regs + MAC_ECOLL) +
2276 readl(gp->regs + MAC_LCOLL));
2277 writel(0, gp->regs + MAC_ECOLL);
2278 writel(0, gp->regs + MAC_LCOLL);
2279 }
2280
2281 spin_unlock_irq(&gp->lock);
2282
2283 return &gp->net_stats;
2284 }
2285
2286 static void gem_set_multicast(struct net_device *dev)
2287 {
2288 struct gem *gp = dev->priv;
2289 u32 rxcfg, rxcfg_new;
2290 int limit = 10000;
2291
2292 if (!gp->hw_running)
2293 return;
2294
2295 spin_lock_irq(&gp->lock);
2296
2297 netif_stop_queue(dev);
2298
2299 rxcfg = readl(gp->regs + MAC_RXCFG);
2300 rxcfg_new = gem_setup_multicast(gp);
2301 #ifdef STRIP_FCS
2302 rxcfg_new |= MAC_RXCFG_SFCS;
2303 #endif
2304 gp->mac_rx_cfg = rxcfg_new;
2305
2306 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2307 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2308 if (!limit--)
2309 break;
2310 udelay(10);
2311 }
2312
2313 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2314 rxcfg |= rxcfg_new;
2315
2316 writel(rxcfg, gp->regs + MAC_RXCFG);
2317
2318 netif_wake_queue(dev);
2319
2320 spin_unlock_irq(&gp->lock);
2321 }
2322
2323 /* Eventually add support for changing the advertisement
2324 * on autoneg.
2325 */
2326 static int gem_ethtool_ioctl(struct net_device *dev, void *ep_user)
2327 {
2328 struct gem *gp = dev->priv;
2329 struct ethtool_cmd ecmd;
2330
2331 if (copy_from_user(&ecmd, ep_user, sizeof(ecmd)))
2332 return -EFAULT;
2333
2334 switch(ecmd.cmd) {
2335 case ETHTOOL_GDRVINFO: {
2336 struct ethtool_drvinfo info = { .cmd = ETHTOOL_GDRVINFO };
2337
2338 strncpy(info.driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2339 strncpy(info.version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2340 info.fw_version[0] = '\0';
2341 strncpy(info.bus_info, gp->pdev->slot_name, ETHTOOL_BUSINFO_LEN);
2342 info.regdump_len = 0; /*SUNGEM_NREGS;*/
2343
2344 if (copy_to_user(ep_user, &info, sizeof(info)))
2345 return -EFAULT;
2346
2347 return 0;
2348 }
2349
2350 case ETHTOOL_GSET:
2351 if (gp->phy_type == phy_mii_mdio0 ||
2352 gp->phy_type == phy_mii_mdio1) {
2353 if (gp->phy_mii.def)
2354 ecmd.supported = gp->phy_mii.def->features;
2355 else
2356 ecmd.supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
2357
2358 /* XXX hardcoded stuff for now */
2359 ecmd.port = PORT_MII;
2360 ecmd.transceiver = XCVR_EXTERNAL;
2361 ecmd.phy_address = 0; /* XXX fixed PHYAD */
2362
2363 /* Return current PHY settings */
2364 spin_lock_irq(&gp->lock);
2365 ecmd.autoneg = gp->want_autoneg;
2366 ecmd.speed = gp->phy_mii.speed;
2367 ecmd.duplex = gp->phy_mii.duplex;
2368 ecmd.advertising = gp->phy_mii.advertising;
2369 /* If we started with a forced mode, we don't have a default
2370 * advertise set, we need to return something sensible so
2371 * userland can re-enable autoneg properly */
2372 if (ecmd.advertising == 0)
2373 ecmd.advertising = ecmd.supported;
2374 spin_unlock_irq(&gp->lock);
2375 } else { // XXX PCS ?
2376 ecmd.supported =
2377 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2378 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2379 SUPPORTED_Autoneg);
2380 ecmd.advertising = ecmd.supported;
2381 }
2382 if (copy_to_user(ep_user, &ecmd, sizeof(ecmd)))
2383 return -EFAULT;
2384 return 0;
2385
2386 case ETHTOOL_SSET:
2387 if (!capable(CAP_NET_ADMIN))
2388 return -EPERM;
2389
2390 /* Verify the settings we care about. */
2391 if (ecmd.autoneg != AUTONEG_ENABLE &&
2392 ecmd.autoneg != AUTONEG_DISABLE)
2393 return -EINVAL;
2394
2395 if (ecmd.autoneg == AUTONEG_ENABLE &&
2396 ecmd.advertising == 0)
2397 return -EINVAL;
2398
2399 if (ecmd.autoneg == AUTONEG_DISABLE &&
2400 ((ecmd.speed != SPEED_1000 &&
2401 ecmd.speed != SPEED_100 &&
2402 ecmd.speed != SPEED_10) ||
2403 (ecmd.duplex != DUPLEX_HALF &&
2404 ecmd.duplex != DUPLEX_FULL)))
2405 return -EINVAL;
2406
2407 /* Apply settings and restart link process. */
2408 spin_lock_irq(&gp->lock);
2409 gem_begin_auto_negotiation(gp, &ecmd);
2410 spin_unlock_irq(&gp->lock);
2411
2412 return 0;
2413
2414 case ETHTOOL_NWAY_RST:
2415 if (!gp->want_autoneg)
2416 return -EINVAL;
2417
2418 /* Restart link process. */
2419 spin_lock_irq(&gp->lock);
2420 gem_begin_auto_negotiation(gp, NULL);
2421 spin_unlock_irq(&gp->lock);
2422
2423 return 0;
2424
2425 case ETHTOOL_GWOL:
2426 case ETHTOOL_SWOL:
2427 break; /* todo */
2428
2429 /* get link status */
2430 case ETHTOOL_GLINK: {
2431 struct ethtool_value edata = { .cmd = ETHTOOL_GLINK };
2432
2433 edata.data = (gp->lstate == link_up);
2434 if (copy_to_user(ep_user, &edata, sizeof(edata)))
2435 return -EFAULT;
2436 return 0;
2437 }
2438
2439 /* get message-level */
2440 case ETHTOOL_GMSGLVL: {
2441 struct ethtool_value edata = { .cmd = ETHTOOL_GMSGLVL };
2442
2443 edata.data = gp->msg_enable;
2444 if (copy_to_user(ep_user, &edata, sizeof(edata)))
2445 return -EFAULT;
2446 return 0;
2447 }
2448
2449 /* set message-level */
2450 case ETHTOOL_SMSGLVL: {
2451 struct ethtool_value edata;
2452
2453 if (copy_from_user(&edata, ep_user, sizeof(edata)))
2454 return -EFAULT;
2455 gp->msg_enable = edata.data;
2456 return 0;
2457 }
2458
2459 #if 0
2460 case ETHTOOL_GREGS: {
2461 struct ethtool_regs regs;
2462 u32 *regbuf;
2463 int r = 0;
2464
2465 if (copy_from_user(&regs, useraddr, sizeof(regs)))
2466 return -EFAULT;
2467
2468 if (regs.len > SUNGEM_NREGS) {
2469 regs.len = SUNGEM_NREGS;
2470 }
2471 regs.version = 0;
2472 if (copy_to_user(useraddr, &regs, sizeof(regs)))
2473 return -EFAULT;
2474
2475 if (!gp->hw_running)
2476 return -ENODEV;
2477 useraddr += offsetof(struct ethtool_regs, data);
2478
2479 /* Use kmalloc to avoid bloating the stack */
2480 regbuf = kmalloc(4 * SUNGEM_NREGS, GFP_KERNEL);
2481 if (!regbuf)
2482 return -ENOMEM;
2483 spin_lock_irq(&np->lock);
2484 gem_get_regs(gp, regbuf);
2485 spin_unlock_irq(&np->lock);
2486
2487 if (copy_to_user(useraddr, regbuf, regs.len*sizeof(u32)))
2488 r = -EFAULT;
2489 kfree(regbuf);
2490 return r;
2491 }
2492 #endif
2493 };
2494
2495 return -EOPNOTSUPP;
2496 }
2497
2498 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2499 {
2500 struct gem *gp = dev->priv;
2501 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data;
2502 int rc = -EOPNOTSUPP;
2503
2504 /* Hold the PM semaphore while doing ioctl's or we may collide
2505 * with open/close and power management and oops.
2506 */
2507 down(&gp->pm_sem);
2508
2509 switch (cmd) {
2510 case SIOCETHTOOL:
2511 rc = gem_ethtool_ioctl(dev, ifr->ifr_data);
2512 break;
2513
2514 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2515 data->phy_id = gp->mii_phy_addr;
2516 /* Fallthrough... */
2517
2518 case SIOCGMIIREG: /* Read MII PHY register. */
2519 if (!gp->hw_running)
2520 rc = -EIO;
2521 else {
2522 data->val_out = __phy_read(gp, data->phy_id & 0x1f, data->reg_num & 0x1f);
2523 rc = 0;
2524 }
2525 break;
2526
2527 case SIOCSMIIREG: /* Write MII PHY register. */
2528 if (!capable(CAP_NET_ADMIN))
2529 rc = -EPERM;
2530 else if (!gp->hw_running)
2531 rc = -EIO;
2532 else {
2533 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2534 rc = 0;
2535 }
2536 break;
2537 };
2538
2539 up(&gp->pm_sem);
2540
2541 return rc;
2542 }
2543
2544 #if (!defined(__sparc__) && !defined(CONFIG_PPC))
2545 /* Fetch MAC address from vital product data of PCI ROM. */
2546 static void find_eth_addr_in_vpd(void *rom_base, int len, unsigned char *dev_addr)
2547 {
2548 int this_offset;
2549
2550 for (this_offset = 0x20; this_offset < len; this_offset++) {
2551 void *p = rom_base + this_offset;
2552 int i;
2553
2554 if (readb(p + 0) != 0x90 ||
2555 readb(p + 1) != 0x00 ||
2556 readb(p + 2) != 0x09 ||
2557 readb(p + 3) != 0x4e ||
2558 readb(p + 4) != 0x41 ||
2559 readb(p + 5) != 0x06)
2560 continue;
2561
2562 this_offset += 6;
2563 p += 6;
2564
2565 for (i = 0; i < 6; i++)
2566 dev_addr[i] = readb(p + i);
2567 break;
2568 }
2569 }
2570
2571 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2572 {
2573 u32 rom_reg_orig;
2574 void *p;
2575
2576 if (pdev->resource[PCI_ROM_RESOURCE].parent == NULL) {
2577 if (pci_assign_resource(pdev, PCI_ROM_RESOURCE) < 0)
2578 goto use_random;
2579 }
2580
2581 pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_reg_orig);
2582 pci_write_config_dword(pdev, pdev->rom_base_reg,
2583 rom_reg_orig | PCI_ROM_ADDRESS_ENABLE);
2584
2585 p = ioremap(pci_resource_start(pdev, PCI_ROM_RESOURCE), (64 * 1024));
2586 if (p != NULL && readb(p) == 0x55 && readb(p + 1) == 0xaa)
2587 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2588
2589 if (p != NULL)
2590 iounmap(p);
2591
2592 pci_write_config_dword(pdev, pdev->rom_base_reg, rom_reg_orig);
2593 return;
2594
2595 use_random:
2596 /* Sun MAC prefix then 3 random bytes. */
2597 dev_addr[0] = 0x08;
2598 dev_addr[1] = 0x00;
2599 dev_addr[2] = 0x20;
2600 get_random_bytes(dev_addr + 3, 3);
2601 return;
2602 }
2603 #endif /* not Sparc and not PPC */
2604
2605 static int __devinit gem_get_device_address(struct gem *gp)
2606 {
2607 #if defined(__sparc__) || defined(CONFIG_PPC_PMAC)
2608 struct net_device *dev = gp->dev;
2609 #endif
2610
2611 #if defined(__sparc__)
2612 struct pci_dev *pdev = gp->pdev;
2613 struct pcidev_cookie *pcp = pdev->sysdata;
2614 int node = -1;
2615
2616 if (pcp != NULL) {
2617 node = pcp->prom_node;
2618 if (prom_getproplen(node, "local-mac-address") == 6)
2619 prom_getproperty(node, "local-mac-address",
2620 dev->dev_addr, 6);
2621 else
2622 node = -1;
2623 }
2624 if (node == -1)
2625 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2626 #elif defined(CONFIG_PPC_PMAC)
2627 unsigned char *addr;
2628
2629 addr = get_property(gp->of_node, "local-mac-address", NULL);
2630 if (addr == NULL) {
2631 printk("\n");
2632 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2633 return -1;
2634 }
2635 memcpy(dev->dev_addr, addr, 6);
2636 #else
2637 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2638 #endif
2639 return 0;
2640 }
2641
2642 static int __devinit gem_init_one(struct pci_dev *pdev,
2643 const struct pci_device_id *ent)
2644 {
2645 static int gem_version_printed = 0;
2646 unsigned long gemreg_base, gemreg_len;
2647 struct net_device *dev;
2648 struct gem *gp;
2649 int i, err, pci_using_dac;
2650
2651 if (gem_version_printed++ == 0)
2652 printk(KERN_INFO "%s", version);
2653
2654 /* Apple gmac note: during probe, the chip is powered up by
2655 * the arch code to allow the code below to work (and to let
2656 * the chip be probed on the config space. It won't stay powered
2657 * up until the interface is brought up however, so we can't rely
2658 * on register configuration done at this point.
2659 */
2660 err = pci_enable_device(pdev);
2661 if (err) {
2662 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
2663 "aborting.\n");
2664 return err;
2665 }
2666 pci_set_master(pdev);
2667
2668 /* Configure DMA attributes. */
2669
2670 /* All of the GEM documentation states that 64-bit DMA addressing
2671 * is fully supported and should work just fine. However the
2672 * front end for RIO based GEMs is different and only supports
2673 * 32-bit addressing.
2674 *
2675 * For now we assume the various PPC GEMs are 32-bit only as well.
2676 */
2677 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2678 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2679 !pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL)) {
2680 pci_using_dac = 1;
2681 } else {
2682 err = pci_set_dma_mask(pdev, (u64) 0xffffffff);
2683 if (err) {
2684 printk(KERN_ERR PFX "No usable DMA configuration, "
2685 "aborting.\n");
2686 return err;
2687 }
2688 pci_using_dac = 0;
2689 }
2690
2691 gemreg_base = pci_resource_start(pdev, 0);
2692 gemreg_len = pci_resource_len(pdev, 0);
2693
2694 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2695 printk(KERN_ERR PFX "Cannot find proper PCI device "
2696 "base address, aborting.\n");
2697 return -ENODEV;
2698 }
2699
2700 dev = alloc_etherdev(sizeof(*gp));
2701 if (!dev) {
2702 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
2703 return -ENOMEM;
2704 }
2705 SET_MODULE_OWNER(dev);
2706 SET_NETDEV_DEV(dev, &pdev->dev);
2707
2708 gp = dev->priv;
2709
2710 if (pci_request_regions(pdev, dev->name)) {
2711 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
2712 "aborting.\n");
2713 goto err_out_free_netdev;
2714 }
2715
2716 gp->pdev = pdev;
2717 dev->base_addr = (long) pdev;
2718 gp->dev = dev;
2719
2720 gp->msg_enable = DEFAULT_MSG;
2721
2722 spin_lock_init(&gp->lock);
2723 init_MUTEX(&gp->pm_sem);
2724
2725 init_timer(&gp->link_timer);
2726 gp->link_timer.function = gem_link_timer;
2727 gp->link_timer.data = (unsigned long) gp;
2728
2729 init_timer(&gp->pm_timer);
2730 gp->pm_timer.function = gem_pm_timer;
2731 gp->pm_timer.data = (unsigned long) gp;
2732
2733 INIT_WORK(&gp->pm_task, gem_pm_task, gp);
2734 INIT_WORK(&gp->reset_task, gem_reset_task, gp);
2735
2736 gp->lstate = link_down;
2737 gp->timer_ticks = 0;
2738 netif_carrier_off(dev);
2739
2740 gp->regs = (unsigned long) ioremap(gemreg_base, gemreg_len);
2741 if (gp->regs == 0UL) {
2742 printk(KERN_ERR PFX "Cannot map device registers, "
2743 "aborting.\n");
2744 goto err_out_free_res;
2745 }
2746
2747 /* On Apple, we power the chip up now in order for check
2748 * invariants to work, but also because the firmware might
2749 * not have properly shut down the PHY.
2750 */
2751 #ifdef CONFIG_PPC_PMAC
2752 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2753 gem_apple_powerup(gp);
2754 #endif
2755 spin_lock_irq(&gp->lock);
2756 gem_stop(gp);
2757 spin_unlock_irq(&gp->lock);
2758
2759 /* Fill up the mii_phy structure (even if we won't use it) */
2760 gp->phy_mii.dev = dev;
2761 gp->phy_mii.mdio_read = _phy_read;
2762 gp->phy_mii.mdio_write = _phy_write;
2763
2764 /* By default, we start with autoneg */
2765 gp->want_autoneg = 1;
2766
2767 if (gem_check_invariants(gp))
2768 goto err_out_iounmap;
2769
2770 /* It is guaranteed that the returned buffer will be at least
2771 * PAGE_SIZE aligned.
2772 */
2773 gp->init_block = (struct gem_init_block *)
2774 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
2775 &gp->gblock_dvma);
2776 if (!gp->init_block) {
2777 printk(KERN_ERR PFX "Cannot allocate init block, "
2778 "aborting.\n");
2779 goto err_out_iounmap;
2780 }
2781
2782 #ifdef CONFIG_PPC_PMAC
2783 gp->of_node = pci_device_to_OF_node(pdev);
2784 #endif
2785 if (gem_get_device_address(gp))
2786 goto err_out_free_consistent;
2787
2788 if (register_netdev(dev)) {
2789 printk(KERN_ERR PFX "Cannot register net device, "
2790 "aborting.\n");
2791 goto err_out_free_consistent;
2792 }
2793
2794 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
2795 dev->name);
2796 for (i = 0; i < 6; i++)
2797 printk("%2.2x%c", dev->dev_addr[i],
2798 i == 5 ? ' ' : ':');
2799 printk("\n");
2800
2801 /* Detect & init PHY, start autoneg */
2802 spin_lock_irq(&gp->lock);
2803 gp->hw_running = 1;
2804 gem_init_phy(gp);
2805 gem_begin_auto_negotiation(gp, NULL);
2806 spin_unlock_irq(&gp->lock);
2807
2808 if (gp->phy_type == phy_mii_mdio0 ||
2809 gp->phy_type == phy_mii_mdio1)
2810 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
2811 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
2812
2813 pci_set_drvdata(pdev, dev);
2814
2815 dev->open = gem_open;
2816 dev->stop = gem_close;
2817 dev->hard_start_xmit = gem_start_xmit;
2818 dev->get_stats = gem_get_stats;
2819 dev->set_multicast_list = gem_set_multicast;
2820 dev->do_ioctl = gem_ioctl;
2821 dev->tx_timeout = gem_tx_timeout;
2822 dev->watchdog_timeo = 5 * HZ;
2823 dev->change_mtu = gem_change_mtu;
2824 dev->irq = pdev->irq;
2825 dev->dma = 0;
2826
2827 /* GEM can do it all... */
2828 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
2829 if (pci_using_dac)
2830 dev->features |= NETIF_F_HIGHDMA;
2831
2832 /* Fire the PM timer that will shut us down in about 10 seconds */
2833 gp->pm_timer.expires = jiffies + 10*HZ;
2834 add_timer(&gp->pm_timer);
2835
2836 return 0;
2837
2838 err_out_free_consistent:
2839 pci_free_consistent(pdev,
2840 sizeof(struct gem_init_block),
2841 gp->init_block,
2842 gp->gblock_dvma);
2843
2844 err_out_iounmap:
2845 down(&gp->pm_sem);
2846 /* Stop the PM timer & task */
2847 del_timer_sync(&gp->pm_timer);
2848 flush_scheduled_work();
2849 if (gp->hw_running)
2850 gem_shutdown(gp);
2851 up(&gp->pm_sem);
2852
2853 iounmap((void *) gp->regs);
2854
2855 err_out_free_res:
2856 pci_release_regions(pdev);
2857
2858 err_out_free_netdev:
2859 kfree(dev);
2860
2861 return -ENODEV;
2862
2863 }
2864
2865 static void __devexit gem_remove_one(struct pci_dev *pdev)
2866 {
2867 struct net_device *dev = pci_get_drvdata(pdev);
2868
2869 if (dev) {
2870 struct gem *gp = dev->priv;
2871
2872 unregister_netdev(dev);
2873
2874 down(&gp->pm_sem);
2875 /* Stop the PM timer & task */
2876 del_timer_sync(&gp->pm_timer);
2877 flush_scheduled_work();
2878 if (gp->hw_running)
2879 gem_shutdown(gp);
2880 up(&gp->pm_sem);
2881
2882 pci_free_consistent(pdev,
2883 sizeof(struct gem_init_block),
2884 gp->init_block,
2885 gp->gblock_dvma);
2886 iounmap((void *) gp->regs);
2887 pci_release_regions(pdev);
2888 kfree(dev);
2889
2890 pci_set_drvdata(pdev, NULL);
2891 }
2892 }
2893
2894 static struct pci_driver gem_driver = {
2895 .name = GEM_MODULE_NAME,
2896 .id_table = gem_pci_tbl,
2897 .probe = gem_init_one,
2898 .remove = __devexit_p(gem_remove_one),
2899 #ifdef CONFIG_PM
2900 .suspend = gem_suspend,
2901 .resume = gem_resume,
2902 #endif /* CONFIG_PM */
2903 };
2904
2905 static int __init gem_init(void)
2906 {
2907 return pci_module_init(&gem_driver);
2908 }
2909
2910 static void __exit gem_cleanup(void)
2911 {
2912 pci_unregister_driver(&gem_driver);
2913 }
2914
2915 module_init(gem_init);
2916 module_exit(gem_cleanup);
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