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[linux-2.6/linux-mips.git] / drivers / net / sunbmac.c
blob2b3197ed55d80bea514c8c6ef6c087466681f3cb
1 /* $Id: sunbmac.c,v 1.30 2002/01/15 06:48:55 davem Exp $
2 * sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 */
6
7 #include <linux/module.h>
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/fcntl.h>
12 #include <linux/interrupt.h>
13 #include <linux/ioport.h>
14 #include <linux/in.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/crc32.h>
20 #include <linux/errno.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24
25 #include <asm/auxio.h>
26 #include <asm/bitops.h>
27 #include <asm/byteorder.h>
28 #include <asm/dma.h>
29 #include <asm/idprom.h>
30 #include <asm/io.h>
31 #include <asm/openprom.h>
32 #include <asm/oplib.h>
33 #include <asm/pgtable.h>
34 #include <asm/sbus.h>
35 #include <asm/system.h>
36
37 #include "sunbmac.h"
38
39 static char version[] __initdata =
40 "sunbmac.c:v1.9 11/Sep/99 David S. Miller (davem@redhat.com)\n";
41
42 #undef DEBUG_PROBE
43 #undef DEBUG_TX
44 #undef DEBUG_IRQ
45
46 #ifdef DEBUG_PROBE
47 #define DP(x) printk x
48 #else
49 #define DP(x)
50 #endif
51
52 #ifdef DEBUG_TX
53 #define DTX(x) printk x
54 #else
55 #define DTX(x)
56 #endif
57
58 #ifdef DEBUG_IRQ
59 #define DIRQ(x) printk x
60 #else
61 #define DIRQ(x)
62 #endif
63
64 static struct bigmac *root_bigmac_dev;
65
66 #define DEFAULT_JAMSIZE 4 /* Toe jam */
67
68 #define QEC_RESET_TRIES 200
69
70 static int qec_global_reset(unsigned long gregs)
71 {
72 int tries = QEC_RESET_TRIES;
73
74 sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
75 while (--tries) {
76 if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) {
77 udelay(20);
78 continue;
79 }
80 break;
81 }
82 if (tries)
83 return 0;
84 printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n");
85 return -1;
86 }
87
88 static void qec_init(struct bigmac *bp)
89 {
90 unsigned long gregs = bp->gregs;
91 struct sbus_dev *qec_sdev = bp->qec_sdev;
92 u8 bsizes = bp->bigmac_bursts;
93 u32 regval;
94
95 /* 64byte bursts do not work at the moment, do
96 * not even try to enable them. -DaveM
97 */
98 if (bsizes & DMA_BURST32)
99 regval = GLOB_CTRL_B32;
100 else
101 regval = GLOB_CTRL_B16;
102 sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL);
103 sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE);
104
105 /* All of memsize is given to bigmac. */
106 sbus_writel(qec_sdev->reg_addrs[1].reg_size,
107 gregs + GLOB_MSIZE);
108
109 /* Half to the transmitter, half to the receiver. */
110 sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
111 gregs + GLOB_TSIZE);
112 sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
113 gregs + GLOB_RSIZE);
114 }
115
116 #define TX_RESET_TRIES 32
117 #define RX_RESET_TRIES 32
118
119 static void bigmac_tx_reset(unsigned long bregs)
120 {
121 int tries = TX_RESET_TRIES;
122
123 sbus_writel(0, bregs + BMAC_TXCFG);
124
125 /* The fifo threshold bit is read-only and does
126 * not clear. -DaveM
127 */
128 while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
129 --tries != 0)
130 udelay(20);
131
132 if (!tries) {
133 printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n");
134 printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n",
135 sbus_readl(bregs + BMAC_TXCFG));
136 }
137 }
138
139 static void bigmac_rx_reset(unsigned long bregs)
140 {
141 int tries = RX_RESET_TRIES;
142
143 sbus_writel(0, bregs + BMAC_RXCFG);
144 while (sbus_readl(bregs + BMAC_RXCFG) && --tries)
145 udelay(20);
146
147 if (!tries) {
148 printk(KERN_ERR "BIGMAC: Receiver will not reset.\n");
149 printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n",
150 sbus_readl(bregs + BMAC_RXCFG));
151 }
152 }
153
154 /* Reset the transmitter and receiver. */
155 static void bigmac_stop(struct bigmac *bp)
156 {
157 bigmac_tx_reset(bp->bregs);
158 bigmac_rx_reset(bp->bregs);
159 }
160
161 static void bigmac_get_counters(struct bigmac *bp, unsigned long bregs)
162 {
163 struct net_device_stats *stats = &bp->enet_stats;
164
165 stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR);
166 sbus_writel(0, bregs + BMAC_RCRCECTR);
167
168 stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR);
169 sbus_writel(0, bregs + BMAC_UNALECTR);
170
171 stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR);
172 sbus_writel(0, bregs + BMAC_GLECTR);
173
174 stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR);
175
176 stats->collisions +=
177 (sbus_readl(bregs + BMAC_EXCTR) +
178 sbus_readl(bregs + BMAC_LTCTR));
179 sbus_writel(0, bregs + BMAC_EXCTR);
180 sbus_writel(0, bregs + BMAC_LTCTR);
181 }
182
183 static void bigmac_clean_rings(struct bigmac *bp)
184 {
185 int i;
186
187 for (i = 0; i < RX_RING_SIZE; i++) {
188 if (bp->rx_skbs[i] != NULL) {
189 dev_kfree_skb_any(bp->rx_skbs[i]);
190 bp->rx_skbs[i] = NULL;
191 }
192 }
193
194 for (i = 0; i < TX_RING_SIZE; i++) {
195 if (bp->tx_skbs[i] != NULL) {
196 dev_kfree_skb_any(bp->tx_skbs[i]);
197 bp->tx_skbs[i] = NULL;
198 }
199 }
200 }
201
202 static void bigmac_init_rings(struct bigmac *bp, int from_irq)
203 {
204 struct bmac_init_block *bb = bp->bmac_block;
205 struct net_device *dev = bp->dev;
206 int i, gfp_flags = GFP_KERNEL;
207
208 if (from_irq || in_interrupt())
209 gfp_flags = GFP_ATOMIC;
210
211 bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
212
213 /* Free any skippy bufs left around in the rings. */
214 bigmac_clean_rings(bp);
215
216 /* Now get new skbufs for the receive ring. */
217 for (i = 0; i < RX_RING_SIZE; i++) {
218 struct sk_buff *skb;
219
220 skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
221 if (!skb)
222 continue;
223
224 bp->rx_skbs[i] = skb;
225 skb->dev = dev;
226
227 /* Because we reserve afterwards. */
228 skb_put(skb, ETH_FRAME_LEN);
229 skb_reserve(skb, 34);
230
231 bb->be_rxd[i].rx_addr =
232 sbus_map_single(bp->bigmac_sdev, skb->data,
233 RX_BUF_ALLOC_SIZE - 34,
234 SBUS_DMA_FROMDEVICE);
235 bb->be_rxd[i].rx_flags =
236 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
237 }
238
239 for (i = 0; i < TX_RING_SIZE; i++)
240 bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
241 }
242
243 #define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
244 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
245
246 static void idle_transceiver(unsigned long tregs)
247 {
248 int i = 20;
249
250 while (i--) {
251 sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL);
252 sbus_readl(tregs + TCVR_MPAL);
253 sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL);
254 sbus_readl(tregs + TCVR_MPAL);
255 }
256 }
257
258 static void write_tcvr_bit(struct bigmac *bp, unsigned long tregs, int bit)
259 {
260 if (bp->tcvr_type == internal) {
261 bit = (bit & 1) << 3;
262 sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO),
263 tregs + TCVR_MPAL);
264 sbus_readl(tregs + TCVR_MPAL);
265 sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
266 tregs + TCVR_MPAL);
267 sbus_readl(tregs + TCVR_MPAL);
268 } else if (bp->tcvr_type == external) {
269 bit = (bit & 1) << 2;
270 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB,
271 tregs + TCVR_MPAL);
272 sbus_readl(tregs + TCVR_MPAL);
273 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK,
274 tregs + TCVR_MPAL);
275 sbus_readl(tregs + TCVR_MPAL);
276 } else {
277 printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n");
278 }
279 }
280
281 static int read_tcvr_bit(struct bigmac *bp, unsigned long tregs)
282 {
283 int retval = 0;
284
285 if (bp->tcvr_type == internal) {
286 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
287 sbus_readl(tregs + TCVR_MPAL);
288 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
289 tregs + TCVR_MPAL);
290 sbus_readl(tregs + TCVR_MPAL);
291 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
292 } else if (bp->tcvr_type == external) {
293 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
294 sbus_readl(tregs + TCVR_MPAL);
295 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
296 sbus_readl(tregs + TCVR_MPAL);
297 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
298 } else {
299 printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n");
300 }
301 return retval;
302 }
303
304 static int read_tcvr_bit2(struct bigmac *bp, unsigned long tregs)
305 {
306 int retval = 0;
307
308 if (bp->tcvr_type == internal) {
309 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
310 sbus_readl(tregs + TCVR_MPAL);
311 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
312 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
313 sbus_readl(tregs + TCVR_MPAL);
314 } else if (bp->tcvr_type == external) {
315 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
316 sbus_readl(tregs + TCVR_MPAL);
317 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
318 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
319 sbus_readl(tregs + TCVR_MPAL);
320 } else {
321 printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n");
322 }
323 return retval;
324 }
325
326 static void put_tcvr_byte(struct bigmac *bp,
327 unsigned long tregs,
328 unsigned int byte)
329 {
330 int shift = 4;
331
332 do {
333 write_tcvr_bit(bp, tregs, ((byte >> shift) & 1));
334 shift -= 1;
335 } while (shift >= 0);
336 }
337
338 static void bigmac_tcvr_write(struct bigmac *bp, unsigned long tregs,
339 int reg, unsigned short val)
340 {
341 int shift;
342
343 reg &= 0xff;
344 val &= 0xffff;
345 switch(bp->tcvr_type) {
346 case internal:
347 case external:
348 break;
349
350 default:
351 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
352 return;
353 };
354
355 idle_transceiver(tregs);
356 write_tcvr_bit(bp, tregs, 0);
357 write_tcvr_bit(bp, tregs, 1);
358 write_tcvr_bit(bp, tregs, 0);
359 write_tcvr_bit(bp, tregs, 1);
360
361 put_tcvr_byte(bp, tregs,
362 ((bp->tcvr_type == internal) ?
363 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
364
365 put_tcvr_byte(bp, tregs, reg);
366
367 write_tcvr_bit(bp, tregs, 1);
368 write_tcvr_bit(bp, tregs, 0);
369
370 shift = 15;
371 do {
372 write_tcvr_bit(bp, tregs, (val >> shift) & 1);
373 shift -= 1;
374 } while (shift >= 0);
375 }
376
377 static unsigned short bigmac_tcvr_read(struct bigmac *bp,
378 unsigned long tregs,
379 int reg)
380 {
381 unsigned short retval = 0;
382
383 reg &= 0xff;
384 switch(bp->tcvr_type) {
385 case internal:
386 case external:
387 break;
388
389 default:
390 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
391 return 0xffff;
392 };
393
394 idle_transceiver(tregs);
395 write_tcvr_bit(bp, tregs, 0);
396 write_tcvr_bit(bp, tregs, 1);
397 write_tcvr_bit(bp, tregs, 1);
398 write_tcvr_bit(bp, tregs, 0);
399
400 put_tcvr_byte(bp, tregs,
401 ((bp->tcvr_type == internal) ?
402 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
403
404 put_tcvr_byte(bp, tregs, reg);
405
406 if (bp->tcvr_type == external) {
407 int shift = 15;
408
409 (void) read_tcvr_bit2(bp, tregs);
410 (void) read_tcvr_bit2(bp, tregs);
411
412 do {
413 int tmp;
414
415 tmp = read_tcvr_bit2(bp, tregs);
416 retval |= ((tmp & 1) << shift);
417 shift -= 1;
418 } while (shift >= 0);
419
420 (void) read_tcvr_bit2(bp, tregs);
421 (void) read_tcvr_bit2(bp, tregs);
422 (void) read_tcvr_bit2(bp, tregs);
423 } else {
424 int shift = 15;
425
426 (void) read_tcvr_bit(bp, tregs);
427 (void) read_tcvr_bit(bp, tregs);
428
429 do {
430 int tmp;
431
432 tmp = read_tcvr_bit(bp, tregs);
433 retval |= ((tmp & 1) << shift);
434 shift -= 1;
435 } while (shift >= 0);
436
437 (void) read_tcvr_bit(bp, tregs);
438 (void) read_tcvr_bit(bp, tregs);
439 (void) read_tcvr_bit(bp, tregs);
440 }
441 return retval;
442 }
443
444 static void bigmac_tcvr_init(struct bigmac *bp)
445 {
446 unsigned long tregs = bp->tregs;
447 u32 mpal;
448
449 idle_transceiver(tregs);
450 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
451 tregs + TCVR_MPAL);
452 sbus_readl(tregs + TCVR_MPAL);
453
454 /* Only the bit for the present transceiver (internal or
455 * external) will stick, set them both and see what stays.
456 */
457 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
458 sbus_readl(tregs + TCVR_MPAL);
459 udelay(20);
460
461 mpal = sbus_readl(tregs + TCVR_MPAL);
462 if (mpal & MGMT_PAL_EXT_MDIO) {
463 bp->tcvr_type = external;
464 sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
465 tregs + TCVR_TPAL);
466 sbus_readl(tregs + TCVR_TPAL);
467 } else if (mpal & MGMT_PAL_INT_MDIO) {
468 bp->tcvr_type = internal;
469 sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK |
470 TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
471 tregs + TCVR_TPAL);
472 sbus_readl(tregs + TCVR_TPAL);
473 } else {
474 printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor "
475 "external MDIO available!\n");
476 printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
477 sbus_readl(tregs + TCVR_MPAL),
478 sbus_readl(tregs + TCVR_TPAL));
479 }
480 }
481
482 static int bigmac_init(struct bigmac *, int);
483
484 static int try_next_permutation(struct bigmac *bp, unsigned long tregs)
485 {
486 if (bp->sw_bmcr & BMCR_SPEED100) {
487 int timeout;
488
489 /* Reset the PHY. */
490 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
491 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
492 bp->sw_bmcr = (BMCR_RESET);
493 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
494
495 timeout = 64;
496 while (--timeout) {
497 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
498 if ((bp->sw_bmcr & BMCR_RESET) == 0)
499 break;
500 udelay(20);
501 }
502 if (timeout == 0)
503 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
504
505 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
506
507 /* Now we try 10baseT. */
508 bp->sw_bmcr &= ~(BMCR_SPEED100);
509 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
510 return 0;
511 }
512
513 /* We've tried them all. */
514 return -1;
515 }
516
517 static void bigmac_timer(unsigned long data)
518 {
519 struct bigmac *bp = (struct bigmac *) data;
520 unsigned long tregs = bp->tregs;
521 int restart_timer = 0;
522
523 bp->timer_ticks++;
524 if (bp->timer_state == ltrywait) {
525 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
526 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
527 if (bp->sw_bmsr & BMSR_LSTATUS) {
528 printk(KERN_INFO "%s: Link is now up at %s.\n",
529 bp->dev->name,
530 (bp->sw_bmcr & BMCR_SPEED100) ?
531 "100baseT" : "10baseT");
532 bp->timer_state = asleep;
533 restart_timer = 0;
534 } else {
535 if (bp->timer_ticks >= 4) {
536 int ret;
537
538 ret = try_next_permutation(bp, tregs);
539 if (ret == -1) {
540 printk(KERN_ERR "%s: Link down, cable problem?\n",
541 bp->dev->name);
542 ret = bigmac_init(bp, 0);
543 if (ret) {
544 printk(KERN_ERR "%s: Error, cannot re-init the "
545 "BigMAC.\n", bp->dev->name);
546 }
547 return;
548 }
549 bp->timer_ticks = 0;
550 restart_timer = 1;
551 } else {
552 restart_timer = 1;
553 }
554 }
555 } else {
556 /* Can't happens.... */
557 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
558 bp->dev->name);
559 restart_timer = 0;
560 bp->timer_ticks = 0;
561 bp->timer_state = asleep; /* foo on you */
562 }
563
564 if (restart_timer != 0) {
565 bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
566 add_timer(&bp->bigmac_timer);
567 }
568 }
569
570 /* Well, really we just force the chip into 100baseT then
571 * 10baseT, each time checking for a link status.
572 */
573 static void bigmac_begin_auto_negotiation(struct bigmac *bp)
574 {
575 unsigned long tregs = bp->tregs;
576 int timeout;
577
578 /* Grab new software copies of PHY registers. */
579 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
580 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
581
582 /* Reset the PHY. */
583 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
584 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
585 bp->sw_bmcr = (BMCR_RESET);
586 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
587
588 timeout = 64;
589 while (--timeout) {
590 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
591 if ((bp->sw_bmcr & BMCR_RESET) == 0)
592 break;
593 udelay(20);
594 }
595 if (timeout == 0)
596 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
597
598 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
599
600 /* First we try 100baseT. */
601 bp->sw_bmcr |= BMCR_SPEED100;
602 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
603
604 bp->timer_state = ltrywait;
605 bp->timer_ticks = 0;
606 bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10;
607 bp->bigmac_timer.data = (unsigned long) bp;
608 bp->bigmac_timer.function = &bigmac_timer;
609 add_timer(&bp->bigmac_timer);
610 }
611
612 static int bigmac_init(struct bigmac *bp, int from_irq)
613 {
614 unsigned long gregs = bp->gregs;
615 unsigned long cregs = bp->creg;
616 unsigned long bregs = bp->bregs;
617 unsigned char *e = &bp->dev->dev_addr[0];
618
619 /* Latch current counters into statistics. */
620 bigmac_get_counters(bp, bregs);
621
622 /* Reset QEC. */
623 qec_global_reset(gregs);
624
625 /* Init QEC. */
626 qec_init(bp);
627
628 /* Alloc and reset the tx/rx descriptor chains. */
629 bigmac_init_rings(bp, from_irq);
630
631 /* Initialize the PHY. */
632 bigmac_tcvr_init(bp);
633
634 /* Stop transmitter and receiver. */
635 bigmac_stop(bp);
636
637 /* Set hardware ethernet address. */
638 sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2);
639 sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1);
640 sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0);
641
642 /* Clear the hash table until mc upload occurs. */
643 sbus_writel(0, bregs + BMAC_HTABLE3);
644 sbus_writel(0, bregs + BMAC_HTABLE2);
645 sbus_writel(0, bregs + BMAC_HTABLE1);
646 sbus_writel(0, bregs + BMAC_HTABLE0);
647
648 /* Enable Big Mac hash table filter. */
649 sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO,
650 bregs + BMAC_RXCFG);
651 udelay(20);
652
653 /* Ok, configure the Big Mac transmitter. */
654 sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG);
655
656 /* The HME docs recommend to use the 10LSB of our MAC here. */
657 sbus_writel(((e[5] | e[4] << 8) & 0x3ff),
658 bregs + BMAC_RSEED);
659
660 /* Enable the output drivers no matter what. */
661 sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV,
662 bregs + BMAC_XIFCFG);
663
664 /* Tell the QEC where the ring descriptors are. */
665 sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0),
666 cregs + CREG_RXDS);
667 sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0),
668 cregs + CREG_TXDS);
669
670 /* Setup the FIFO pointers into QEC local memory. */
671 sbus_writel(0, cregs + CREG_RXRBUFPTR);
672 sbus_writel(0, cregs + CREG_RXWBUFPTR);
673 sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
674 cregs + CREG_TXRBUFPTR);
675 sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
676 cregs + CREG_TXWBUFPTR);
677
678 /* Tell bigmac what interrupts we don't want to hear about. */
679 sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME,
680 bregs + BMAC_IMASK);
681
682 /* Enable the various other irq's. */
683 sbus_writel(0, cregs + CREG_RIMASK);
684 sbus_writel(0, cregs + CREG_TIMASK);
685 sbus_writel(0, cregs + CREG_QMASK);
686 sbus_writel(0, cregs + CREG_BMASK);
687
688 /* Set jam size to a reasonable default. */
689 sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE);
690
691 /* Clear collision counter. */
692 sbus_writel(0, cregs + CREG_CCNT);
693
694 /* Enable transmitter and receiver. */
695 sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE,
696 bregs + BMAC_TXCFG);
697 sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE,
698 bregs + BMAC_RXCFG);
699
700 /* Ok, start detecting link speed/duplex. */
701 bigmac_begin_auto_negotiation(bp);
702
703 /* Success. */
704 return 0;
705 }
706
707 /* Error interrupts get sent here. */
708 static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status)
709 {
710 printk(KERN_ERR "bigmac_is_medium_rare: ");
711 if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) {
712 if (qec_status & GLOB_STAT_ER)
713 printk("QEC_ERROR, ");
714 if (qec_status & GLOB_STAT_BM)
715 printk("QEC_BMAC_ERROR, ");
716 }
717 if (bmac_status & CREG_STAT_ERRORS) {
718 if (bmac_status & CREG_STAT_BERROR)
719 printk("BMAC_ERROR, ");
720 if (bmac_status & CREG_STAT_TXDERROR)
721 printk("TXD_ERROR, ");
722 if (bmac_status & CREG_STAT_TXLERR)
723 printk("TX_LATE_ERROR, ");
724 if (bmac_status & CREG_STAT_TXPERR)
725 printk("TX_PARITY_ERROR, ");
726 if (bmac_status & CREG_STAT_TXSERR)
727 printk("TX_SBUS_ERROR, ");
728
729 if (bmac_status & CREG_STAT_RXDROP)
730 printk("RX_DROP_ERROR, ");
731
732 if (bmac_status & CREG_STAT_RXSMALL)
733 printk("RX_SMALL_ERROR, ");
734 if (bmac_status & CREG_STAT_RXLERR)
735 printk("RX_LATE_ERROR, ");
736 if (bmac_status & CREG_STAT_RXPERR)
737 printk("RX_PARITY_ERROR, ");
738 if (bmac_status & CREG_STAT_RXSERR)
739 printk("RX_SBUS_ERROR, ");
740 }
741
742 printk(" RESET\n");
743 bigmac_init(bp, 1);
744 }
745
746 /* BigMAC transmit complete service routines. */
747 static void bigmac_tx(struct bigmac *bp)
748 {
749 struct be_txd *txbase = &bp->bmac_block->be_txd[0];
750 struct net_device *dev = bp->dev;
751 int elem;
752
753 spin_lock(&bp->lock);
754
755 elem = bp->tx_old;
756 DTX(("bigmac_tx: tx_old[%d] ", elem));
757 while (elem != bp->tx_new) {
758 struct sk_buff *skb;
759 struct be_txd *this = &txbase[elem];
760
761 DTX(("this(%p) [flags(%08x)addr(%08x)]",
762 this, this->tx_flags, this->tx_addr));
763
764 if (this->tx_flags & TXD_OWN)
765 break;
766 skb = bp->tx_skbs[elem];
767 bp->enet_stats.tx_packets++;
768 bp->enet_stats.tx_bytes += skb->len;
769 sbus_unmap_single(bp->bigmac_sdev,
770 this->tx_addr, skb->len,
771 SBUS_DMA_TODEVICE);
772
773 DTX(("skb(%p) ", skb));
774 bp->tx_skbs[elem] = NULL;
775 dev_kfree_skb_irq(skb);
776
777 elem = NEXT_TX(elem);
778 }
779 DTX((" DONE, tx_old=%d\n", elem));
780 bp->tx_old = elem;
781
782 if (netif_queue_stopped(dev) &&
783 TX_BUFFS_AVAIL(bp) > 0)
784 netif_wake_queue(bp->dev);
785
786 spin_unlock(&bp->lock);
787 }
788
789 /* BigMAC receive complete service routines. */
790 static void bigmac_rx(struct bigmac *bp)
791 {
792 struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
793 struct be_rxd *this;
794 int elem = bp->rx_new, drops = 0;
795 u32 flags;
796
797 this = &rxbase[elem];
798 while (!((flags = this->rx_flags) & RXD_OWN)) {
799 struct sk_buff *skb;
800 int len = (flags & RXD_LENGTH); /* FCS not included */
801
802 /* Check for errors. */
803 if (len < ETH_ZLEN) {
804 bp->enet_stats.rx_errors++;
805 bp->enet_stats.rx_length_errors++;
806
807 drop_it:
808 /* Return it to the BigMAC. */
809 bp->enet_stats.rx_dropped++;
810 this->rx_flags =
811 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
812 goto next;
813 }
814 skb = bp->rx_skbs[elem];
815 if (len > RX_COPY_THRESHOLD) {
816 struct sk_buff *new_skb;
817
818 /* Now refill the entry, if we can. */
819 new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
820 if (new_skb == NULL) {
821 drops++;
822 goto drop_it;
823 }
824 sbus_unmap_single(bp->bigmac_sdev,
825 this->rx_addr,
826 RX_BUF_ALLOC_SIZE - 34,
827 SBUS_DMA_FROMDEVICE);
828 bp->rx_skbs[elem] = new_skb;
829 new_skb->dev = bp->dev;
830 skb_put(new_skb, ETH_FRAME_LEN);
831 skb_reserve(new_skb, 34);
832 this->rx_addr = sbus_map_single(bp->bigmac_sdev,
833 new_skb->data,
834 RX_BUF_ALLOC_SIZE - 34,
835 SBUS_DMA_FROMDEVICE);
836 this->rx_flags =
837 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
838
839 /* Trim the original skb for the netif. */
840 skb_trim(skb, len);
841 } else {
842 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
843
844 if (copy_skb == NULL) {
845 drops++;
846 goto drop_it;
847 }
848 copy_skb->dev = bp->dev;
849 skb_reserve(copy_skb, 2);
850 skb_put(copy_skb, len);
851 sbus_dma_sync_single(bp->bigmac_sdev,
852 this->rx_addr, len, SBUS_DMA_FROMDEVICE);
853 eth_copy_and_sum(copy_skb, (unsigned char *)skb->data, len, 0);
854
855 /* Reuse original ring buffer. */
856 this->rx_flags =
857 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
858
859 skb = copy_skb;
860 }
861
862 /* No checksums done by the BigMAC ;-( */
863 skb->protocol = eth_type_trans(skb, bp->dev);
864 netif_rx(skb);
865 bp->dev->last_rx = jiffies;
866 bp->enet_stats.rx_packets++;
867 bp->enet_stats.rx_bytes += len;
868 next:
869 elem = NEXT_RX(elem);
870 this = &rxbase[elem];
871 }
872 bp->rx_new = elem;
873 if (drops)
874 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name);
875 }
876
877 static irqreturn_t bigmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
878 {
879 struct bigmac *bp = (struct bigmac *) dev_id;
880 u32 qec_status, bmac_status;
881
882 DIRQ(("bigmac_interrupt: "));
883
884 /* Latch status registers now. */
885 bmac_status = sbus_readl(bp->creg + CREG_STAT);
886 qec_status = sbus_readl(bp->gregs + GLOB_STAT);
887
888 DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status));
889 if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) ||
890 (bmac_status & CREG_STAT_ERRORS))
891 bigmac_is_medium_rare(bp, qec_status, bmac_status);
892
893 if (bmac_status & CREG_STAT_TXIRQ)
894 bigmac_tx(bp);
895
896 if (bmac_status & CREG_STAT_RXIRQ)
897 bigmac_rx(bp);
898
899 return IRQ_HANDLED;
900 }
901
902 static int bigmac_open(struct net_device *dev)
903 {
904 struct bigmac *bp = (struct bigmac *) dev->priv;
905 int ret;
906
907 ret = request_irq(dev->irq, &bigmac_interrupt, SA_SHIRQ, dev->name, bp);
908 if (ret) {
909 printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq);
910 return ret;
911 }
912 init_timer(&bp->bigmac_timer);
913 ret = bigmac_init(bp, 0);
914 if (ret)
915 free_irq(dev->irq, bp);
916 return ret;
917 }
918
919 static int bigmac_close(struct net_device *dev)
920 {
921 struct bigmac *bp = (struct bigmac *) dev->priv;
922
923 del_timer(&bp->bigmac_timer);
924 bp->timer_state = asleep;
925 bp->timer_ticks = 0;
926
927 bigmac_stop(bp);
928 bigmac_clean_rings(bp);
929 free_irq(dev->irq, bp);
930 return 0;
931 }
932
933 static void bigmac_tx_timeout(struct net_device *dev)
934 {
935 struct bigmac *bp = (struct bigmac *) dev->priv;
936
937 bigmac_init(bp, 0);
938 netif_wake_queue(dev);
939 }
940
941 /* Put a packet on the wire. */
942 static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
943 {
944 struct bigmac *bp = (struct bigmac *) dev->priv;
945 int len, entry;
946 u32 mapping;
947
948 len = skb->len;
949 mapping = sbus_map_single(bp->bigmac_sdev, skb->data, len, SBUS_DMA_TODEVICE);
950
951 /* Avoid a race... */
952 spin_lock_irq(&bp->lock);
953 entry = bp->tx_new;
954 DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry));
955 bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
956 bp->tx_skbs[entry] = skb;
957 bp->bmac_block->be_txd[entry].tx_addr = mapping;
958 bp->bmac_block->be_txd[entry].tx_flags =
959 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
960 bp->tx_new = NEXT_TX(entry);
961 if (TX_BUFFS_AVAIL(bp) <= 0)
962 netif_stop_queue(dev);
963 spin_unlock_irq(&bp->lock);
964
965 /* Get it going. */
966 sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL);
967
968
969 dev->trans_start = jiffies;
970
971 return 0;
972 }
973
974 static struct net_device_stats *bigmac_get_stats(struct net_device *dev)
975 {
976 struct bigmac *bp = (struct bigmac *) dev->priv;
977
978 bigmac_get_counters(bp, bp->bregs);
979 return &bp->enet_stats;
980 }
981
982 static void bigmac_set_multicast(struct net_device *dev)
983 {
984 struct bigmac *bp = (struct bigmac *) dev->priv;
985 unsigned long bregs = bp->bregs;
986 struct dev_mc_list *dmi = dev->mc_list;
987 char *addrs;
988 int i;
989 u32 tmp, crc;
990
991 /* Disable the receiver. The bit self-clears when
992 * the operation is complete.
993 */
994 tmp = sbus_readl(bregs + BMAC_RXCFG);
995 tmp &= ~(BIGMAC_RXCFG_ENABLE);
996 sbus_writel(tmp, bregs + BMAC_RXCFG);
997 while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0)
998 udelay(20);
999
1000 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1001 sbus_writel(0xffff, bregs + BMAC_HTABLE0);
1002 sbus_writel(0xffff, bregs + BMAC_HTABLE1);
1003 sbus_writel(0xffff, bregs + BMAC_HTABLE2);
1004 sbus_writel(0xffff, bregs + BMAC_HTABLE3);
1005 } else if (dev->flags & IFF_PROMISC) {
1006 tmp = sbus_readl(bregs + BMAC_RXCFG);
1007 tmp |= BIGMAC_RXCFG_PMISC;
1008 sbus_writel(tmp, bregs + BMAC_RXCFG);
1009 } else {
1010 u16 hash_table[4];
1011
1012 for (i = 0; i < 4; i++)
1013 hash_table[i] = 0;
1014
1015 for (i = 0; i < dev->mc_count; i++) {
1016 addrs = dmi->dmi_addr;
1017 dmi = dmi->next;
1018
1019 if (!(*addrs & 1))
1020 continue;
1021
1022 crc = ether_crc_le(6, addrs);
1023 crc >>= 26;
1024 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1025 }
1026 sbus_writel(hash_table[0], bregs + BMAC_HTABLE0);
1027 sbus_writel(hash_table[1], bregs + BMAC_HTABLE1);
1028 sbus_writel(hash_table[2], bregs + BMAC_HTABLE2);
1029 sbus_writel(hash_table[3], bregs + BMAC_HTABLE3);
1030 }
1031
1032 /* Re-enable the receiver. */
1033 tmp = sbus_readl(bregs + BMAC_RXCFG);
1034 tmp |= BIGMAC_RXCFG_ENABLE;
1035 sbus_writel(tmp, bregs + BMAC_RXCFG);
1036 }
1037
1038 static int __init bigmac_ether_init(struct sbus_dev *qec_sdev)
1039 {
1040 struct net_device *dev;
1041 static int version_printed;
1042 struct bigmac *bp;
1043 u8 bsizes, bsizes_more;
1044 int i;
1045
1046 /* Get a new device struct for this interface. */
1047 dev = init_etherdev(NULL, sizeof(struct bigmac));
1048 if (!dev)
1049 return -ENOMEM;
1050 SET_MODULE_OWNER(dev);
1051
1052 if (version_printed++ == 0)
1053 printk(KERN_INFO "%s", version);
1054
1055 /* Report what we have found to the user. */
1056 printk(KERN_INFO "%s: BigMAC 100baseT Ethernet ", dev->name);
1057 dev->base_addr = (long) qec_sdev;
1058 for (i = 0; i < 6; i++)
1059 printk("%2.2x%c", dev->dev_addr[i] = idprom->id_ethaddr[i],
1060 i == 5 ? ' ' : ':');
1061 printk("\n");
1062
1063 /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
1064 bp = dev->priv;
1065 bp->qec_sdev = qec_sdev;
1066 bp->bigmac_sdev = qec_sdev->child;
1067
1068 spin_lock_init(&bp->lock);
1069
1070 /* Verify the registers we expect, are actually there. */
1071 if ((bp->bigmac_sdev->num_registers != 3) ||
1072 (bp->qec_sdev->num_registers != 2)) {
1073 printk(KERN_ERR "BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n",
1074 bp->qec_sdev->num_registers,
1075 bp->bigmac_sdev->num_registers);
1076 printk(KERN_ERR "BIGMAC: Would you like that for here or to go?\n");
1077 goto fail_and_cleanup;
1078 }
1079
1080 /* Map in QEC global control registers. */
1081 bp->gregs = sbus_ioremap(&bp->qec_sdev->resource[0], 0,
1082 GLOB_REG_SIZE, "BigMAC QEC GLobal Regs");
1083 if (!bp->gregs) {
1084 printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n");
1085 goto fail_and_cleanup;
1086 }
1087
1088 /* Make sure QEC is in BigMAC mode. */
1089 if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) {
1090 printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
1091 goto fail_and_cleanup;
1092 }
1093
1094 /* Reset the QEC. */
1095 if (qec_global_reset(bp->gregs))
1096 goto fail_and_cleanup;
1097
1098 /* Get supported SBUS burst sizes. */
1099 bsizes = prom_getintdefault(bp->qec_sdev->prom_node,
1100 "burst-sizes",
1101 0xff);
1102
1103 bsizes_more = prom_getintdefault(bp->qec_sdev->bus->prom_node,
1104 "burst-sizes",
1105 0xff);
1106
1107 bsizes &= 0xff;
1108 if (bsizes_more != 0xff)
1109 bsizes &= bsizes_more;
1110 if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
1111 (bsizes & DMA_BURST32) == 0)
1112 bsizes = (DMA_BURST32 - 1);
1113 bp->bigmac_bursts = bsizes;
1114
1115 /* Perform QEC initialization. */
1116 qec_init(bp);
1117
1118 /* Map in the BigMAC channel registers. */
1119 bp->creg = sbus_ioremap(&bp->bigmac_sdev->resource[0], 0,
1120 CREG_REG_SIZE, "BigMAC QEC Channel Regs");
1121 if (!bp->creg) {
1122 printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n");
1123 goto fail_and_cleanup;
1124 }
1125
1126 /* Map in the BigMAC control registers. */
1127 bp->bregs = sbus_ioremap(&bp->bigmac_sdev->resource[1], 0,
1128 BMAC_REG_SIZE, "BigMAC Primary Regs");
1129 if (!bp->bregs) {
1130 printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n");
1131 goto fail_and_cleanup;
1132 }
1133
1134 /* Map in the BigMAC transceiver registers, this is how you poke at
1135 * the BigMAC's PHY.
1136 */
1137 bp->tregs = sbus_ioremap(&bp->bigmac_sdev->resource[2], 0,
1138 TCVR_REG_SIZE, "BigMAC Transceiver Regs");
1139 if (!bp->tregs) {
1140 printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n");
1141 goto fail_and_cleanup;
1142 }
1143
1144 /* Stop the BigMAC. */
1145 bigmac_stop(bp);
1146
1147 /* Allocate transmit/receive descriptor DVMA block. */
1148 bp->bmac_block = sbus_alloc_consistent(bp->bigmac_sdev,
1149 PAGE_SIZE,
1150 &bp->bblock_dvma);
1151 if (bp->bmac_block == NULL || bp->bblock_dvma == 0) {
1152 printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n");
1153 goto fail_and_cleanup;
1154 }
1155
1156 /* Get the board revision of this BigMAC. */
1157 bp->board_rev = prom_getintdefault(bp->bigmac_sdev->prom_node,
1158 "board-version", 1);
1159
1160 /* Init auto-negotiation timer state. */
1161 init_timer(&bp->bigmac_timer);
1162 bp->timer_state = asleep;
1163 bp->timer_ticks = 0;
1164
1165 /* Backlink to generic net device struct. */
1166 bp->dev = dev;
1167
1168 /* Set links to our BigMAC open and close routines. */
1169 dev->open = &bigmac_open;
1170 dev->stop = &bigmac_close;
1171 dev->hard_start_xmit = &bigmac_start_xmit;
1172
1173 /* Set links to BigMAC statistic and multi-cast loading code. */
1174 dev->get_stats = &bigmac_get_stats;
1175 dev->set_multicast_list = &bigmac_set_multicast;
1176
1177 dev->tx_timeout = &bigmac_tx_timeout;
1178 dev->watchdog_timeo = 5*HZ;
1179
1180 /* Finish net device registration. */
1181 dev->irq = bp->bigmac_sdev->irqs[0];
1182 dev->dma = 0;
1183
1184 /* Put us into the list of instances attached for later driver
1185 * exit.
1186 */
1187 bp->next_module = root_bigmac_dev;
1188 root_bigmac_dev = bp;
1189
1190 return 0;
1191
1192 fail_and_cleanup:
1193 /* Something went wrong, undo whatever we did so far. */
1194 /* Free register mappings if any. */
1195 if (bp->gregs)
1196 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1197 if (bp->creg)
1198 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1199 if (bp->bregs)
1200 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1201 if (bp->tregs)
1202 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1203
1204 if (bp->bmac_block)
1205 sbus_free_consistent(bp->bigmac_sdev,
1206 PAGE_SIZE,
1207 bp->bmac_block,
1208 bp->bblock_dvma);
1209
1210 unregister_netdev(dev);
1211 /* This also frees the co-located 'dev->priv' */
1212 kfree(dev);
1213 return -ENODEV;
1214 }
1215
1216 /* QEC can be the parent of either QuadEthernet or
1217 * a BigMAC. We want the latter.
1218 */
1219 static int __init bigmac_match(struct sbus_dev *sdev)
1220 {
1221 struct sbus_dev *child = sdev->child;
1222
1223 if (strcmp(sdev->prom_name, "qec") != 0)
1224 return 0;
1225
1226 if (child == NULL)
1227 return 0;
1228
1229 if (strcmp(child->prom_name, "be") != 0)
1230 return 0;
1231
1232 return 1;
1233 }
1234
1235 static int __init bigmac_probe(void)
1236 {
1237 struct sbus_bus *sbus;
1238 struct sbus_dev *sdev = 0;
1239 static int called;
1240 int cards = 0, v;
1241
1242 root_bigmac_dev = NULL;
1243
1244 if (called)
1245 return -ENODEV;
1246 called++;
1247
1248 for_each_sbus(sbus) {
1249 for_each_sbusdev(sdev, sbus) {
1250 if (bigmac_match(sdev)) {
1251 cards++;
1252 if ((v = bigmac_ether_init(sdev)))
1253 return v;
1254 }
1255 }
1256 }
1257 if (!cards)
1258 return -ENODEV;
1259 return 0;
1260 }
1261
1262 static void __exit bigmac_cleanup(void)
1263 {
1264 while (root_bigmac_dev) {
1265 struct bigmac *bp = root_bigmac_dev;
1266 struct bigmac *bp_nxt = root_bigmac_dev->next_module;
1267
1268 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1269 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1270 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1271 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1272 sbus_free_consistent(bp->bigmac_sdev,
1273 PAGE_SIZE,
1274 bp->bmac_block,
1275 bp->bblock_dvma);
1276
1277 unregister_netdev(bp->dev);
1278 kfree(bp->dev);
1279 root_bigmac_dev = bp_nxt;
1280 }
1281 }
1282
1283 module_init(bigmac_probe);
1284 module_exit(bigmac_cleanup);
1285 MODULE_LICENSE("GPL");
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