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[linux-2.6/linux-mips.git] / drivers / net / r8169.c
blob9b7c3f8f03547e99e1ee4cc3a529f348a3a6ce20
1 /*
2 =========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 =========================================================================
10 1. The media can be forced in 5 modes.
11 Command: 'insmod r8169 media = SET_MEDIA'
12 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
13
14 SET_MEDIA can be:
15 _10_Half = 0x01
16 _10_Full = 0x02
17 _100_Half = 0x04
18 _100_Full = 0x08
19 _1000_Full = 0x10
20
21 2. Support TBI mode.
22 =========================================================================
23 VERSION 1.1 <2002/10/4>
24
25 The bit4:0 of MII register 4 is called "selector field", and have to be
26 00001b to indicate support of IEEE std 802.3 during NWay process of
27 exchanging Link Code Word (FLP).
28
29 VERSION 1.2 <2002/11/30>
30
31 - Large style cleanup
32 - Use ether_crc in stock kernel (linux/crc32.h)
33 - Copy mc_filter setup code from 8139cp
34 (includes an optimization, and avoids set_bit use)
35
36 */
37
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/delay.h>
43 #include <linux/crc32.h>
44 #include <linux/init.h>
45
46 #include <asm/io.h>
47
48 #define RTL8169_VERSION "1.2"
49 #define MODULENAME "r8169"
50 #define RTL8169_DRIVER_NAME MODULENAME " Gigabit Ethernet driver " RTL8169_VERSION
51 #define PFX MODULENAME ": "
52
53 #ifdef RTL8169_DEBUG
54 #define assert(expr) \
55 if(!(expr)) { \
56 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
57 #expr,__FILE__,__FUNCTION__,__LINE__); \
58 }
59 #else
60 #define assert(expr) do {} while (0)
61 #endif
62
63 /* media options */
64 #define MAX_UNITS 8
65 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
66
67 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
68 static int max_interrupt_work = 20;
69
70 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
71 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
72 static int multicast_filter_limit = 32;
73
74 /* MAC address length*/
75 #define MAC_ADDR_LEN 6
76
77 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
78 #define MAX_ETH_FRAME_SIZE 1536
79
80 #define TX_FIFO_THRESH 256 /* In bytes */
81
82 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
83 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
84 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
85 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
86 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
87 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
88
89 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
90 #define NUM_RX_DESC 64 /* Number of Rx descriptor registers */
91 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
92
93 #define RTL_MIN_IO_SIZE 0x80
94 #define TX_TIMEOUT (6*HZ)
95
96 /* write/read MMIO register */
97 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
98 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
99 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
100 #define RTL_R8(reg) readb (ioaddr + (reg))
101 #define RTL_R16(reg) readw (ioaddr + (reg))
102 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
103
104 static struct {
105 const char *name;
106 } board_info[] __devinitdata = {
107 {
108 "RealTek RTL8169 Gigabit Ethernet"},};
109
110 static struct pci_device_id rtl8169_pci_tbl[] __devinitdata = {
111 {0x10ec, 0x8169, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
112 {0,},
113 };
114
115 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
116
117 enum RTL8169_registers {
118 MAC0 = 0, /* Ethernet hardware address. */
119 MAR0 = 8, /* Multicast filter. */
120 TxDescStartAddr = 0x20,
121 TxHDescStartAddr = 0x28,
122 FLASH = 0x30,
123 ERSR = 0x36,
124 ChipCmd = 0x37,
125 TxPoll = 0x38,
126 IntrMask = 0x3C,
127 IntrStatus = 0x3E,
128 TxConfig = 0x40,
129 RxConfig = 0x44,
130 RxMissed = 0x4C,
131 Cfg9346 = 0x50,
132 Config0 = 0x51,
133 Config1 = 0x52,
134 Config2 = 0x53,
135 Config3 = 0x54,
136 Config4 = 0x55,
137 Config5 = 0x56,
138 MultiIntr = 0x5C,
139 PHYAR = 0x60,
140 TBICSR = 0x64,
141 TBI_ANAR = 0x68,
142 TBI_LPAR = 0x6A,
143 PHYstatus = 0x6C,
144 RxMaxSize = 0xDA,
145 CPlusCmd = 0xE0,
146 RxDescStartAddr = 0xE4,
147 EarlyTxThres = 0xEC,
148 FuncEvent = 0xF0,
149 FuncEventMask = 0xF4,
150 FuncPresetState = 0xF8,
151 FuncForceEvent = 0xFC,
152 };
153
154 enum RTL8169_register_content {
155 /*InterruptStatusBits */
156 SYSErr = 0x8000,
157 PCSTimeout = 0x4000,
158 SWInt = 0x0100,
159 TxDescUnavail = 0x80,
160 RxFIFOOver = 0x40,
161 RxUnderrun = 0x20,
162 RxOverflow = 0x10,
163 TxErr = 0x08,
164 TxOK = 0x04,
165 RxErr = 0x02,
166 RxOK = 0x01,
167
168 /*RxStatusDesc */
169 RxRES = 0x00200000,
170 RxCRC = 0x00080000,
171 RxRUNT = 0x00100000,
172 RxRWT = 0x00400000,
173
174 /*ChipCmdBits */
175 CmdReset = 0x10,
176 CmdRxEnb = 0x08,
177 CmdTxEnb = 0x04,
178 RxBufEmpty = 0x01,
179
180 /*Cfg9346Bits */
181 Cfg9346_Lock = 0x00,
182 Cfg9346_Unlock = 0xC0,
183
184 /*rx_mode_bits */
185 AcceptErr = 0x20,
186 AcceptRunt = 0x10,
187 AcceptBroadcast = 0x08,
188 AcceptMulticast = 0x04,
189 AcceptMyPhys = 0x02,
190 AcceptAllPhys = 0x01,
191
192 /*RxConfigBits */
193 RxCfgFIFOShift = 13,
194 RxCfgDMAShift = 8,
195
196 /*TxConfigBits */
197 TxInterFrameGapShift = 24,
198 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
199
200 /*rtl8169_PHYstatus */
201 TBI_Enable = 0x80,
202 TxFlowCtrl = 0x40,
203 RxFlowCtrl = 0x20,
204 _1000bpsF = 0x10,
205 _100bps = 0x08,
206 _10bps = 0x04,
207 LinkStatus = 0x02,
208 FullDup = 0x01,
209
210 /*GIGABIT_PHY_registers */
211 PHY_CTRL_REG = 0,
212 PHY_STAT_REG = 1,
213 PHY_AUTO_NEGO_REG = 4,
214 PHY_1000_CTRL_REG = 9,
215
216 /*GIGABIT_PHY_REG_BIT */
217 PHY_Restart_Auto_Nego = 0x0200,
218 PHY_Enable_Auto_Nego = 0x1000,
219
220 //PHY_STAT_REG = 1;
221 PHY_Auto_Neco_Comp = 0x0020,
222
223 //PHY_AUTO_NEGO_REG = 4;
224 PHY_Cap_10_Half = 0x0020,
225 PHY_Cap_10_Full = 0x0040,
226 PHY_Cap_100_Half = 0x0080,
227 PHY_Cap_100_Full = 0x0100,
228
229 //PHY_1000_CTRL_REG = 9;
230 PHY_Cap_1000_Full = 0x0200,
231
232 PHY_Cap_Null = 0x0,
233
234 /*_MediaType*/
235 _10_Half = 0x01,
236 _10_Full = 0x02,
237 _100_Half = 0x04,
238 _100_Full = 0x08,
239 _1000_Full = 0x10,
240
241 /*_TBICSRBit*/
242 TBILinkOK = 0x02000000,
243 };
244
245 const static struct {
246 const char *name;
247 u8 version; /* depend on RTL8169 docs */
248 u32 RxConfigMask; /* should clear the bits supported by this chip */
249 } rtl_chip_info[] = {
250 {
251 "RTL-8169", 0x00, 0xff7e1880,},};
252
253 enum _DescStatusBit {
254 OWNbit = 0x80000000,
255 EORbit = 0x40000000,
256 FSbit = 0x20000000,
257 LSbit = 0x10000000,
258 };
259
260 struct TxDesc {
261 u32 status;
262 u32 vlan_tag;
263 u32 buf_addr;
264 u32 buf_Haddr;
265 };
266
267 struct RxDesc {
268 u32 status;
269 u32 vlan_tag;
270 u32 buf_addr;
271 u32 buf_Haddr;
272 };
273
274 struct rtl8169_private {
275 void *mmio_addr; /* memory map physical address */
276 struct pci_dev *pci_dev; /* Index of PCI device */
277 struct net_device_stats stats; /* statistics of net device */
278 spinlock_t lock; /* spin lock flag */
279 int chipset;
280 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
281 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
282 unsigned long dirty_tx;
283 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
284 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
285 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
286 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
287 unsigned char *RxBufferRings; /* Index of Rx Buffer */
288 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
289 struct sk_buff *Tx_skbuff[NUM_TX_DESC]; /* Index of Transmit data buffer */
290 };
291
292 MODULE_AUTHOR("Realtek");
293 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
294 MODULE_PARM(media, "1-" __MODULE_STRING(MAX_UNITS) "i");
295
296 static int rtl8169_open(struct net_device *dev);
297 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
298 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
299 struct pt_regs *regs);
300 static void rtl8169_init_ring(struct net_device *dev);
301 static void rtl8169_hw_start(struct net_device *dev);
302 static int rtl8169_close(struct net_device *dev);
303 static void rtl8169_set_rx_mode(struct net_device *dev);
304 static void rtl8169_tx_timeout(struct net_device *dev);
305 static struct net_device_stats *rtl8169_get_stats(struct net_device *netdev);
306
307 static const u16 rtl8169_intr_mask =
308 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | TxOK |
309 RxErr | RxOK;
310 static const unsigned int rtl8169_rx_config =
311 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
312
313 void
314 mdio_write(void *ioaddr, int RegAddr, int value)
315 {
316 int i;
317
318 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
319 udelay(1000);
320
321 for (i = 2000; i > 0; i--) {
322 // Check if the RTL8169 has completed writing to the specified MII register
323 if (!(RTL_R32(PHYAR) & 0x80000000)) {
324 break;
325 } else {
326 udelay(100);
327 }
328 }
329 }
330
331 int
332 mdio_read(void *ioaddr, int RegAddr)
333 {
334 int i, value = -1;
335
336 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
337 udelay(1000);
338
339 for (i = 2000; i > 0; i--) {
340 // Check if the RTL8169 has completed retrieving data from the specified MII register
341 if (RTL_R32(PHYAR) & 0x80000000) {
342 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
343 break;
344 } else {
345 udelay(100);
346 }
347 }
348 return value;
349 }
350
351 static int __devinit
352 rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
353 void **ioaddr_out)
354 {
355 void *ioaddr = NULL;
356 struct net_device *dev;
357 struct rtl8169_private *tp;
358 int rc, i;
359 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
360 u32 tmp;
361
362 assert(pdev != NULL);
363 assert(ioaddr_out != NULL);
364
365 *ioaddr_out = NULL;
366 *dev_out = NULL;
367
368 // dev zeroed in alloc_etherdev
369 dev = alloc_etherdev(sizeof (*tp));
370 if (dev == NULL) {
371 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
372 return -ENOMEM;
373 }
374
375 SET_MODULE_OWNER(dev);
376 SET_NETDEV_DEV(dev, &pdev->dev);
377 tp = dev->priv;
378
379 // enable device (incl. PCI PM wakeup and hotplug setup)
380 rc = pci_enable_device(pdev);
381 if (rc)
382 goto err_out;
383
384 mmio_start = pci_resource_start(pdev, 1);
385 mmio_end = pci_resource_end(pdev, 1);
386 mmio_flags = pci_resource_flags(pdev, 1);
387 mmio_len = pci_resource_len(pdev, 1);
388
389 // make sure PCI base addr 1 is MMIO
390 if (!(mmio_flags & IORESOURCE_MEM)) {
391 printk(KERN_ERR PFX
392 "region #1 not an MMIO resource, aborting\n");
393 rc = -ENODEV;
394 goto err_out_disable;
395 }
396 // check for weird/broken PCI region reporting
397 if (mmio_len < RTL_MIN_IO_SIZE) {
398 printk(KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
399 rc = -ENODEV;
400 goto err_out_disable;
401 }
402
403 rc = pci_request_regions(pdev, dev->name);
404 if (rc)
405 goto err_out_disable;
406
407 // enable PCI bus-mastering
408 pci_set_master(pdev);
409
410 // ioremap MMIO region
411 ioaddr = ioremap(mmio_start, mmio_len);
412 if (ioaddr == NULL) {
413 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
414 rc = -EIO;
415 goto err_out_free_res;
416 }
417
418 // Soft reset the chip.
419 RTL_W8(ChipCmd, CmdReset);
420
421 // Check that the chip has finished the reset.
422 for (i = 1000; i > 0; i--)
423 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
424 break;
425 else
426 udelay(10);
427
428 // identify chip attached to board
429 tmp = RTL_R32(TxConfig);
430 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
431
432 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
433 if (tmp == rtl_chip_info[i].version) {
434 tp->chipset = i;
435 goto match;
436 }
437 //if unknown chip, assume array element #0, original RTL-8169 in this case
438 printk(KERN_DEBUG PFX
439 "PCI device %s: unknown chip version, assuming RTL-8169\n",
440 pdev->slot_name);
441 printk(KERN_DEBUG PFX "PCI device %s: TxConfig = 0x%lx\n",
442 pdev->slot_name, (unsigned long) RTL_R32(TxConfig));
443 tp->chipset = 0;
444
445 match:
446 *ioaddr_out = ioaddr;
447 *dev_out = dev;
448 return 0;
449
450 err_out_free_res:
451 pci_release_regions(pdev);
452
453 err_out_disable:
454 pci_disable_device(pdev);
455
456 err_out:
457 kfree(dev);
458 return rc;
459 }
460
461 static int __devinit
462 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
463 {
464 struct net_device *dev = NULL;
465 struct rtl8169_private *tp = NULL;
466 void *ioaddr = NULL;
467 static int board_idx = -1;
468 static int printed_version = 0;
469 int i, rc;
470 int option = -1, Cap10_100 = 0, Cap1000 = 0;
471
472 assert(pdev != NULL);
473 assert(ent != NULL);
474
475 board_idx++;
476
477 if (!printed_version) {
478 printk(KERN_INFO RTL8169_DRIVER_NAME " loaded\n");
479 printed_version = 1;
480 }
481
482 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
483 if (rc)
484 return rc;
485
486 tp = dev->priv;
487 assert(ioaddr != NULL);
488 assert(dev != NULL);
489 assert(tp != NULL);
490
491 // Get MAC address. FIXME: read EEPROM
492 for (i = 0; i < MAC_ADDR_LEN; i++)
493 dev->dev_addr[i] = RTL_R8(MAC0 + i);
494
495 dev->open = rtl8169_open;
496 dev->hard_start_xmit = rtl8169_start_xmit;
497 dev->get_stats = rtl8169_get_stats;
498 dev->stop = rtl8169_close;
499 dev->tx_timeout = rtl8169_tx_timeout;
500 dev->set_multicast_list = rtl8169_set_rx_mode;
501 dev->watchdog_timeo = TX_TIMEOUT;
502 dev->irq = pdev->irq;
503 dev->base_addr = (unsigned long) ioaddr;
504 // dev->do_ioctl = mii_ioctl;
505
506 tp = dev->priv; // private data //
507 tp->pci_dev = pdev;
508 tp->mmio_addr = ioaddr;
509
510 spin_lock_init(&tp->lock);
511
512 rc = register_netdev(dev);
513 if (rc) {
514 iounmap(ioaddr);
515 pci_release_regions(pdev);
516 pci_disable_device(pdev);
517 kfree(dev);
518 return rc;
519 }
520
521 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", dev->name,
522 rtl_chip_info[tp->chipset].name);
523
524 pci_set_drvdata(pdev, dev);
525
526 printk(KERN_INFO "%s: %s at 0x%lx, "
527 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
528 "IRQ %d\n",
529 dev->name,
530 board_info[ent->driver_data].name,
531 dev->base_addr,
532 dev->dev_addr[0], dev->dev_addr[1],
533 dev->dev_addr[2], dev->dev_addr[3],
534 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
535
536 // if TBI is not endbled
537 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
538 int val = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
539
540 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
541 // Force RTL8169 in 10/100/1000 Full/Half mode.
542 if (option > 0) {
543 printk(KERN_INFO "%s: Force-mode Enabled.\n",
544 dev->name);
545 Cap10_100 = 0, Cap1000 = 0;
546 switch (option) {
547 case _10_Half:
548 Cap10_100 = PHY_Cap_10_Half;
549 Cap1000 = PHY_Cap_Null;
550 break;
551 case _10_Full:
552 Cap10_100 = PHY_Cap_10_Full;
553 Cap1000 = PHY_Cap_Null;
554 break;
555 case _100_Half:
556 Cap10_100 = PHY_Cap_100_Half;
557 Cap1000 = PHY_Cap_Null;
558 break;
559 case _100_Full:
560 Cap10_100 = PHY_Cap_100_Full;
561 Cap1000 = PHY_Cap_Null;
562 break;
563 case _1000_Full:
564 Cap10_100 = PHY_Cap_Null;
565 Cap1000 = PHY_Cap_1000_Full;
566 break;
567 default:
568 break;
569 }
570 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); //leave PHY_AUTO_NEGO_REG bit4:0 unchanged
571 mdio_write(ioaddr, PHY_1000_CTRL_REG, Cap1000);
572 } else {
573 printk(KERN_INFO "%s: Auto-negotiation Enabled.\n",
574 dev->name);
575
576 // enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
577 mdio_write(ioaddr, PHY_AUTO_NEGO_REG,
578 PHY_Cap_10_Half | PHY_Cap_10_Full |
579 PHY_Cap_100_Half | PHY_Cap_100_Full | (val &
580 0x1F));
581
582 // enable 1000 Full Mode
583 mdio_write(ioaddr, PHY_1000_CTRL_REG,
584 PHY_Cap_1000_Full);
585
586 }
587
588 // Enable auto-negotiation and restart auto-nigotiation
589 mdio_write(ioaddr, PHY_CTRL_REG,
590 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
591 udelay(100);
592
593 // wait for auto-negotiation process
594 for (i = 10000; i > 0; i--) {
595 //check if auto-negotiation complete
596 if (mdio_read(ioaddr, PHY_STAT_REG) &
597 PHY_Auto_Neco_Comp) {
598 udelay(100);
599 option = RTL_R8(PHYstatus);
600 if (option & _1000bpsF) {
601 printk(KERN_INFO
602 "%s: 1000Mbps Full-duplex operation.\n",
603 dev->name);
604 } else {
605 printk(KERN_INFO
606 "%s: %sMbps %s-duplex operation.\n",
607 dev->name,
608 (option & _100bps) ? "100" :
609 "10",
610 (option & FullDup) ? "Full" :
611 "Half");
612 }
613 break;
614 } else {
615 udelay(100);
616 }
617 } // end for-loop to wait for auto-negotiation process
618
619 } else {
620 udelay(100);
621 printk(KERN_INFO
622 "%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
623 dev->name,
624 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
625
626 }
627
628 return 0;
629 }
630
631 static void __devexit
632 rtl8169_remove_one(struct pci_dev *pdev)
633 {
634 struct net_device *dev = pci_get_drvdata(pdev);
635 struct rtl8169_private *tp = dev->priv;
636
637 assert(dev != NULL);
638 assert(tp != NULL);
639
640 unregister_netdev(dev);
641 iounmap(tp->mmio_addr);
642 pci_release_regions(pdev);
643
644 // poison memory before freeing
645 memset(dev, 0xBC,
646 sizeof (struct net_device) + sizeof (struct rtl8169_private));
647
648 pci_disable_device(pdev);
649 kfree(dev);
650 pci_set_drvdata(pdev, NULL);
651 }
652
653 static int
654 rtl8169_open(struct net_device *dev)
655 {
656 struct rtl8169_private *tp = dev->priv;
657 int retval;
658 u8 diff;
659 u32 TxPhyAddr, RxPhyAddr;
660
661 retval =
662 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
663 if (retval) {
664 return retval;
665 }
666
667 tp->TxDescArrays =
668 kmalloc(NUM_TX_DESC * sizeof (struct TxDesc) + 256, GFP_KERNEL);
669 // Tx Desscriptor needs 256 bytes alignment;
670 TxPhyAddr = virt_to_bus(tp->TxDescArrays);
671 diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8));
672 TxPhyAddr += diff;
673 tp->TxDescArray = (struct TxDesc *) (tp->TxDescArrays + diff);
674
675 tp->RxDescArrays =
676 kmalloc(NUM_RX_DESC * sizeof (struct RxDesc) + 256, GFP_KERNEL);
677 // Rx Desscriptor needs 256 bytes alignment;
678 RxPhyAddr = virt_to_bus(tp->RxDescArrays);
679 diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8));
680 RxPhyAddr += diff;
681 tp->RxDescArray = (struct RxDesc *) (tp->RxDescArrays + diff);
682
683 if (tp->TxDescArrays == NULL || tp->RxDescArrays == NULL) {
684 printk(KERN_INFO
685 "Allocate RxDescArray or TxDescArray failed\n");
686 free_irq(dev->irq, dev);
687 if (tp->TxDescArrays)
688 kfree(tp->TxDescArrays);
689 if (tp->RxDescArrays)
690 kfree(tp->RxDescArrays);
691 return -ENOMEM;
692 }
693 tp->RxBufferRings = kmalloc(RX_BUF_SIZE * NUM_RX_DESC, GFP_KERNEL);
694 if (tp->RxBufferRings == NULL) {
695 printk(KERN_INFO "Allocate RxBufferRing failed\n");
696 }
697
698 rtl8169_init_ring(dev);
699 rtl8169_hw_start(dev);
700
701 return 0;
702
703 }
704
705 static void
706 rtl8169_hw_start(struct net_device *dev)
707 {
708 struct rtl8169_private *tp = dev->priv;
709 void *ioaddr = tp->mmio_addr;
710 u32 i;
711
712 /* Soft reset the chip. */
713 RTL_W8(ChipCmd, CmdReset);
714
715 /* Check that the chip has finished the reset. */
716 for (i = 1000; i > 0; i--) {
717 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
718 break;
719 else
720 udelay(10);
721 }
722
723 RTL_W8(Cfg9346, Cfg9346_Unlock);
724 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
725 RTL_W8(EarlyTxThres, EarlyTxThld);
726
727 // For gigabit rtl8169
728 RTL_W16(RxMaxSize, RxPacketMaxSize);
729
730 // Set Rx Config register
731 i = rtl8169_rx_config | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].
732 RxConfigMask);
733 RTL_W32(RxConfig, i);
734
735 /* Set DMA burst size and Interframe Gap Time */
736 RTL_W32(TxConfig,
737 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
738 TxInterFrameGapShift));
739
740 tp->cur_rx = 0;
741
742 RTL_W32(TxDescStartAddr, virt_to_bus(tp->TxDescArray));
743 RTL_W32(RxDescStartAddr, virt_to_bus(tp->RxDescArray));
744 RTL_W8(Cfg9346, Cfg9346_Lock);
745 udelay(10);
746
747 RTL_W32(RxMissed, 0);
748
749 rtl8169_set_rx_mode(dev);
750
751 /* no early-rx interrupts */
752 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
753
754 /* Enable all known interrupts by setting the interrupt mask. */
755 RTL_W16(IntrMask, rtl8169_intr_mask);
756
757 netif_start_queue(dev);
758
759 }
760
761 static void
762 rtl8169_init_ring(struct net_device *dev)
763 {
764 struct rtl8169_private *tp = dev->priv;
765 int i;
766
767 tp->cur_rx = 0;
768 tp->cur_tx = 0;
769 tp->dirty_tx = 0;
770 memset(tp->TxDescArray, 0x0, NUM_TX_DESC * sizeof (struct TxDesc));
771 memset(tp->RxDescArray, 0x0, NUM_RX_DESC * sizeof (struct RxDesc));
772
773 for (i = 0; i < NUM_TX_DESC; i++) {
774 tp->Tx_skbuff[i] = NULL;
775 }
776 for (i = 0; i < NUM_RX_DESC; i++) {
777 if (i == (NUM_RX_DESC - 1))
778 tp->RxDescArray[i].status =
779 (OWNbit | EORbit) + RX_BUF_SIZE;
780 else
781 tp->RxDescArray[i].status = OWNbit + RX_BUF_SIZE;
782
783 tp->RxBufferRing[i] = &(tp->RxBufferRings[i * RX_BUF_SIZE]);
784 tp->RxDescArray[i].buf_addr = virt_to_bus(tp->RxBufferRing[i]);
785 }
786 }
787
788 static void
789 rtl8169_tx_clear(struct rtl8169_private *tp)
790 {
791 int i;
792
793 tp->cur_tx = 0;
794 for (i = 0; i < NUM_TX_DESC; i++) {
795 if (tp->Tx_skbuff[i] != NULL) {
796 dev_kfree_skb(tp->Tx_skbuff[i]);
797 tp->Tx_skbuff[i] = NULL;
798 tp->stats.tx_dropped++;
799 }
800 }
801 }
802
803 static void
804 rtl8169_tx_timeout(struct net_device *dev)
805 {
806 struct rtl8169_private *tp = dev->priv;
807 void *ioaddr = tp->mmio_addr;
808 u8 tmp8;
809
810 /* disable Tx, if not already */
811 tmp8 = RTL_R8(ChipCmd);
812 if (tmp8 & CmdTxEnb)
813 RTL_W8(ChipCmd, tmp8 & ~CmdTxEnb);
814
815 /* Disable interrupts by clearing the interrupt mask. */
816 RTL_W16(IntrMask, 0x0000);
817
818 /* Stop a shared interrupt from scavenging while we are. */
819 spin_lock_irq(&tp->lock);
820 rtl8169_tx_clear(tp);
821 spin_unlock_irq(&tp->lock);
822
823 /* ...and finally, reset everything */
824 rtl8169_hw_start(dev);
825
826 netif_wake_queue(dev);
827 }
828
829 static int
830 rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
831 {
832 struct rtl8169_private *tp = dev->priv;
833 void *ioaddr = tp->mmio_addr;
834 int entry = tp->cur_tx % NUM_TX_DESC;
835
836 if (skb->len < ETH_ZLEN) {
837 skb = skb_padto(skb, ETH_ZLEN);
838 if (skb == NULL)
839 return 0;
840 }
841
842 spin_lock_irq(&tp->lock);
843
844 if ((tp->TxDescArray[entry].status & OWNbit) == 0) {
845 tp->Tx_skbuff[entry] = skb;
846 tp->TxDescArray[entry].buf_addr = virt_to_bus(skb->data);
847 if (entry != (NUM_TX_DESC - 1))
848 tp->TxDescArray[entry].status =
849 (OWNbit | FSbit | LSbit) | ((skb->len > ETH_ZLEN) ?
850 skb->len : ETH_ZLEN);
851 else
852 tp->TxDescArray[entry].status =
853 (OWNbit | EORbit | FSbit | LSbit) |
854 ((skb->len > ETH_ZLEN) ? skb->len : ETH_ZLEN);
855
856 RTL_W8(TxPoll, 0x40); //set polling bit
857
858 dev->trans_start = jiffies;
859
860 tp->cur_tx++;
861 }
862
863 spin_unlock_irq(&tp->lock);
864
865 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) {
866 netif_stop_queue(dev);
867 }
868
869 return 0;
870 }
871
872 static void
873 rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
874 void *ioaddr)
875 {
876 unsigned long dirty_tx, tx_left = 0;
877 int entry = tp->cur_tx % NUM_TX_DESC;
878
879 assert(dev != NULL);
880 assert(tp != NULL);
881 assert(ioaddr != NULL);
882
883 dirty_tx = tp->dirty_tx;
884 tx_left = tp->cur_tx - dirty_tx;
885
886 while (tx_left > 0) {
887 if ((tp->TxDescArray[entry].status & OWNbit) == 0) {
888 dev_kfree_skb_irq(tp->
889 Tx_skbuff[dirty_tx % NUM_TX_DESC]);
890 tp->Tx_skbuff[dirty_tx % NUM_TX_DESC] = NULL;
891 tp->stats.tx_packets++;
892 dirty_tx++;
893 tx_left--;
894 entry++;
895 }
896 }
897
898 if (tp->dirty_tx != dirty_tx) {
899 tp->dirty_tx = dirty_tx;
900 if (netif_queue_stopped(dev))
901 netif_wake_queue(dev);
902 }
903 }
904
905 static void
906 rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
907 void *ioaddr)
908 {
909 int cur_rx;
910 struct sk_buff *skb;
911 int pkt_size = 0;
912
913 assert(dev != NULL);
914 assert(tp != NULL);
915 assert(ioaddr != NULL);
916
917 cur_rx = tp->cur_rx;
918
919 while ((tp->RxDescArray[cur_rx].status & OWNbit) == 0) {
920
921 if (tp->RxDescArray[cur_rx].status & RxRES) {
922 printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name);
923 tp->stats.rx_errors++;
924 if (tp->RxDescArray[cur_rx].status & (RxRWT | RxRUNT))
925 tp->stats.rx_length_errors++;
926 if (tp->RxDescArray[cur_rx].status & RxCRC)
927 tp->stats.rx_crc_errors++;
928 } else {
929 pkt_size =
930 (int) (tp->RxDescArray[cur_rx].
931 status & 0x00001FFF) - 4;
932 skb = dev_alloc_skb(pkt_size + 2);
933 if (skb != NULL) {
934 skb->dev = dev;
935 skb_reserve(skb, 2); // 16 byte align the IP fields. //
936 eth_copy_and_sum(skb, tp->RxBufferRing[cur_rx],
937 pkt_size, 0);
938 skb_put(skb, pkt_size);
939 skb->protocol = eth_type_trans(skb, dev);
940 netif_rx(skb);
941
942 if (cur_rx == (NUM_RX_DESC - 1))
943 tp->RxDescArray[cur_rx].status =
944 (OWNbit | EORbit) + RX_BUF_SIZE;
945 else
946 tp->RxDescArray[cur_rx].status =
947 OWNbit + RX_BUF_SIZE;
948
949 tp->RxDescArray[cur_rx].buf_addr =
950 virt_to_bus(tp->RxBufferRing[cur_rx]);
951 dev->last_rx = jiffies;
952 tp->stats.rx_bytes += pkt_size;
953 tp->stats.rx_packets++;
954 } else {
955 printk(KERN_WARNING
956 "%s: Memory squeeze, deferring packet.\n",
957 dev->name);
958 /* We should check that some rx space is free.
959 If not, free one and mark stats->rx_dropped++. */
960 tp->stats.rx_dropped++;
961 }
962 }
963
964 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
965
966 }
967
968 tp->cur_rx = cur_rx;
969 }
970
971 /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
972 static irqreturn_t
973 rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
974 {
975 struct net_device *dev = (struct net_device *) dev_instance;
976 struct rtl8169_private *tp = dev->priv;
977 int boguscnt = max_interrupt_work;
978 void *ioaddr = tp->mmio_addr;
979 int status = 0;
980 int handled = 0;
981
982 do {
983 status = RTL_R16(IntrStatus);
984
985 /* h/w no longer present (hotplug?) or major error, bail */
986 if (status == 0xFFFF)
987 break;
988
989 handled = 1;
990 /*
991 if (status & RxUnderrun)
992 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
993 */
994 RTL_W16(IntrStatus,
995 (status & RxFIFOOver) ? (status | RxOverflow) : status);
996
997 if ((status &
998 (SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver
999 | TxErr | TxOK | RxErr | RxOK)) == 0)
1000 break;
1001
1002 // Rx interrupt
1003 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) {
1004 rtl8169_rx_interrupt(dev, tp, ioaddr);
1005 }
1006 // Tx interrupt
1007 if (status & (TxOK | TxErr)) {
1008 spin_lock(&tp->lock);
1009 rtl8169_tx_interrupt(dev, tp, ioaddr);
1010 spin_unlock(&tp->lock);
1011 }
1012
1013 boguscnt--;
1014 } while (boguscnt > 0);
1015
1016 if (boguscnt <= 0) {
1017 printk(KERN_WARNING "%s: Too much work at interrupt!\n",
1018 dev->name);
1019 /* Clear all interrupt sources. */
1020 RTL_W16(IntrStatus, 0xffff);
1021 }
1022 return IRQ_RETVAL(handled);
1023 }
1024
1025 static int
1026 rtl8169_close(struct net_device *dev)
1027 {
1028 struct rtl8169_private *tp = dev->priv;
1029 void *ioaddr = tp->mmio_addr;
1030 int i;
1031
1032 netif_stop_queue(dev);
1033
1034 spin_lock_irq(&tp->lock);
1035
1036 /* Stop the chip's Tx and Rx DMA processes. */
1037 RTL_W8(ChipCmd, 0x00);
1038
1039 /* Disable interrupts by clearing the interrupt mask. */
1040 RTL_W16(IntrMask, 0x0000);
1041
1042 /* Update the error counts. */
1043 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1044 RTL_W32(RxMissed, 0);
1045
1046 spin_unlock_irq(&tp->lock);
1047
1048 synchronize_irq(dev->irq);
1049 free_irq(dev->irq, dev);
1050
1051 rtl8169_tx_clear(tp);
1052 kfree(tp->TxDescArrays);
1053 kfree(tp->RxDescArrays);
1054 tp->TxDescArrays = NULL;
1055 tp->RxDescArrays = NULL;
1056 tp->TxDescArray = NULL;
1057 tp->RxDescArray = NULL;
1058 kfree(tp->RxBufferRings);
1059 for (i = 0; i < NUM_RX_DESC; i++) {
1060 tp->RxBufferRing[i] = NULL;
1061 }
1062
1063 return 0;
1064 }
1065
1066 static void
1067 rtl8169_set_rx_mode(struct net_device *dev)
1068 {
1069 struct rtl8169_private *tp = dev->priv;
1070 void *ioaddr = tp->mmio_addr;
1071 unsigned long flags;
1072 u32 mc_filter[2]; /* Multicast hash filter */
1073 int i, rx_mode;
1074 u32 tmp = 0;
1075
1076 if (dev->flags & IFF_PROMISC) {
1077 /* Unconditionally log net taps. */
1078 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1079 dev->name);
1080 rx_mode =
1081 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1082 AcceptAllPhys;
1083 mc_filter[1] = mc_filter[0] = 0xffffffff;
1084 } else if ((dev->mc_count > multicast_filter_limit)
1085 || (dev->flags & IFF_ALLMULTI)) {
1086 /* Too many to filter perfectly -- accept all multicasts. */
1087 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1088 mc_filter[1] = mc_filter[0] = 0xffffffff;
1089 } else {
1090 struct dev_mc_list *mclist;
1091 rx_mode = AcceptBroadcast | AcceptMyPhys;
1092 mc_filter[1] = mc_filter[0] = 0;
1093 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1094 i++, mclist = mclist->next) {
1095 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1096 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1097 rx_mode |= AcceptMulticast;
1098 }
1099 }
1100
1101 spin_lock_irqsave(&tp->lock, flags);
1102
1103 tmp =
1104 rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
1105 rtl_chip_info[tp->chipset].
1106 RxConfigMask);
1107
1108 RTL_W32(RxConfig, tmp);
1109 RTL_W32(MAR0 + 0, mc_filter[0]);
1110 RTL_W32(MAR0 + 4, mc_filter[1]);
1111
1112 spin_unlock_irqrestore(&tp->lock, flags);
1113 }
1114
1115 struct net_device_stats *
1116 rtl8169_get_stats(struct net_device *dev)
1117 {
1118 struct rtl8169_private *tp = dev->priv;
1119
1120 return &tp->stats;
1121 }
1122
1123 static struct pci_driver rtl8169_pci_driver = {
1124 .name = MODULENAME,
1125 .id_table = rtl8169_pci_tbl,
1126 .probe = rtl8169_init_one,
1127 .remove = __devexit_p(rtl8169_remove_one),
1128 .suspend = NULL,
1129 .resume = NULL,
1130 };
1131
1132 static int __init
1133 rtl8169_init_module(void)
1134 {
1135 return pci_module_init(&rtl8169_pci_driver);
1136 }
1137
1138 static void __exit
1139 rtl8169_cleanup_module(void)
1140 {
1141 pci_unregister_driver(&rtl8169_pci_driver);
1142 }
1143
1144 module_init(rtl8169_init_module);
1145 module_exit(rtl8169_cleanup_module);
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