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[linux-2.6/linux-mips.git] / drivers / net / pcnet32.c
blobae9491176cfc3576b78c1dcfa735ab0ce9548480
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.27b"
26 #define DRV_RELDATE "01.10.2002"
27 #define PFX DRV_NAME ": "
28
29 static const char *version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49
50 #include <asm/bitops.h>
51 #include <asm/dma.h>
52 #include <asm/io.h>
53 #include <asm/uaccess.h>
54
55 /*
56 * PCI device identifiers for "new style" Linux PCI Device Drivers
57 */
58 static struct pci_device_id pcnet32_pci_tbl[] __devinitdata = {
59 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
60 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
61 { 0, }
62 };
63
64 MODULE_DEVICE_TABLE (pci, pcnet32_pci_tbl);
65
66 int cards_found __initdata;
67
68 /*
69 * VLB I/O addresses
70 */
71 static unsigned int pcnet32_portlist[] __initdata =
72 { 0x300, 0x320, 0x340, 0x360, 0 };
73
74
75
76 static int pcnet32_debug = 1;
77 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
78 static int pcnet32vlb; /* check for VLB cards ? */
79
80 static struct net_device *pcnet32_dev;
81
82 static int max_interrupt_work = 80;
83 static int rx_copybreak = 200;
84
85 #define PCNET32_PORT_AUI 0x00
86 #define PCNET32_PORT_10BT 0x01
87 #define PCNET32_PORT_GPSI 0x02
88 #define PCNET32_PORT_MII 0x03
89
90 #define PCNET32_PORT_PORTSEL 0x03
91 #define PCNET32_PORT_ASEL 0x04
92 #define PCNET32_PORT_100 0x40
93 #define PCNET32_PORT_FD 0x80
94
95 #define PCNET32_DMA_MASK 0xffffffff
96
97 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
98
99 /*
100 * table to translate option values from tulip
101 * to internal options
102 */
103 static unsigned char options_mapping[] = {
104 PCNET32_PORT_ASEL, /* 0 Auto-select */
105 PCNET32_PORT_AUI, /* 1 BNC/AUI */
106 PCNET32_PORT_AUI, /* 2 AUI/BNC */
107 PCNET32_PORT_ASEL, /* 3 not supported */
108 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
109 PCNET32_PORT_ASEL, /* 5 not supported */
110 PCNET32_PORT_ASEL, /* 6 not supported */
111 PCNET32_PORT_ASEL, /* 7 not supported */
112 PCNET32_PORT_ASEL, /* 8 not supported */
113 PCNET32_PORT_MII, /* 9 MII 10baseT */
114 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
115 PCNET32_PORT_MII, /* 11 MII (autosel) */
116 PCNET32_PORT_10BT, /* 12 10BaseT */
117 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
118 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
119 PCNET32_PORT_ASEL /* 15 not supported */
120 };
121
122 #define MAX_UNITS 8 /* More are supported, limit only on options */
123 static int options[MAX_UNITS];
124 static int full_duplex[MAX_UNITS];
125
126 /*
127 * Theory of Operation
128 *
129 * This driver uses the same software structure as the normal lance
130 * driver. So look for a verbose description in lance.c. The differences
131 * to the normal lance driver is the use of the 32bit mode of PCnet32
132 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
133 * 16MB limitation and we don't need bounce buffers.
134 */
135
136 /*
137 * History:
138 * v0.01: Initial version
139 * only tested on Alpha Noname Board
140 * v0.02: changed IRQ handling for new interrupt scheme (dev_id)
141 * tested on a ASUS SP3G
142 * v0.10: fixed an odd problem with the 79C974 in a Compaq Deskpro XL
143 * looks like the 974 doesn't like stopping and restarting in a
144 * short period of time; now we do a reinit of the lance; the
145 * bug was triggered by doing ifconfig eth0 <ip> broadcast <addr>
146 * and hangs the machine (thanks to Klaus Liedl for debugging)
147 * v0.12: by suggestion from Donald Becker: Renamed driver to pcnet32,
148 * made it standalone (no need for lance.c)
149 * v0.13: added additional PCI detecting for special PCI devices (Compaq)
150 * v0.14: stripped down additional PCI probe (thanks to David C Niemi
151 * and sveneric@xs4all.nl for testing this on their Compaq boxes)
152 * v0.15: added 79C965 (VLB) probe
153 * added interrupt sharing for PCI chips
154 * v0.16: fixed set_multicast_list on Alpha machines
155 * v0.17: removed hack from dev.c; now pcnet32 uses ethif_probe in Space.c
156 * v0.19: changed setting of autoselect bit
157 * v0.20: removed additional Compaq PCI probe; there is now a working one
158 * in arch/i386/bios32.c
159 * v0.21: added endian conversion for ppc, from work by cort@cs.nmt.edu
160 * v0.22: added printing of status to ring dump
161 * v0.23: changed enet_statistics to net_devive_stats
162 * v0.90: added multicast filter
163 * added module support
164 * changed irq probe to new style
165 * added PCnetFast chip id
166 * added fix for receive stalls with Intel saturn chipsets
167 * added in-place rx skbs like in the tulip driver
168 * minor cleanups
169 * v0.91: added PCnetFast+ chip id
170 * back port to 2.0.x
171 * v1.00: added some stuff from Donald Becker's 2.0.34 version
172 * added support for byte counters in net_dev_stats
173 * v1.01: do ring dumps, only when debugging the driver
174 * increased the transmit timeout
175 * v1.02: fixed memory leak in pcnet32_init_ring()
176 * v1.10: workaround for stopped transmitter
177 * added port selection for modules
178 * detect special T1/E1 WAN card and setup port selection
179 * v1.11: fixed wrong checking of Tx errors
180 * v1.20: added check of return value kmalloc (cpeterso@cs.washington.edu)
181 * added save original kmalloc addr for freeing (mcr@solidum.com)
182 * added support for PCnetHome chip (joe@MIT.EDU)
183 * rewritten PCI card detection
184 * added dwio mode to get driver working on some PPC machines
185 * v1.21: added mii selection and mii ioctl
186 * v1.22: changed pci scanning code to make PPC people happy
187 * fixed switching to 32bit mode in pcnet32_open() (thanks
188 * to Michael Richard <mcr@solidum.com> for noticing this one)
189 * added sub vendor/device id matching (thanks again to
190 * Michael Richard <mcr@solidum.com>)
191 * added chip id for 79c973/975 (thanks to Zach Brown <zab@zabbo.net>)
192 * v1.23 fixed small bug, when manual selecting MII speed/duplex
193 * v1.24 Applied Thomas' patch to use TxStartPoint and thus decrease TxFIFO
194 * underflows. Added tx_start_pt module parameter. Increased
195 * TX_RING_SIZE from 16 to 32. Added #ifdef'd code to use DXSUFLO
196 * for FAST[+] chipsets. <kaf@fc.hp.com>
197 * v1.24ac Added SMP spinlocking - Alan Cox <alan@redhat.com>
198 * v1.25kf Added No Interrupt on successful Tx for some Tx's <kaf@fc.hp.com>
199 * v1.26 Converted to pci_alloc_consistent, Jamey Hicks / George France
200 * <jamey@crl.dec.com>
201 * - Fixed a few bugs, related to running the controller in 32bit mode.
202 * 23 Oct, 2000. Carsten Langgaard, carstenl@mips.com
203 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
204 * v1.26p Fix oops on rmmod+insmod; plug i/o resource leak - Paul Gortmaker
205 * v1.27 improved CSR/PROM address detection, lots of cleanups,
206 * new pcnet32vlb module option, HP-PARISC support,
207 * added module parameter descriptions,
208 * initial ethtool support - Helge Deller <deller@gmx.de>
209 * v1.27a Sun Feb 10 2002 Go Taniguchi <go@turbolinux.co.jp>
210 * use alloc_etherdev and register_netdev
211 * fix pci probe not increment cards_found
212 * FD auto negotiate error workaround for xSeries250
213 * clean up and using new mii module
214 * v1.27b Sep 30 2002 Kent Yoder <yoder1@us.ibm.com>
215 * Added timer for cable connection state changes.
216 */
217
218
219 /*
220 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
221 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
222 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
223 */
224 #ifndef PCNET32_LOG_TX_BUFFERS
225 #define PCNET32_LOG_TX_BUFFERS 4
226 #define PCNET32_LOG_RX_BUFFERS 5
227 #endif
228
229 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
230 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
231 #define TX_RING_LEN_BITS ((PCNET32_LOG_TX_BUFFERS) << 12)
232
233 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
234 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
235 #define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
236
237 #define PKT_BUF_SZ 1544
238
239 /* Offsets from base I/O address. */
240 #define PCNET32_WIO_RDP 0x10
241 #define PCNET32_WIO_RAP 0x12
242 #define PCNET32_WIO_RESET 0x14
243 #define PCNET32_WIO_BDP 0x16
244
245 #define PCNET32_DWIO_RDP 0x10
246 #define PCNET32_DWIO_RAP 0x14
247 #define PCNET32_DWIO_RESET 0x18
248 #define PCNET32_DWIO_BDP 0x1C
249
250 #define PCNET32_TOTAL_SIZE 0x20
251
252 /* The PCNET32 Rx and Tx ring descriptors. */
253 struct pcnet32_rx_head {
254 u32 base;
255 s16 buf_length;
256 s16 status;
257 u32 msg_length;
258 u32 reserved;
259 };
260
261 struct pcnet32_tx_head {
262 u32 base;
263 s16 length;
264 s16 status;
265 u32 misc;
266 u32 reserved;
267 };
268
269 /* The PCNET32 32-Bit initialization block, described in databook. */
270 struct pcnet32_init_block {
271 u16 mode;
272 u16 tlen_rlen;
273 u8 phys_addr[6];
274 u16 reserved;
275 u32 filter[2];
276 /* Receive and transmit ring base, along with extra bits. */
277 u32 rx_ring;
278 u32 tx_ring;
279 };
280
281 /* PCnet32 access functions */
282 struct pcnet32_access {
283 u16 (*read_csr)(unsigned long, int);
284 void (*write_csr)(unsigned long, int, u16);
285 u16 (*read_bcr)(unsigned long, int);
286 void (*write_bcr)(unsigned long, int, u16);
287 u16 (*read_rap)(unsigned long);
288 void (*write_rap)(unsigned long, u16);
289 void (*reset)(unsigned long);
290 };
291
292 /*
293 * The first three fields of pcnet32_private are read by the ethernet device
294 * so we allocate the structure should be allocated by pci_alloc_consistent().
295 */
296 struct pcnet32_private {
297 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
298 struct pcnet32_rx_head rx_ring[RX_RING_SIZE];
299 struct pcnet32_tx_head tx_ring[TX_RING_SIZE];
300 struct pcnet32_init_block init_block;
301 dma_addr_t dma_addr; /* DMA address of beginning of this object,
302 returned by pci_alloc_consistent */
303 struct pci_dev *pci_dev; /* Pointer to the associated pci device structure */
304 const char *name;
305 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
306 struct sk_buff *tx_skbuff[TX_RING_SIZE];
307 struct sk_buff *rx_skbuff[RX_RING_SIZE];
308 dma_addr_t tx_dma_addr[TX_RING_SIZE];
309 dma_addr_t rx_dma_addr[RX_RING_SIZE];
310 struct pcnet32_access a;
311 spinlock_t lock; /* Guard lock */
312 unsigned int cur_rx, cur_tx; /* The next free ring entry */
313 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
314 struct net_device_stats stats;
315 char tx_full;
316 int options;
317 int shared_irq:1, /* shared irq possible */
318 ltint:1, /* enable TxDone-intr inhibitor */
319 dxsuflo:1, /* disable transmit stop on uflo */
320 mii:1; /* mii port available */
321 struct net_device *next;
322 struct mii_if_info mii_if;
323 struct timer_list watchdog_timer;
324 };
325
326 static void pcnet32_probe_vlbus(void);
327 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
328 static int pcnet32_probe1(unsigned long, unsigned int, int, struct pci_dev *);
329 static int pcnet32_open(struct net_device *);
330 static int pcnet32_init_ring(struct net_device *);
331 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
332 static int pcnet32_rx(struct net_device *);
333 static void pcnet32_tx_timeout (struct net_device *dev);
334 static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
335 static int pcnet32_close(struct net_device *);
336 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
337 static void pcnet32_set_multicast_list(struct net_device *);
338 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
339 static void pcnet32_watchdog(struct net_device *);
340 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
341 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val);
342
343 enum pci_flags_bit {
344 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
345 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
346 };
347
348
349 static u16 pcnet32_wio_read_csr (unsigned long addr, int index)
350 {
351 outw (index, addr+PCNET32_WIO_RAP);
352 return inw (addr+PCNET32_WIO_RDP);
353 }
354
355 static void pcnet32_wio_write_csr (unsigned long addr, int index, u16 val)
356 {
357 outw (index, addr+PCNET32_WIO_RAP);
358 outw (val, addr+PCNET32_WIO_RDP);
359 }
360
361 static u16 pcnet32_wio_read_bcr (unsigned long addr, int index)
362 {
363 outw (index, addr+PCNET32_WIO_RAP);
364 return inw (addr+PCNET32_WIO_BDP);
365 }
366
367 static void pcnet32_wio_write_bcr (unsigned long addr, int index, u16 val)
368 {
369 outw (index, addr+PCNET32_WIO_RAP);
370 outw (val, addr+PCNET32_WIO_BDP);
371 }
372
373 static u16 pcnet32_wio_read_rap (unsigned long addr)
374 {
375 return inw (addr+PCNET32_WIO_RAP);
376 }
377
378 static void pcnet32_wio_write_rap (unsigned long addr, u16 val)
379 {
380 outw (val, addr+PCNET32_WIO_RAP);
381 }
382
383 static void pcnet32_wio_reset (unsigned long addr)
384 {
385 inw (addr+PCNET32_WIO_RESET);
386 }
387
388 static int pcnet32_wio_check (unsigned long addr)
389 {
390 outw (88, addr+PCNET32_WIO_RAP);
391 return (inw (addr+PCNET32_WIO_RAP) == 88);
392 }
393
394 static struct pcnet32_access pcnet32_wio = {
395 .read_csr = pcnet32_wio_read_csr,
396 .write_csr = pcnet32_wio_write_csr,
397 .read_bcr = pcnet32_wio_read_bcr,
398 .write_bcr = pcnet32_wio_write_bcr,
399 .read_rap = pcnet32_wio_read_rap,
400 .write_rap = pcnet32_wio_write_rap,
401 .reset = pcnet32_wio_reset
402 };
403
404 static u16 pcnet32_dwio_read_csr (unsigned long addr, int index)
405 {
406 outl (index, addr+PCNET32_DWIO_RAP);
407 return (inl (addr+PCNET32_DWIO_RDP) & 0xffff);
408 }
409
410 static void pcnet32_dwio_write_csr (unsigned long addr, int index, u16 val)
411 {
412 outl (index, addr+PCNET32_DWIO_RAP);
413 outl (val, addr+PCNET32_DWIO_RDP);
414 }
415
416 static u16 pcnet32_dwio_read_bcr (unsigned long addr, int index)
417 {
418 outl (index, addr+PCNET32_DWIO_RAP);
419 return (inl (addr+PCNET32_DWIO_BDP) & 0xffff);
420 }
421
422 static void pcnet32_dwio_write_bcr (unsigned long addr, int index, u16 val)
423 {
424 outl (index, addr+PCNET32_DWIO_RAP);
425 outl (val, addr+PCNET32_DWIO_BDP);
426 }
427
428 static u16 pcnet32_dwio_read_rap (unsigned long addr)
429 {
430 return (inl (addr+PCNET32_DWIO_RAP) & 0xffff);
431 }
432
433 static void pcnet32_dwio_write_rap (unsigned long addr, u16 val)
434 {
435 outl (val, addr+PCNET32_DWIO_RAP);
436 }
437
438 static void pcnet32_dwio_reset (unsigned long addr)
439 {
440 inl (addr+PCNET32_DWIO_RESET);
441 }
442
443 static int pcnet32_dwio_check (unsigned long addr)
444 {
445 outl (88, addr+PCNET32_DWIO_RAP);
446 return ((inl (addr+PCNET32_DWIO_RAP) & 0xffff) == 88);
447 }
448
449 static struct pcnet32_access pcnet32_dwio = {
450 .read_csr = pcnet32_dwio_read_csr,
451 .write_csr = pcnet32_dwio_write_csr,
452 .read_bcr = pcnet32_dwio_read_bcr,
453 .write_bcr = pcnet32_dwio_write_bcr,
454 .read_rap = pcnet32_dwio_read_rap,
455 .write_rap = pcnet32_dwio_write_rap,
456 .reset = pcnet32_dwio_reset
457 };
458
459
460
461 /* only probes for non-PCI devices, the rest are handled by
462 * pci_register_driver via pcnet32_probe_pci */
463
464 static void __devinit
465 pcnet32_probe_vlbus(void)
466 {
467 unsigned int *port, ioaddr;
468
469 /* search for PCnet32 VLB cards at known addresses */
470 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
471 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
472 /* check if there is really a pcnet chip on that ioaddr */
473 if ((inb(ioaddr + 14) == 0x57) && (inb(ioaddr + 15) == 0x57)) {
474 pcnet32_probe1(ioaddr, 0, 0, NULL);
475 } else {
476 release_region(ioaddr, PCNET32_TOTAL_SIZE);
477 }
478 }
479 }
480 }
481
482
483 static int __devinit
484 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
485 {
486 unsigned long ioaddr;
487 int err;
488
489 err = pci_enable_device(pdev);
490 if (err < 0) {
491 printk(KERN_ERR PFX "failed to enable device -- err=%d\n", err);
492 return err;
493 }
494 pci_set_master(pdev);
495
496 ioaddr = pci_resource_start (pdev, 0);
497 if (!ioaddr) {
498 printk (KERN_ERR PFX "card has no PCI IO resources, aborting\n");
499 return -ENODEV;
500 }
501
502 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
503 printk(KERN_ERR PFX "architecture does not support 32bit PCI busmaster DMA\n");
504 return -ENODEV;
505 }
506 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") == NULL) {
507 printk(KERN_ERR PFX "io address range already allocated\n");
508 return -EBUSY;
509 }
510
511 return pcnet32_probe1(ioaddr, pdev->irq, 1, pdev);
512 }
513
514
515 /* pcnet32_probe1
516 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
517 * pdev will be NULL when called from pcnet32_probe_vlbus.
518 */
519 static int __devinit
520 pcnet32_probe1(unsigned long ioaddr, unsigned int irq_line, int shared,
521 struct pci_dev *pdev)
522 {
523 struct pcnet32_private *lp;
524 dma_addr_t lp_dma_addr;
525 int i, media;
526 int fdx, mii, fset, dxsuflo, ltint;
527 int chip_version;
528 char *chipname;
529 struct net_device *dev;
530 struct pcnet32_access *a = NULL;
531 u8 promaddr[6];
532
533 /* reset the chip */
534 pcnet32_wio_reset(ioaddr);
535
536 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
537 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
538 a = &pcnet32_wio;
539 } else {
540 pcnet32_dwio_reset(ioaddr);
541 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
542 a = &pcnet32_dwio;
543 } else {
544 release_region(ioaddr, PCNET32_TOTAL_SIZE);
545 return -ENODEV;
546 }
547 }
548
549 chip_version = a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr,89) << 16);
550 if (pcnet32_debug > 2)
551 printk(KERN_INFO " PCnet chip version is %#x.\n", chip_version);
552 if ((chip_version & 0xfff) != 0x003) {
553 release_region(ioaddr, PCNET32_TOTAL_SIZE);
554 return -ENODEV;
555 }
556
557 /* initialize variables */
558 fdx = mii = fset = dxsuflo = ltint = 0;
559 chip_version = (chip_version >> 12) & 0xffff;
560
561 switch (chip_version) {
562 case 0x2420:
563 chipname = "PCnet/PCI 79C970"; /* PCI */
564 break;
565 case 0x2430:
566 if (shared)
567 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
568 else
569 chipname = "PCnet/32 79C965"; /* 486/VL bus */
570 break;
571 case 0x2621:
572 chipname = "PCnet/PCI II 79C970A"; /* PCI */
573 fdx = 1;
574 break;
575 case 0x2623:
576 chipname = "PCnet/FAST 79C971"; /* PCI */
577 fdx = 1; mii = 1; fset = 1;
578 ltint = 1;
579 break;
580 case 0x2624:
581 chipname = "PCnet/FAST+ 79C972"; /* PCI */
582 fdx = 1; mii = 1; fset = 1;
583 break;
584 case 0x2625:
585 chipname = "PCnet/FAST III 79C973"; /* PCI */
586 fdx = 1; mii = 1;
587 break;
588 case 0x2626:
589 chipname = "PCnet/Home 79C978"; /* PCI */
590 fdx = 1;
591 /*
592 * This is based on specs published at www.amd.com. This section
593 * assumes that a card with a 79C978 wants to go into 1Mb HomePNA
594 * mode. The 79C978 can also go into standard ethernet, and there
595 * probably should be some sort of module option to select the
596 * mode by which the card should operate
597 */
598 /* switch to home wiring mode */
599 media = a->read_bcr(ioaddr, 49);
600 #if 0
601 if (pcnet32_debug > 2)
602 printk(KERN_DEBUG PFX "media value %#x.\n", media);
603 media &= ~3;
604 media |= 1;
605 #endif
606 if (pcnet32_debug > 2)
607 printk(KERN_DEBUG PFX "media reset to %#x.\n", media);
608 a->write_bcr(ioaddr, 49, media);
609 break;
610 case 0x2627:
611 chipname = "PCnet/FAST III 79C975"; /* PCI */
612 fdx = 1; mii = 1;
613 break;
614 default:
615 printk(KERN_INFO PFX "PCnet version %#x, no PCnet32 chip.\n",
616 chip_version);
617 release_region(ioaddr, PCNET32_TOTAL_SIZE);
618 return -ENODEV;
619 }
620
621 /*
622 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
623 * starting until the packet is loaded. Strike one for reliability, lose
624 * one for latency - although on PCI this isnt a big loss. Older chips
625 * have FIFO's smaller than a packet, so you can't do this.
626 */
627
628 if(fset)
629 {
630 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0800));
631 a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
632 dxsuflo = 1;
633 ltint = 1;
634 }
635
636 dev = alloc_etherdev(0);
637 if(!dev) {
638 release_region(ioaddr, PCNET32_TOTAL_SIZE);
639 return -ENOMEM;
640 }
641 SET_NETDEV_DEV(dev, &pdev->dev);
642
643 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
644
645 /* In most chips, after a chip reset, the ethernet address is read from the
646 * station address PROM at the base address and programmed into the
647 * "Physical Address Registers" CSR12-14.
648 * As a precautionary measure, we read the PROM values and complain if
649 * they disagree with the CSRs. Either way, we use the CSR values, and
650 * double check that they are valid.
651 */
652 for (i = 0; i < 3; i++) {
653 unsigned int val;
654 val = a->read_csr(ioaddr, i+12) & 0x0ffff;
655 /* There may be endianness issues here. */
656 dev->dev_addr[2*i] = val & 0x0ff;
657 dev->dev_addr[2*i+1] = (val >> 8) & 0x0ff;
658 }
659
660 /* read PROM address and compare with CSR address */
661 for (i = 0; i < 6; i++)
662 promaddr[i] = inb(ioaddr + i);
663
664 if( memcmp( promaddr, dev->dev_addr, 6)
665 || !is_valid_ether_addr(dev->dev_addr) ) {
666 #ifndef __powerpc__
667 if( is_valid_ether_addr(promaddr) ){
668 #else
669 if( !is_valid_ether_addr(dev->dev_addr)
670 && is_valid_ether_addr(promaddr)) {
671 #endif
672 printk(" warning: CSR address invalid,\n");
673 printk(KERN_INFO " using instead PROM address of");
674 memcpy(dev->dev_addr, promaddr, 6);
675 }
676 }
677
678 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
679 if( !is_valid_ether_addr(dev->dev_addr) )
680 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
681
682 for (i = 0; i < 6; i++)
683 printk(" %2.2x", dev->dev_addr[i] );
684
685 if (((chip_version + 1) & 0xfffe) == 0x2624) { /* Version 0x2623 or 0x2624 */
686 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
687 printk("\n" KERN_INFO " tx_start_pt(0x%04x):",i);
688 switch(i>>10) {
689 case 0: printk(" 20 bytes,"); break;
690 case 1: printk(" 64 bytes,"); break;
691 case 2: printk(" 128 bytes,"); break;
692 case 3: printk("~220 bytes,"); break;
693 }
694 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
695 printk(" BCR18(%x):",i&0xffff);
696 if (i & (1<<5)) printk("BurstWrEn ");
697 if (i & (1<<6)) printk("BurstRdEn ");
698 if (i & (1<<7)) printk("DWordIO ");
699 if (i & (1<<11)) printk("NoUFlow ");
700 i = a->read_bcr(ioaddr, 25);
701 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,",i<<8);
702 i = a->read_bcr(ioaddr, 26);
703 printk(" SRAM_BND=0x%04x,",i<<8);
704 i = a->read_bcr(ioaddr, 27);
705 if (i & (1<<14)) printk("LowLatRx");
706 }
707
708 dev->base_addr = ioaddr;
709 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
710 if ((lp = pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
711 release_region(ioaddr, PCNET32_TOTAL_SIZE);
712 return -ENOMEM;
713 }
714
715 memset(lp, 0, sizeof(*lp));
716 lp->dma_addr = lp_dma_addr;
717 lp->pci_dev = pdev;
718
719 spin_lock_init(&lp->lock);
720
721 SET_MODULE_OWNER(dev);
722 SET_NETDEV_DEV(dev, &pdev->dev);
723 dev->priv = lp;
724 lp->name = chipname;
725 lp->shared_irq = shared;
726 lp->mii_if.full_duplex = fdx;
727 lp->dxsuflo = dxsuflo;
728 lp->ltint = ltint;
729 lp->mii = mii;
730 if ((cards_found >= MAX_UNITS) || (options[cards_found] > sizeof(options_mapping)))
731 lp->options = PCNET32_PORT_ASEL;
732 else
733 lp->options = options_mapping[options[cards_found]];
734 lp->mii_if.dev = dev;
735 lp->mii_if.mdio_read = mdio_read;
736 lp->mii_if.mdio_write = mdio_write;
737
738 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
739 ((cards_found>=MAX_UNITS) || full_duplex[cards_found]))
740 lp->options |= PCNET32_PORT_FD;
741
742 if (!a) {
743 printk(KERN_ERR PFX "No access methods\n");
744 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
745 release_region(ioaddr, PCNET32_TOTAL_SIZE);
746 return -ENODEV;
747 }
748 lp->a = *a;
749
750 /* detect special T1/E1 WAN card by checking for MAC address */
751 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && dev->dev_addr[2] == 0x75)
752 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
753
754 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
755 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
756 for (i = 0; i < 6; i++)
757 lp->init_block.phys_addr[i] = dev->dev_addr[i];
758 lp->init_block.filter[0] = 0x00000000;
759 lp->init_block.filter[1] = 0x00000000;
760 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, rx_ring));
761 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, tx_ring));
762
763 /* switch pcnet32 to 32bit mode */
764 a->write_bcr (ioaddr, 20, 2);
765
766 a->write_csr (ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) & 0xffff);
767 a->write_csr (ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) >> 16);
768
769 if (irq_line) {
770 dev->irq = irq_line;
771 }
772
773 if (dev->irq >= 2)
774 printk(" assigned IRQ %d.\n", dev->irq);
775 else {
776 unsigned long irq_mask = probe_irq_on();
777
778 /*
779 * To auto-IRQ we enable the initialization-done and DMA error
780 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
781 * boards will work.
782 */
783 /* Trigger an initialization just for the interrupt. */
784 a->write_csr (ioaddr, 0, 0x41);
785 mdelay (1);
786
787 dev->irq = probe_irq_off (irq_mask);
788 if (dev->irq)
789 printk(", probed IRQ %d.\n", dev->irq);
790 else {
791 printk(", failed to detect IRQ line.\n");
792 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
793 release_region(ioaddr, PCNET32_TOTAL_SIZE);
794 return -ENODEV;
795 }
796 }
797
798 /* Set the mii phy_id so that we can query the link state */
799 if (lp->mii)
800 lp->mii_if.phy_id = ((lp->a.read_bcr (ioaddr, 33)) >> 5) & 0x1f;
801
802 init_timer (&lp->watchdog_timer);
803 lp->watchdog_timer.data = (unsigned long) dev;
804 lp->watchdog_timer.function = (void *) &pcnet32_watchdog;
805
806 /* The PCNET32-specific entries in the device structure. */
807 dev->open = &pcnet32_open;
808 dev->hard_start_xmit = &pcnet32_start_xmit;
809 dev->stop = &pcnet32_close;
810 dev->get_stats = &pcnet32_get_stats;
811 dev->set_multicast_list = &pcnet32_set_multicast_list;
812 dev->do_ioctl = &pcnet32_ioctl;
813 dev->tx_timeout = pcnet32_tx_timeout;
814 dev->watchdog_timeo = (5*HZ);
815
816 lp->next = pcnet32_dev;
817 pcnet32_dev = dev;
818
819 /* Fill in the generic fields of the device structure. */
820 register_netdev(dev);
821 printk(KERN_INFO "%s: registered as %s\n",dev->name, lp->name);
822 cards_found++;
823 return 0;
824 }
825
826
827 static int
828 pcnet32_open(struct net_device *dev)
829 {
830 struct pcnet32_private *lp = dev->priv;
831 unsigned long ioaddr = dev->base_addr;
832 u16 val;
833 int i;
834
835 if (dev->irq == 0 ||
836 request_irq(dev->irq, &pcnet32_interrupt,
837 lp->shared_irq ? SA_SHIRQ : 0, lp->name, (void *)dev)) {
838 return -EAGAIN;
839 }
840
841 /* Check for a valid station address */
842 if( !is_valid_ether_addr(dev->dev_addr) )
843 return -EINVAL;
844
845 /* Reset the PCNET32 */
846 lp->a.reset (ioaddr);
847
848 /* switch pcnet32 to 32bit mode */
849 lp->a.write_bcr (ioaddr, 20, 2);
850
851 if (pcnet32_debug > 1)
852 printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
853 dev->name, dev->irq,
854 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, tx_ring)),
855 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, rx_ring)),
856 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)));
857
858 /* set/reset autoselect bit */
859 val = lp->a.read_bcr (ioaddr, 2) & ~2;
860 if (lp->options & PCNET32_PORT_ASEL)
861 val |= 2;
862 lp->a.write_bcr (ioaddr, 2, val);
863
864 /* handle full duplex setting */
865 if (lp->mii_if.full_duplex) {
866 val = lp->a.read_bcr (ioaddr, 9) & ~3;
867 if (lp->options & PCNET32_PORT_FD) {
868 val |= 1;
869 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
870 val |= 2;
871 } else if (lp->options & PCNET32_PORT_ASEL) {
872 /* workaround of xSeries250, turn on for 79C975 only */
873 i = ((lp->a.read_csr(ioaddr, 88) | (lp->a.read_csr(ioaddr,89) << 16)) >> 12) & 0xffff;
874 if (i == 0x2627) val |= 3;
875 }
876 lp->a.write_bcr (ioaddr, 9, val);
877 }
878
879 /* set/reset GPSI bit in test register */
880 val = lp->a.read_csr (ioaddr, 124) & ~0x10;
881 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
882 val |= 0x10;
883 lp->a.write_csr (ioaddr, 124, val);
884
885 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
886 val = lp->a.read_bcr (ioaddr, 32) & ~0x38; /* disable Auto Negotiation, set 10Mpbs, HD */
887 if (lp->options & PCNET32_PORT_FD)
888 val |= 0x10;
889 if (lp->options & PCNET32_PORT_100)
890 val |= 0x08;
891 lp->a.write_bcr (ioaddr, 32, val);
892 } else {
893 if (lp->options & PCNET32_PORT_ASEL) { /* enable auto negotiate, setup, disable fd */
894 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
895 val |= 0x20;
896 lp->a.write_bcr(ioaddr, 32, val);
897 }
898 }
899
900 #ifdef DO_DXSUFLO
901 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
902 val = lp->a.read_csr (ioaddr, 3);
903 val |= 0x40;
904 lp->a.write_csr (ioaddr, 3, val);
905 }
906 #endif
907
908 if (lp->ltint) { /* Enable TxDone-intr inhibitor */
909 val = lp->a.read_csr (ioaddr, 5);
910 val |= (1<<14);
911 lp->a.write_csr (ioaddr, 5, val);
912 }
913
914 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
915 lp->init_block.filter[0] = 0x00000000;
916 lp->init_block.filter[1] = 0x00000000;
917 if (pcnet32_init_ring(dev))
918 return -ENOMEM;
919
920 /* Re-initialize the PCNET32, and start it when done. */
921 lp->a.write_csr (ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) &0xffff);
922 lp->a.write_csr (ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) >> 16);
923
924 lp->a.write_csr (ioaddr, 4, 0x0915);
925 lp->a.write_csr (ioaddr, 0, 0x0001);
926
927 netif_start_queue(dev);
928
929 /* If we have mii, print the link status and start the watchdog */
930 if (lp->mii) {
931 mii_check_media (&lp->mii_if, 1, 1);
932 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
933 }
934
935 i = 0;
936 while (i++ < 100)
937 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
938 break;
939 /*
940 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
941 * reports that doing so triggers a bug in the '974.
942 */
943 lp->a.write_csr (ioaddr, 0, 0x0042);
944
945 if (pcnet32_debug > 2)
946 printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
947 dev->name, i, (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)),
948 lp->a.read_csr(ioaddr, 0));
949
950
951 return 0; /* Always succeed */
952 }
953
954 /*
955 * The LANCE has been halted for one reason or another (busmaster memory
956 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
957 * etc.). Modern LANCE variants always reload their ring-buffer
958 * configuration when restarted, so we must reinitialize our ring
959 * context before restarting. As part of this reinitialization,
960 * find all packets still on the Tx ring and pretend that they had been
961 * sent (in effect, drop the packets on the floor) - the higher-level
962 * protocols will time out and retransmit. It'd be better to shuffle
963 * these skbs to a temp list and then actually re-Tx them after
964 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
965 */
966
967 static void
968 pcnet32_purge_tx_ring(struct net_device *dev)
969 {
970 struct pcnet32_private *lp = dev->priv;
971 int i;
972
973 for (i = 0; i < TX_RING_SIZE; i++) {
974 if (lp->tx_skbuff[i]) {
975 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
976 dev_kfree_skb_any(lp->tx_skbuff[i]);
977 lp->tx_skbuff[i] = NULL;
978 lp->tx_dma_addr[i] = 0;
979 }
980 }
981 }
982
983
984 /* Initialize the PCNET32 Rx and Tx rings. */
985 static int
986 pcnet32_init_ring(struct net_device *dev)
987 {
988 struct pcnet32_private *lp = dev->priv;
989 int i;
990
991 lp->tx_full = 0;
992 lp->cur_rx = lp->cur_tx = 0;
993 lp->dirty_rx = lp->dirty_tx = 0;
994
995 for (i = 0; i < RX_RING_SIZE; i++) {
996 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
997 if (rx_skbuff == NULL) {
998 if (!(rx_skbuff = lp->rx_skbuff[i] = dev_alloc_skb (PKT_BUF_SZ))) {
999 /* there is not much, we can do at this point */
1000 printk(KERN_ERR "%s: pcnet32_init_ring dev_alloc_skb failed.\n",dev->name);
1001 return -1;
1002 }
1003 skb_reserve (rx_skbuff, 2);
1004 }
1005
1006 if (lp->rx_dma_addr[i] == 0)
1007 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, rx_skbuff->tail, rx_skbuff->len, PCI_DMA_FROMDEVICE);
1008 lp->rx_ring[i].base = (u32)le32_to_cpu(lp->rx_dma_addr[i]);
1009 lp->rx_ring[i].buf_length = le16_to_cpu(-PKT_BUF_SZ);
1010 lp->rx_ring[i].status = le16_to_cpu(0x8000);
1011 }
1012 /* The Tx buffer address is filled in as needed, but we do need to clear
1013 the upper ownership bit. */
1014 for (i = 0; i < TX_RING_SIZE; i++) {
1015 lp->tx_ring[i].base = 0;
1016 lp->tx_ring[i].status = 0;
1017 lp->tx_dma_addr[i] = 0;
1018 }
1019
1020 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
1021 for (i = 0; i < 6; i++)
1022 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1023 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, rx_ring));
1024 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, tx_ring));
1025 return 0;
1026 }
1027
1028 static void
1029 pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1030 {
1031 struct pcnet32_private *lp = dev->priv;
1032 unsigned long ioaddr = dev->base_addr;
1033 int i;
1034
1035 pcnet32_purge_tx_ring(dev);
1036 if (pcnet32_init_ring(dev))
1037 return;
1038
1039 /* ReInit Ring */
1040 lp->a.write_csr (ioaddr, 0, 1);
1041 i = 0;
1042 while (i++ < 1000)
1043 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1044 break;
1045
1046 lp->a.write_csr (ioaddr, 0, csr0_bits);
1047 }
1048
1049
1050 static void
1051 pcnet32_tx_timeout (struct net_device *dev)
1052 {
1053 struct pcnet32_private *lp = dev->priv;
1054 unsigned long ioaddr = dev->base_addr, flags;
1055
1056 spin_lock_irqsave(&lp->lock, flags);
1057 /* Transmitter timeout, serious problems. */
1058 printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n",
1059 dev->name, lp->a.read_csr(ioaddr, 0));
1060 lp->a.write_csr (ioaddr, 0, 0x0004);
1061 lp->stats.tx_errors++;
1062 if (pcnet32_debug > 2) {
1063 int i;
1064 printk(KERN_DEBUG " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
1065 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
1066 lp->cur_rx);
1067 for (i = 0 ; i < RX_RING_SIZE; i++)
1068 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1069 lp->rx_ring[i].base, -lp->rx_ring[i].buf_length,
1070 lp->rx_ring[i].msg_length, (unsigned)lp->rx_ring[i].status);
1071 for (i = 0 ; i < TX_RING_SIZE; i++)
1072 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1073 lp->tx_ring[i].base, -lp->tx_ring[i].length,
1074 lp->tx_ring[i].misc, (unsigned)lp->tx_ring[i].status);
1075 printk("\n");
1076 }
1077 pcnet32_restart(dev, 0x0042);
1078
1079 dev->trans_start = jiffies;
1080 netif_start_queue(dev);
1081
1082 spin_unlock_irqrestore(&lp->lock, flags);
1083 }
1084
1085
1086 static int
1087 pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1088 {
1089 struct pcnet32_private *lp = dev->priv;
1090 unsigned long ioaddr = dev->base_addr;
1091 u16 status;
1092 int entry;
1093 unsigned long flags;
1094
1095 if (pcnet32_debug > 3) {
1096 printk(KERN_DEBUG "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
1097 dev->name, lp->a.read_csr(ioaddr, 0));
1098 }
1099
1100 spin_lock_irqsave(&lp->lock, flags);
1101
1102 /* Default status -- will not enable Successful-TxDone
1103 * interrupt when that option is available to us.
1104 */
1105 status = 0x8300;
1106 if ((lp->ltint) &&
1107 ((lp->cur_tx - lp->dirty_tx == TX_RING_SIZE/2) ||
1108 (lp->cur_tx - lp->dirty_tx >= TX_RING_SIZE-2)))
1109 {
1110 /* Enable Successful-TxDone interrupt if we have
1111 * 1/2 of, or nearly all of, our ring buffer Tx'd
1112 * but not yet cleaned up. Thus, most of the time,
1113 * we will not enable Successful-TxDone interrupts.
1114 */
1115 status = 0x9300;
1116 }
1117
1118 /* Fill in a Tx ring entry */
1119
1120 /* Mask to ring buffer boundary. */
1121 entry = lp->cur_tx & TX_RING_MOD_MASK;
1122
1123 /* Caution: the write order is important here, set the base address
1124 with the "ownership" bits last. */
1125
1126 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1127
1128 lp->tx_ring[entry].misc = 0x00000000;
1129
1130 lp->tx_skbuff[entry] = skb;
1131 lp->tx_dma_addr[entry] = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1132 lp->tx_ring[entry].base = (u32)le32_to_cpu(lp->tx_dma_addr[entry]);
1133 wmb(); /* Make sure owner changes after all others are visible */
1134 lp->tx_ring[entry].status = le16_to_cpu(status);
1135
1136 lp->cur_tx++;
1137 lp->stats.tx_bytes += skb->len;
1138
1139 /* Trigger an immediate send poll. */
1140 lp->a.write_csr (ioaddr, 0, 0x0048);
1141
1142 dev->trans_start = jiffies;
1143
1144 if (lp->tx_ring[(entry+1) & TX_RING_MOD_MASK].base == 0)
1145 netif_start_queue(dev);
1146 else {
1147 lp->tx_full = 1;
1148 netif_stop_queue(dev);
1149 }
1150 spin_unlock_irqrestore(&lp->lock, flags);
1151 return 0;
1152 }
1153
1154 /* The PCNET32 interrupt handler. */
1155 static irqreturn_t
1156 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1157 {
1158 struct net_device *dev = dev_id;
1159 struct pcnet32_private *lp;
1160 unsigned long ioaddr;
1161 u16 csr0,rap;
1162 int boguscnt = max_interrupt_work;
1163 int must_restart;
1164
1165 if (!dev) {
1166 printk (KERN_DEBUG "%s(): irq %d for unknown device\n",
1167 __FUNCTION__, irq);
1168 return IRQ_NONE;
1169 }
1170
1171 ioaddr = dev->base_addr;
1172 lp = dev->priv;
1173
1174 spin_lock(&lp->lock);
1175
1176 rap = lp->a.read_rap(ioaddr);
1177 while ((csr0 = lp->a.read_csr (ioaddr, 0)) & 0x8600 && --boguscnt >= 0) {
1178 /* Acknowledge all of the current interrupt sources ASAP. */
1179 lp->a.write_csr (ioaddr, 0, csr0 & ~0x004f);
1180
1181 must_restart = 0;
1182
1183 if (pcnet32_debug > 5)
1184 printk(KERN_DEBUG "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
1185 dev->name, csr0, lp->a.read_csr (ioaddr, 0));
1186
1187 if (csr0 & 0x0400) /* Rx interrupt */
1188 pcnet32_rx(dev);
1189
1190 if (csr0 & 0x0200) { /* Tx-done interrupt */
1191 unsigned int dirty_tx = lp->dirty_tx;
1192
1193 while (dirty_tx < lp->cur_tx) {
1194 int entry = dirty_tx & TX_RING_MOD_MASK;
1195 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1196
1197 if (status < 0)
1198 break; /* It still hasn't been Txed */
1199
1200 lp->tx_ring[entry].base = 0;
1201
1202 if (status & 0x4000) {
1203 /* There was an major error, log it. */
1204 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1205 lp->stats.tx_errors++;
1206 if (err_status & 0x04000000) lp->stats.tx_aborted_errors++;
1207 if (err_status & 0x08000000) lp->stats.tx_carrier_errors++;
1208 if (err_status & 0x10000000) lp->stats.tx_window_errors++;
1209 #ifndef DO_DXSUFLO
1210 if (err_status & 0x40000000) {
1211 lp->stats.tx_fifo_errors++;
1212 /* Ackk! On FIFO errors the Tx unit is turned off! */
1213 /* Remove this verbosity later! */
1214 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1215 dev->name, csr0);
1216 must_restart = 1;
1217 }
1218 #else
1219 if (err_status & 0x40000000) {
1220 lp->stats.tx_fifo_errors++;
1221 if (! lp->dxsuflo) { /* If controller doesn't recover ... */
1222 /* Ackk! On FIFO errors the Tx unit is turned off! */
1223 /* Remove this verbosity later! */
1224 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1225 dev->name, csr0);
1226 must_restart = 1;
1227 }
1228 }
1229 #endif
1230 } else {
1231 if (status & 0x1800)
1232 lp->stats.collisions++;
1233 lp->stats.tx_packets++;
1234 }
1235
1236 /* We must free the original skb */
1237 if (lp->tx_skbuff[entry]) {
1238 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[entry],
1239 lp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
1240 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
1241 lp->tx_skbuff[entry] = 0;
1242 lp->tx_dma_addr[entry] = 0;
1243 }
1244 dirty_tx++;
1245 }
1246
1247 if (lp->cur_tx - dirty_tx >= TX_RING_SIZE) {
1248 printk(KERN_ERR "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1249 dev->name, dirty_tx, lp->cur_tx, lp->tx_full);
1250 dirty_tx += TX_RING_SIZE;
1251 }
1252
1253 if (lp->tx_full &&
1254 netif_queue_stopped(dev) &&
1255 dirty_tx > lp->cur_tx - TX_RING_SIZE + 2) {
1256 /* The ring is no longer full, clear tbusy. */
1257 lp->tx_full = 0;
1258 netif_wake_queue (dev);
1259 }
1260 lp->dirty_tx = dirty_tx;
1261 }
1262
1263 /* Log misc errors. */
1264 if (csr0 & 0x4000) lp->stats.tx_errors++; /* Tx babble. */
1265 if (csr0 & 0x1000) {
1266 /*
1267 * this happens when our receive ring is full. This shouldn't
1268 * be a problem as we will see normal rx interrupts for the frames
1269 * in the receive ring. But there are some PCI chipsets (I can reproduce
1270 * this on SP3G with Intel saturn chipset) which have sometimes problems
1271 * and will fill up the receive ring with error descriptors. In this
1272 * situation we don't get a rx interrupt, but a missed frame interrupt sooner
1273 * or later. So we try to clean up our receive ring here.
1274 */
1275 pcnet32_rx(dev);
1276 lp->stats.rx_errors++; /* Missed a Rx frame. */
1277 }
1278 if (csr0 & 0x0800) {
1279 printk(KERN_ERR "%s: Bus master arbitration failure, status %4.4x.\n",
1280 dev->name, csr0);
1281 /* unlike for the lance, there is no restart needed */
1282 }
1283
1284 if (must_restart) {
1285 /* stop the chip to clear the error condition, then restart */
1286 lp->a.write_csr (ioaddr, 0, 0x0004);
1287 pcnet32_restart(dev, 0x0002);
1288 }
1289 }
1290
1291 /* Clear any other interrupt, and set interrupt enable. */
1292 lp->a.write_csr (ioaddr, 0, 0x7940);
1293 lp->a.write_rap (ioaddr,rap);
1294
1295 if (pcnet32_debug > 4)
1296 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
1297 dev->name, lp->a.read_csr (ioaddr, 0));
1298
1299 spin_unlock(&lp->lock);
1300
1301 return IRQ_HANDLED;
1302 }
1303
1304 static int
1305 pcnet32_rx(struct net_device *dev)
1306 {
1307 struct pcnet32_private *lp = dev->priv;
1308 int entry = lp->cur_rx & RX_RING_MOD_MASK;
1309
1310 /* If we own the next entry, it's a new packet. Send it up. */
1311 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
1312 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
1313
1314 if (status != 0x03) { /* There was an error. */
1315 /*
1316 * There is a tricky error noted by John Murphy,
1317 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1318 * buffers it's possible for a jabber packet to use two
1319 * buffers, with only the last correctly noting the error.
1320 */
1321 if (status & 0x01) /* Only count a general error at the */
1322 lp->stats.rx_errors++; /* end of a packet.*/
1323 if (status & 0x20) lp->stats.rx_frame_errors++;
1324 if (status & 0x10) lp->stats.rx_over_errors++;
1325 if (status & 0x08) lp->stats.rx_crc_errors++;
1326 if (status & 0x04) lp->stats.rx_fifo_errors++;
1327 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1328 } else {
1329 /* Malloc up new buffer, compatible with net-2e. */
1330 short pkt_len = (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)-4;
1331 struct sk_buff *skb;
1332
1333 if(pkt_len < 60) {
1334 printk(KERN_ERR "%s: Runt packet!\n",dev->name);
1335 lp->stats.rx_errors++;
1336 } else {
1337 int rx_in_place = 0;
1338
1339 if (pkt_len > rx_copybreak) {
1340 struct sk_buff *newskb;
1341
1342 if ((newskb = dev_alloc_skb (PKT_BUF_SZ))) {
1343 skb_reserve (newskb, 2);
1344 skb = lp->rx_skbuff[entry];
1345 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry], skb->len, PCI_DMA_FROMDEVICE);
1346 skb_put (skb, pkt_len);
1347 lp->rx_skbuff[entry] = newskb;
1348 newskb->dev = dev;
1349 lp->rx_dma_addr[entry] =
1350 pci_map_single(lp->pci_dev, newskb->tail,
1351 newskb->len, PCI_DMA_FROMDEVICE);
1352 lp->rx_ring[entry].base = le32_to_cpu(lp->rx_dma_addr[entry]);
1353 rx_in_place = 1;
1354 } else
1355 skb = NULL;
1356 } else {
1357 skb = dev_alloc_skb(pkt_len+2);
1358 }
1359
1360 if (skb == NULL) {
1361 int i;
1362 printk(KERN_ERR "%s: Memory squeeze, deferring packet.\n", dev->name);
1363 for (i = 0; i < RX_RING_SIZE; i++)
1364 if ((short)le16_to_cpu(lp->rx_ring[(entry+i) & RX_RING_MOD_MASK].status) < 0)
1365 break;
1366
1367 if (i > RX_RING_SIZE -2) {
1368 lp->stats.rx_dropped++;
1369 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1370 lp->cur_rx++;
1371 }
1372 break;
1373 }
1374 skb->dev = dev;
1375 if (!rx_in_place) {
1376 skb_reserve(skb,2); /* 16 byte align */
1377 skb_put(skb,pkt_len); /* Make room */
1378 eth_copy_and_sum(skb,
1379 (unsigned char *)(lp->rx_skbuff[entry]->tail),
1380 pkt_len,0);
1381 }
1382 lp->stats.rx_bytes += skb->len;
1383 skb->protocol=eth_type_trans(skb,dev);
1384 netif_rx(skb);
1385 dev->last_rx = jiffies;
1386 lp->stats.rx_packets++;
1387 }
1388 }
1389 /*
1390 * The docs say that the buffer length isn't touched, but Andrew Boyd
1391 * of QNX reports that some revs of the 79C965 clear it.
1392 */
1393 lp->rx_ring[entry].buf_length = le16_to_cpu(-PKT_BUF_SZ);
1394 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1395 entry = (++lp->cur_rx) & RX_RING_MOD_MASK;
1396 }
1397
1398 return 0;
1399 }
1400
1401 static int
1402 pcnet32_close(struct net_device *dev)
1403 {
1404 unsigned long ioaddr = dev->base_addr;
1405 struct pcnet32_private *lp = dev->priv;
1406 int i;
1407
1408 del_timer_sync(&lp->watchdog_timer);
1409
1410 netif_stop_queue(dev);
1411
1412 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
1413
1414 if (pcnet32_debug > 1)
1415 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1416 dev->name, lp->a.read_csr (ioaddr, 0));
1417
1418 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
1419 lp->a.write_csr (ioaddr, 0, 0x0004);
1420
1421 /*
1422 * Switch back to 16bit mode to avoid problems with dumb
1423 * DOS packet driver after a warm reboot
1424 */
1425 lp->a.write_bcr (ioaddr, 20, 4);
1426
1427 free_irq(dev->irq, dev);
1428
1429 /* free all allocated skbuffs */
1430 for (i = 0; i < RX_RING_SIZE; i++) {
1431 lp->rx_ring[i].status = 0;
1432 if (lp->rx_skbuff[i]) {
1433 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], lp->rx_skbuff[i]->len, PCI_DMA_FROMDEVICE);
1434 dev_kfree_skb(lp->rx_skbuff[i]);
1435 }
1436 lp->rx_skbuff[i] = NULL;
1437 lp->rx_dma_addr[i] = 0;
1438 }
1439
1440 for (i = 0; i < TX_RING_SIZE; i++) {
1441 if (lp->tx_skbuff[i]) {
1442 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
1443 dev_kfree_skb(lp->tx_skbuff[i]);
1444 }
1445 lp->tx_skbuff[i] = NULL;
1446 lp->tx_dma_addr[i] = 0;
1447 }
1448
1449 return 0;
1450 }
1451
1452 static struct net_device_stats *
1453 pcnet32_get_stats(struct net_device *dev)
1454 {
1455 struct pcnet32_private *lp = dev->priv;
1456 unsigned long ioaddr = dev->base_addr;
1457 u16 saved_addr;
1458 unsigned long flags;
1459
1460 spin_lock_irqsave(&lp->lock, flags);
1461 saved_addr = lp->a.read_rap(ioaddr);
1462 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
1463 lp->a.write_rap(ioaddr, saved_addr);
1464 spin_unlock_irqrestore(&lp->lock, flags);
1465
1466 return &lp->stats;
1467 }
1468
1469 /* taken from the sunlance driver, which it took from the depca driver */
1470 static void pcnet32_load_multicast (struct net_device *dev)
1471 {
1472 struct pcnet32_private *lp = dev->priv;
1473 volatile struct pcnet32_init_block *ib = &lp->init_block;
1474 volatile u16 *mcast_table = (u16 *)&ib->filter;
1475 struct dev_mc_list *dmi=dev->mc_list;
1476 char *addrs;
1477 int i;
1478 u32 crc;
1479
1480 /* set all multicast bits */
1481 if (dev->flags & IFF_ALLMULTI){
1482 ib->filter[0] = 0xffffffff;
1483 ib->filter[1] = 0xffffffff;
1484 return;
1485 }
1486 /* clear the multicast filter */
1487 ib->filter[0] = 0;
1488 ib->filter[1] = 0;
1489
1490 /* Add addresses */
1491 for (i = 0; i < dev->mc_count; i++){
1492 addrs = dmi->dmi_addr;
1493 dmi = dmi->next;
1494
1495 /* multicast address? */
1496 if (!(*addrs & 1))
1497 continue;
1498
1499 crc = ether_crc_le(6, addrs);
1500 crc = crc >> 26;
1501 mcast_table [crc >> 4] = le16_to_cpu(
1502 le16_to_cpu(mcast_table [crc >> 4]) | (1 << (crc & 0xf))
1503 );
1504 }
1505 return;
1506 }
1507
1508
1509 /*
1510 * Set or clear the multicast filter for this adaptor.
1511 */
1512 static void pcnet32_set_multicast_list(struct net_device *dev)
1513 {
1514 unsigned long ioaddr = dev->base_addr, flags;
1515 struct pcnet32_private *lp = dev->priv;
1516
1517 spin_lock_irqsave(&lp->lock, flags);
1518 if (dev->flags&IFF_PROMISC) {
1519 /* Log any net taps. */
1520 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1521 lp->init_block.mode = le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 7);
1522 } else {
1523 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1524 pcnet32_load_multicast (dev);
1525 }
1526
1527 lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
1528
1529 pcnet32_restart(dev, 0x0042); /* Resume normal operation */
1530 spin_unlock_irqrestore(&lp->lock, flags);
1531 }
1532
1533 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
1534 {
1535 struct pcnet32_private *lp = dev->priv;
1536 unsigned long ioaddr = dev->base_addr;
1537 u16 val_out;
1538 int phyaddr;
1539
1540 if (!lp->mii)
1541 return 0;
1542
1543 phyaddr = lp->a.read_bcr(ioaddr, 33);
1544
1545 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
1546 val_out = lp->a.read_bcr(ioaddr, 34);
1547 lp->a.write_bcr(ioaddr, 33, phyaddr);
1548
1549 return val_out;
1550 }
1551
1552 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
1553 {
1554 struct pcnet32_private *lp = dev->priv;
1555 unsigned long ioaddr = dev->base_addr;
1556 int phyaddr;
1557
1558 if (!lp->mii)
1559 return;
1560
1561 phyaddr = lp->a.read_bcr(ioaddr, 33);
1562
1563 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
1564 lp->a.write_bcr(ioaddr, 34, val);
1565 lp->a.write_bcr(ioaddr, 33, phyaddr);
1566 }
1567
1568 static int pcnet32_ethtool_ioctl (struct net_device *dev, void *useraddr)
1569 {
1570 struct pcnet32_private *lp = dev->priv;
1571 u32 ethcmd;
1572 int phyaddr = 0;
1573 int phy_id = 0;
1574 unsigned long ioaddr = dev->base_addr;
1575
1576 if (lp->mii) {
1577 phyaddr = lp->a.read_bcr (ioaddr, 33);
1578 phy_id = (phyaddr >> 5) & 0x1f;
1579 lp->mii_if.phy_id = phy_id;
1580 }
1581
1582 if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
1583 return -EFAULT;
1584
1585 switch (ethcmd) {
1586 case ETHTOOL_GDRVINFO: {
1587 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1588 strcpy (info.driver, DRV_NAME);
1589 strcpy (info.version, DRV_VERSION);
1590 if (lp->pci_dev)
1591 strcpy (info.bus_info, lp->pci_dev->slot_name);
1592 else
1593 sprintf(info.bus_info, "VLB 0x%lx", dev->base_addr);
1594 if (copy_to_user (useraddr, &info, sizeof (info)))
1595 return -EFAULT;
1596 return 0;
1597 }
1598
1599 /* get settings */
1600 case ETHTOOL_GSET: {
1601 struct ethtool_cmd ecmd = { ETHTOOL_GSET };
1602 spin_lock_irq(&lp->lock);
1603 mii_ethtool_gset(&lp->mii_if, &ecmd);
1604 spin_unlock_irq(&lp->lock);
1605 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
1606 return -EFAULT;
1607 return 0;
1608 }
1609 /* set settings */
1610 case ETHTOOL_SSET: {
1611 int r;
1612 struct ethtool_cmd ecmd;
1613 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
1614 return -EFAULT;
1615 spin_lock_irq(&lp->lock);
1616 r = mii_ethtool_sset(&lp->mii_if, &ecmd);
1617 spin_unlock_irq(&lp->lock);
1618 return r;
1619 }
1620 /* restart autonegotiation */
1621 case ETHTOOL_NWAY_RST: {
1622 return mii_nway_restart(&lp->mii_if);
1623 }
1624 /* get link status */
1625 case ETHTOOL_GLINK: {
1626 struct ethtool_value edata = {ETHTOOL_GLINK};
1627 edata.data = mii_link_ok(&lp->mii_if);
1628 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1629 return -EFAULT;
1630 return 0;
1631 }
1632
1633 /* get message-level */
1634 case ETHTOOL_GMSGLVL: {
1635 struct ethtool_value edata = {ETHTOOL_GMSGLVL};
1636 edata.data = pcnet32_debug;
1637 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1638 return -EFAULT;
1639 return 0;
1640 }
1641 /* set message-level */
1642 case ETHTOOL_SMSGLVL: {
1643 struct ethtool_value edata;
1644 if (copy_from_user(&edata, useraddr, sizeof(edata)))
1645 return -EFAULT;
1646 pcnet32_debug = edata.data;
1647 return 0;
1648 }
1649 default:
1650 break;
1651 }
1652
1653 return -EOPNOTSUPP;
1654 }
1655
1656 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1657 {
1658 unsigned long ioaddr = dev->base_addr;
1659 struct pcnet32_private *lp = dev->priv;
1660 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
1661 int phyaddr = lp->a.read_bcr (ioaddr, 33);
1662
1663 if (cmd == SIOCETHTOOL)
1664 return pcnet32_ethtool_ioctl(dev, (void *) rq->ifr_data);
1665
1666 if (lp->mii) {
1667 switch(cmd) {
1668 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1669 data->phy_id = (phyaddr >> 5) & 0x1f;
1670 /* Fall Through */
1671 case SIOCGMIIREG: /* Read MII PHY register. */
1672 lp->a.write_bcr (ioaddr, 33, ((data->phy_id & 0x1f) << 5) | (data->reg_num & 0x1f));
1673 data->val_out = lp->a.read_bcr (ioaddr, 34);
1674 lp->a.write_bcr (ioaddr, 33, phyaddr);
1675 return 0;
1676 case SIOCSMIIREG: /* Write MII PHY register. */
1677 if (!capable(CAP_NET_ADMIN))
1678 return -EPERM;
1679 lp->a.write_bcr (ioaddr, 33, ((data->phy_id & 0x1f) << 5) | (data->reg_num & 0x1f));
1680 lp->a.write_bcr (ioaddr, 34, data->val_in);
1681 lp->a.write_bcr (ioaddr, 33, phyaddr);
1682 return 0;
1683 default:
1684 return -EOPNOTSUPP;
1685 }
1686 }
1687 return -EOPNOTSUPP;
1688 }
1689
1690 static void pcnet32_watchdog(struct net_device *dev)
1691 {
1692 struct pcnet32_private *lp = dev->priv;
1693
1694 /* Print the link status if it has changed */
1695 if (lp->mii)
1696 mii_check_media (&lp->mii_if, 1, 0);
1697
1698 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1699 }
1700
1701 static struct pci_driver pcnet32_driver = {
1702 .name = DRV_NAME,
1703 .probe = pcnet32_probe_pci,
1704 .id_table = pcnet32_pci_tbl,
1705 };
1706
1707 MODULE_PARM(debug, "i");
1708 MODULE_PARM_DESC(debug, DRV_NAME " debug level (0-6)");
1709 MODULE_PARM(max_interrupt_work, "i");
1710 MODULE_PARM_DESC(max_interrupt_work, DRV_NAME " maximum events handled per interrupt");
1711 MODULE_PARM(rx_copybreak, "i");
1712 MODULE_PARM_DESC(rx_copybreak, DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1713 MODULE_PARM(tx_start_pt, "i");
1714 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
1715 MODULE_PARM(pcnet32vlb, "i");
1716 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
1717 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
1718 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
1719 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
1720 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
1721
1722 MODULE_AUTHOR("Thomas Bogendoerfer");
1723 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
1724 MODULE_LICENSE("GPL");
1725
1726 /* An additional parameter that may be passed in... */
1727 static int debug = -1;
1728 static int tx_start_pt = -1;
1729
1730 static int __init pcnet32_init_module(void)
1731 {
1732 printk(KERN_INFO "%s", version);
1733
1734 if (debug > 0)
1735 pcnet32_debug = debug;
1736
1737 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
1738 tx_start = tx_start_pt;
1739
1740 /* find the PCI devices */
1741 pci_module_init(&pcnet32_driver);
1742
1743 /* should we find any remaining VLbus devices ? */
1744 if (pcnet32vlb)
1745 pcnet32_probe_vlbus();
1746
1747 if (cards_found)
1748 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1749
1750 return cards_found ? 0 : -ENODEV;
1751 }
1752
1753 static void __exit pcnet32_cleanup_module(void)
1754 {
1755 struct net_device *next_dev;
1756
1757 while (pcnet32_dev) {
1758 struct pcnet32_private *lp = pcnet32_dev->priv;
1759 next_dev = lp->next;
1760 unregister_netdev(pcnet32_dev);
1761 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
1762 if (lp->pci_dev)
1763 pci_unregister_driver(&pcnet32_driver);
1764 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1765 kfree(pcnet32_dev);
1766 pcnet32_dev = next_dev;
1767 }
1768 }
1769
1770 module_init(pcnet32_init_module);
1771 module_exit(pcnet32_cleanup_module);
1772
1773 /*
1774 * Local variables:
1775 * compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c pcnet32.c"
1776 * c-indent-level: 4
1777 * tab-width: 8
1778 * End:
1779 */
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