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[linux-2.6/linux-mips.git] / drivers / net / pci-skeleton.c
blob8d6170175ed148a62d1ca9560c29dbc8feeeca17
1 /*
2
3 drivers/net/pci-skeleton.c
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
11
12 -----<snip>-----
13
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41
42 -----------------------------------------------------------------------------
43
44 Theory of Operation
45
46 I. Board Compatibility
47
48 This device driver is designed for the RealTek RTL8139 series, the RealTek
49 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50 low-end boards, sometimes with its markings changed.
51
52
53 II. Board-specific settings
54
55 PCI bus devices are configured by the system at boot time, so no jumpers
56 need to be set on the board. The system BIOS will assign the
57 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
58
59 III. Driver operation
60
61 IIIa. Rx Ring buffers
62
63 The receive unit uses a single linear ring buffer rather than the more
64 common (and more efficient) descriptor-based architecture. Incoming frames
65 are sequentially stored into the Rx region, and the host copies them into
66 skbuffs.
67
68 Comment: While it is theoretically possible to process many frames in place,
69 any delay in Rx processing would cause us to drop frames. More importantly,
70 the Linux protocol stack is not designed to operate in this manner.
71
72 IIIb. Tx operation
73
74 The RTL8139 uses a fixed set of four Tx descriptors in register space.
75 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76 aligns the IP header on word boundaries, and 14 byte ethernet header means
77 that almost all frames will need to be copied to an alignment buffer.
78
79 IVb. References
80
81 http://www.realtek.com.tw/cn/cn.html
82 http://www.scyld.com/expert/NWay.html
83
84 IVc. Errata
85
86 */
87
88 #include <linux/config.h>
89 #include <linux/module.h>
90 #include <linux/kernel.h>
91 #include <linux/pci.h>
92 #include <linux/init.h>
93 #include <linux/ioport.h>
94 #include <linux/netdevice.h>
95 #include <linux/etherdevice.h>
96 #include <linux/delay.h>
97 #include <linux/ethtool.h>
98 #include <linux/mii.h>
99 #include <linux/crc32.h>
100 #include <asm/io.h>
101
102 #define NETDRV_VERSION "1.0.0"
103 #define MODNAME "netdrv"
104 #define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
105 #define PFX MODNAME ": "
106
107 static char version[] __devinitdata =
108 KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
109 KERN_INFO " Support available from http://foo.com/bar/baz.html\n";
110
111 /* define to 1 to enable PIO instead of MMIO */
112 #undef USE_IO_OPS
113
114 /* define to 1 to enable copious debugging info */
115 #undef NETDRV_DEBUG
116
117 /* define to 1 to disable lightweight runtime debugging checks */
118 #undef NETDRV_NDEBUG
119
120
121 #ifdef NETDRV_DEBUG
122 /* note: prints function name for you */
123 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
124 #else
125 # define DPRINTK(fmt, args...)
126 #endif
127
128 #ifdef NETDRV_NDEBUG
129 # define assert(expr) do {} while (0)
130 #else
131 # define assert(expr) \
132 if(!(expr)) { \
133 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
134 #expr,__FILE__,__FUNCTION__,__LINE__); \
135 }
136 #endif
137
138
139 /* A few user-configurable values. */
140 /* media options */
141 static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
142
143 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
144 static int max_interrupt_work = 20;
145
146 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
147 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
148 static int multicast_filter_limit = 32;
149
150 /* Size of the in-memory receive ring. */
151 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
152 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
153 #define RX_BUF_PAD 16
154 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
155 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
156
157 /* Number of Tx descriptor registers. */
158 #define NUM_TX_DESC 4
159
160 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
161 #define MAX_ETH_FRAME_SIZE 1536
162
163 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
164 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
165 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
166
167 /* PCI Tuning Parameters
168 Threshold is bytes transferred to chip before transmission starts. */
169 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
170
171 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
172 #define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
173 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
174 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
175
176
177 /* Operational parameters that usually are not changed. */
178 /* Time in jiffies before concluding the transmitter is hung. */
179 #define TX_TIMEOUT (6*HZ)
180
181
182 enum {
183 HAS_CHIP_XCVR = 0x020000,
184 HAS_LNK_CHNG = 0x040000,
185 };
186
187 #define NETDRV_MIN_IO_SIZE 0x80
188 #define RTL8139B_IO_SIZE 256
189
190 #define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
191
192 typedef enum {
193 RTL8139 = 0,
194 NETDRV_CB,
195 SMC1211TX,
196 /*MPX5030,*/
197 DELTA8139,
198 ADDTRON8139,
199 } board_t;
200
201
202 /* indexed by board_t, above */
203 static struct {
204 const char *name;
205 } board_info[] __devinitdata = {
206 { "RealTek RTL8139 Fast Ethernet" },
207 { "RealTek RTL8139B PCI/CardBus" },
208 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
209 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
210 { "Delta Electronics 8139 10/100BaseTX" },
211 { "Addtron Technolgy 8139 10/100BaseTX" },
212 };
213
214
215 static struct pci_device_id netdrv_pci_tbl[] __devinitdata = {
216 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
217 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
218 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
219 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
220 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
221 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
222 {0,}
223 };
224 MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
225
226
227 /* The rest of these values should never change. */
228
229 /* Symbolic offsets to registers. */
230 enum NETDRV_registers {
231 MAC0 = 0, /* Ethernet hardware address. */
232 MAR0 = 8, /* Multicast filter. */
233 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
234 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
235 RxBuf = 0x30,
236 RxEarlyCnt = 0x34,
237 RxEarlyStatus = 0x36,
238 ChipCmd = 0x37,
239 RxBufPtr = 0x38,
240 RxBufAddr = 0x3A,
241 IntrMask = 0x3C,
242 IntrStatus = 0x3E,
243 TxConfig = 0x40,
244 ChipVersion = 0x43,
245 RxConfig = 0x44,
246 Timer = 0x48, /* A general-purpose counter. */
247 RxMissed = 0x4C, /* 24 bits valid, write clears. */
248 Cfg9346 = 0x50,
249 Config0 = 0x51,
250 Config1 = 0x52,
251 FlashReg = 0x54,
252 MediaStatus = 0x58,
253 Config3 = 0x59,
254 Config4 = 0x5A, /* absent on RTL-8139A */
255 HltClk = 0x5B,
256 MultiIntr = 0x5C,
257 TxSummary = 0x60,
258 BasicModeCtrl = 0x62,
259 BasicModeStatus = 0x64,
260 NWayAdvert = 0x66,
261 NWayLPAR = 0x68,
262 NWayExpansion = 0x6A,
263 /* Undocumented registers, but required for proper operation. */
264 FIFOTMS = 0x70, /* FIFO Control and test. */
265 CSCR = 0x74, /* Chip Status and Configuration Register. */
266 PARA78 = 0x78,
267 PARA7c = 0x7c, /* Magic transceiver parameter register. */
268 Config5 = 0xD8, /* absent on RTL-8139A */
269 };
270
271 enum ClearBitMasks {
272 MultiIntrClear = 0xF000,
273 ChipCmdClear = 0xE2,
274 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
275 };
276
277 enum ChipCmdBits {
278 CmdReset = 0x10,
279 CmdRxEnb = 0x08,
280 CmdTxEnb = 0x04,
281 RxBufEmpty = 0x01,
282 };
283
284 /* Interrupt register bits, using my own meaningful names. */
285 enum IntrStatusBits {
286 PCIErr = 0x8000,
287 PCSTimeout = 0x4000,
288 RxFIFOOver = 0x40,
289 RxUnderrun = 0x20,
290 RxOverflow = 0x10,
291 TxErr = 0x08,
292 TxOK = 0x04,
293 RxErr = 0x02,
294 RxOK = 0x01,
295 };
296 enum TxStatusBits {
297 TxHostOwns = 0x2000,
298 TxUnderrun = 0x4000,
299 TxStatOK = 0x8000,
300 TxOutOfWindow = 0x20000000,
301 TxAborted = 0x40000000,
302 TxCarrierLost = 0x80000000,
303 };
304 enum RxStatusBits {
305 RxMulticast = 0x8000,
306 RxPhysical = 0x4000,
307 RxBroadcast = 0x2000,
308 RxBadSymbol = 0x0020,
309 RxRunt = 0x0010,
310 RxTooLong = 0x0008,
311 RxCRCErr = 0x0004,
312 RxBadAlign = 0x0002,
313 RxStatusOK = 0x0001,
314 };
315
316 /* Bits in RxConfig. */
317 enum rx_mode_bits {
318 AcceptErr = 0x20,
319 AcceptRunt = 0x10,
320 AcceptBroadcast = 0x08,
321 AcceptMulticast = 0x04,
322 AcceptMyPhys = 0x02,
323 AcceptAllPhys = 0x01,
324 };
325
326 /* Bits in TxConfig. */
327 enum tx_config_bits {
328 TxIFG1 = (1 << 25), /* Interframe Gap Time */
329 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
330 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
331 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
332 TxClearAbt = (1 << 0), /* Clear abort (WO) */
333 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
334
335 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
336 };
337
338 /* Bits in Config1 */
339 enum Config1Bits {
340 Cfg1_PM_Enable = 0x01,
341 Cfg1_VPD_Enable = 0x02,
342 Cfg1_PIO = 0x04,
343 Cfg1_MMIO = 0x08,
344 Cfg1_LWAKE = 0x10,
345 Cfg1_Driver_Load = 0x20,
346 Cfg1_LED0 = 0x40,
347 Cfg1_LED1 = 0x80,
348 };
349
350 enum RxConfigBits {
351 /* Early Rx threshold, none or X/16 */
352 RxCfgEarlyRxNone = 0,
353 RxCfgEarlyRxShift = 24,
354
355 /* rx fifo threshold */
356 RxCfgFIFOShift = 13,
357 RxCfgFIFONone = (7 << RxCfgFIFOShift),
358
359 /* Max DMA burst */
360 RxCfgDMAShift = 8,
361 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
362
363 /* rx ring buffer length */
364 RxCfgRcv8K = 0,
365 RxCfgRcv16K = (1 << 11),
366 RxCfgRcv32K = (1 << 12),
367 RxCfgRcv64K = (1 << 11) | (1 << 12),
368
369 /* Disable packet wrap at end of Rx buffer */
370 RxNoWrap = (1 << 7),
371 };
372
373
374 /* Twister tuning parameters from RealTek.
375 Completely undocumented, but required to tune bad links. */
376 enum CSCRBits {
377 CSCR_LinkOKBit = 0x0400,
378 CSCR_LinkChangeBit = 0x0800,
379 CSCR_LinkStatusBits = 0x0f000,
380 CSCR_LinkDownOffCmd = 0x003c0,
381 CSCR_LinkDownCmd = 0x0f3c0,
382 };
383
384
385 enum Cfg9346Bits {
386 Cfg9346_Lock = 0x00,
387 Cfg9346_Unlock = 0xC0,
388 };
389
390
391 #define PARA78_default 0x78fa8388
392 #define PARA7c_default 0xcb38de43 /* param[0][3] */
393 #define PARA7c_xxx 0xcb38de43
394 static const unsigned long param[4][4] = {
395 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
396 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
397 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
398 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
399 };
400
401 struct ring_info {
402 struct sk_buff *skb;
403 dma_addr_t mapping;
404 };
405
406
407 typedef enum {
408 CH_8139 = 0,
409 CH_8139_K,
410 CH_8139A,
411 CH_8139B,
412 CH_8130,
413 CH_8139C,
414 } chip_t;
415
416
417 /* directly indexed by chip_t, above */
418 const static struct {
419 const char *name;
420 u8 version; /* from RTL8139C docs */
421 u32 RxConfigMask; /* should clear the bits supported by this chip */
422 } rtl_chip_info[] = {
423 { "RTL-8139",
424 0x40,
425 0xf0fe0040, /* XXX copied from RTL8139A, verify */
426 },
427
428 { "RTL-8139 rev K",
429 0x60,
430 0xf0fe0040,
431 },
432
433 { "RTL-8139A",
434 0x70,
435 0xf0fe0040,
436 },
437
438 { "RTL-8139B",
439 0x78,
440 0xf0fc0040
441 },
442
443 { "RTL-8130",
444 0x7C,
445 0xf0fe0040, /* XXX copied from RTL8139A, verify */
446 },
447
448 { "RTL-8139C",
449 0x74,
450 0xf0fc0040, /* XXX copied from RTL8139B, verify */
451 },
452
453 };
454
455
456 struct netdrv_private {
457 board_t board;
458 void *mmio_addr;
459 int drv_flags;
460 struct pci_dev *pci_dev;
461 struct net_device_stats stats;
462 struct timer_list timer; /* Media selection timer. */
463 unsigned char *rx_ring;
464 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
465 unsigned int tx_flag;
466 atomic_t cur_tx;
467 atomic_t dirty_tx;
468 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
469 struct ring_info tx_info[NUM_TX_DESC];
470 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
471 unsigned char *tx_bufs; /* Tx bounce buffer region. */
472 dma_addr_t rx_ring_dma;
473 dma_addr_t tx_bufs_dma;
474 char phys[4]; /* MII device addresses. */
475 char twistie, twist_row, twist_col; /* Twister tune state. */
476 unsigned int full_duplex:1; /* Full-duplex operation requested. */
477 unsigned int duplex_lock:1;
478 unsigned int default_port:4; /* Last dev->if_port value. */
479 unsigned int media2:4; /* Secondary monitored media port. */
480 unsigned int medialock:1; /* Don't sense media type. */
481 unsigned int mediasense:1; /* Media sensing in progress. */
482 spinlock_t lock;
483 chip_t chipset;
484 };
485
486 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
487 MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
488 MODULE_LICENSE("GPL");
489 MODULE_PARM (multicast_filter_limit, "i");
490 MODULE_PARM (max_interrupt_work, "i");
491 MODULE_PARM (debug, "i");
492 MODULE_PARM (media, "1-" __MODULE_STRING(8) "i");
493 MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
494 MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
495 MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
496 MODULE_PARM_DESC (debug, "(unused)");
497
498 static int read_eeprom (void *ioaddr, int location, int addr_len);
499 static int netdrv_open (struct net_device *dev);
500 static int mdio_read (struct net_device *dev, int phy_id, int location);
501 static void mdio_write (struct net_device *dev, int phy_id, int location,
502 int val);
503 static void netdrv_timer (unsigned long data);
504 static void netdrv_tx_timeout (struct net_device *dev);
505 static void netdrv_init_ring (struct net_device *dev);
506 static int netdrv_start_xmit (struct sk_buff *skb,
507 struct net_device *dev);
508 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance,
509 struct pt_regs *regs);
510 static int netdrv_close (struct net_device *dev);
511 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
512 static struct net_device_stats *netdrv_get_stats (struct net_device *dev);
513 static void netdrv_set_rx_mode (struct net_device *dev);
514 static void netdrv_hw_start (struct net_device *dev);
515
516
517 #ifdef USE_IO_OPS
518
519 #define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
520 #define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
521 #define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
522 #define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
523 #define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
524 #define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
525 #define NETDRV_W8_F NETDRV_W8
526 #define NETDRV_W16_F NETDRV_W16
527 #define NETDRV_W32_F NETDRV_W32
528 #undef readb
529 #undef readw
530 #undef readl
531 #undef writeb
532 #undef writew
533 #undef writel
534 #define readb(addr) inb((unsigned long)(addr))
535 #define readw(addr) inw((unsigned long)(addr))
536 #define readl(addr) inl((unsigned long)(addr))
537 #define writeb(val,addr) outb((val),(unsigned long)(addr))
538 #define writew(val,addr) outw((val),(unsigned long)(addr))
539 #define writel(val,addr) outl((val),(unsigned long)(addr))
540
541 #else
542
543 /* write MMIO register, with flush */
544 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
545 #define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
546 #define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
547 #define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
548
549
550 #if MMIO_FLUSH_AUDIT_COMPLETE
551
552 /* write MMIO register */
553 #define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
554 #define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
555 #define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
556
557 #else
558
559 /* write MMIO register, then flush */
560 #define NETDRV_W8 NETDRV_W8_F
561 #define NETDRV_W16 NETDRV_W16_F
562 #define NETDRV_W32 NETDRV_W32_F
563
564 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
565
566 /* read MMIO register */
567 #define NETDRV_R8(reg) readb (ioaddr + (reg))
568 #define NETDRV_R16(reg) readw (ioaddr + (reg))
569 #define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
570
571 #endif /* USE_IO_OPS */
572
573
574 static const u16 netdrv_intr_mask =
575 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
576 TxErr | TxOK | RxErr | RxOK;
577
578 static const unsigned int netdrv_rx_config =
579 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
580 (RX_FIFO_THRESH << RxCfgFIFOShift) |
581 (RX_DMA_BURST << RxCfgDMAShift);
582
583
584 static int __devinit netdrv_init_board (struct pci_dev *pdev,
585 struct net_device **dev_out,
586 void **ioaddr_out)
587 {
588 void *ioaddr = NULL;
589 struct net_device *dev;
590 struct netdrv_private *tp;
591 u8 tmp8;
592 int rc, i;
593 u32 pio_start, pio_end, pio_flags, pio_len;
594 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
595 u32 tmp;
596
597 DPRINTK ("ENTER\n");
598
599 assert (pdev != NULL);
600 assert (ioaddr_out != NULL);
601
602 *ioaddr_out = NULL;
603 *dev_out = NULL;
604
605 /* dev zeroed in alloc_etherdev */
606 dev = alloc_etherdev (sizeof (*tp));
607 if (dev == NULL) {
608 printk (KERN_ERR PFX "unable to alloc new ethernet\n");
609 DPRINTK ("EXIT, returning -ENOMEM\n");
610 return -ENOMEM;
611 }
612 SET_MODULE_OWNER(dev);
613 SET_NETDEV_DEV(dev, &pdev->dev);
614 tp = dev->priv;
615
616 /* enable device (incl. PCI PM wakeup), and bus-mastering */
617 rc = pci_enable_device (pdev);
618 if (rc)
619 goto err_out;
620
621 pio_start = pci_resource_start (pdev, 0);
622 pio_end = pci_resource_end (pdev, 0);
623 pio_flags = pci_resource_flags (pdev, 0);
624 pio_len = pci_resource_len (pdev, 0);
625
626 mmio_start = pci_resource_start (pdev, 1);
627 mmio_end = pci_resource_end (pdev, 1);
628 mmio_flags = pci_resource_flags (pdev, 1);
629 mmio_len = pci_resource_len (pdev, 1);
630
631 /* set this immediately, we need to know before
632 * we talk to the chip directly */
633 DPRINTK("PIO region size == 0x%02X\n", pio_len);
634 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
635
636 /* make sure PCI base addr 0 is PIO */
637 if (!(pio_flags & IORESOURCE_IO)) {
638 printk (KERN_ERR PFX "region #0 not a PIO resource, aborting\n");
639 rc = -ENODEV;
640 goto err_out;
641 }
642
643 /* make sure PCI base addr 1 is MMIO */
644 if (!(mmio_flags & IORESOURCE_MEM)) {
645 printk (KERN_ERR PFX "region #1 not an MMIO resource, aborting\n");
646 rc = -ENODEV;
647 goto err_out;
648 }
649
650 /* check for weird/broken PCI region reporting */
651 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
652 (mmio_len < NETDRV_MIN_IO_SIZE)) {
653 printk (KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
654 rc = -ENODEV;
655 goto err_out;
656 }
657
658 rc = pci_request_regions (pdev, "pci-skeleton");
659 if (rc)
660 goto err_out;
661
662 pci_set_master (pdev);
663
664 #ifdef USE_IO_OPS
665 ioaddr = (void *) pio_start;
666 #else
667 /* ioremap MMIO region */
668 ioaddr = ioremap (mmio_start, mmio_len);
669 if (ioaddr == NULL) {
670 printk (KERN_ERR PFX "cannot remap MMIO, aborting\n");
671 rc = -EIO;
672 goto err_out_free_res;
673 }
674 #endif /* USE_IO_OPS */
675
676 /* Soft reset the chip. */
677 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
678
679 /* Check that the chip has finished the reset. */
680 for (i = 1000; i > 0; i--)
681 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
682 break;
683 else
684 udelay (10);
685
686 /* Bring the chip out of low-power mode. */
687 /* <insert device-specific code here> */
688
689 #ifndef USE_IO_OPS
690 /* sanity checks -- ensure PIO and MMIO registers agree */
691 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
692 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
693 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
694 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
695 #endif /* !USE_IO_OPS */
696
697 /* identify chip attached to board */
698 tmp = NETDRV_R8 (ChipVersion);
699 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
700 if (tmp == rtl_chip_info[i].version) {
701 tp->chipset = i;
702 goto match;
703 }
704
705 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
706 printk (KERN_DEBUG PFX "PCI device %s: unknown chip version, assuming RTL-8139\n",
707 pdev->slot_name);
708 printk (KERN_DEBUG PFX "PCI device %s: TxConfig = 0x%lx\n", pdev->slot_name, NETDRV_R32 (TxConfig));
709 tp->chipset = 0;
710
711 match:
712 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
713 tmp,
714 tp->chipset,
715 rtl_chip_info[tp->chipset].name);
716
717 i = register_netdev (dev);
718 if (i)
719 goto err_out_unmap;
720
721 DPRINTK ("EXIT, returning 0\n");
722 *ioaddr_out = ioaddr;
723 *dev_out = dev;
724 return 0;
725
726 err_out_unmap:
727 #ifndef USE_IO_OPS
728 iounmap(ioaddr);
729 err_out_free_res:
730 #endif
731 pci_release_regions (pdev);
732 err_out:
733 kfree (dev);
734 DPRINTK ("EXIT, returning %d\n", rc);
735 return rc;
736 }
737
738
739 static int __devinit netdrv_init_one (struct pci_dev *pdev,
740 const struct pci_device_id *ent)
741 {
742 struct net_device *dev = NULL;
743 struct netdrv_private *tp;
744 int i, addr_len, option;
745 void *ioaddr = NULL;
746 static int board_idx = -1;
747 u8 tmp;
748
749 /* when built into the kernel, we only print version if device is found */
750 #ifndef MODULE
751 static int printed_version;
752 if (!printed_version++)
753 printk(version);
754 #endif
755
756 DPRINTK ("ENTER\n");
757
758 assert (pdev != NULL);
759 assert (ent != NULL);
760
761 board_idx++;
762
763 i = netdrv_init_board (pdev, &dev, &ioaddr);
764 if (i < 0) {
765 DPRINTK ("EXIT, returning %d\n", i);
766 return i;
767 }
768
769 tp = dev->priv;
770
771 assert (ioaddr != NULL);
772 assert (dev != NULL);
773 assert (tp != NULL);
774
775 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
776 for (i = 0; i < 3; i++)
777 ((u16 *) (dev->dev_addr))[i] =
778 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
779
780 /* The Rtl8139-specific entries in the device structure. */
781 dev->open = netdrv_open;
782 dev->hard_start_xmit = netdrv_start_xmit;
783 dev->stop = netdrv_close;
784 dev->get_stats = netdrv_get_stats;
785 dev->set_multicast_list = netdrv_set_rx_mode;
786 dev->do_ioctl = netdrv_ioctl;
787 dev->tx_timeout = netdrv_tx_timeout;
788 dev->watchdog_timeo = TX_TIMEOUT;
789
790 dev->irq = pdev->irq;
791 dev->base_addr = (unsigned long) ioaddr;
792
793 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
794 tp = dev->priv;
795
796 /* note: tp->chipset set in netdrv_init_board */
797 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
798 PCI_COMMAND_MASTER | NETDRV_CAPS;
799 tp->pci_dev = pdev;
800 tp->board = ent->driver_data;
801 tp->mmio_addr = ioaddr;
802 tp->lock = SPIN_LOCK_UNLOCKED;
803
804 pci_set_drvdata(pdev, dev);
805
806 tp->phys[0] = 32;
807
808 printk (KERN_INFO "%s: %s at 0x%lx, "
809 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
810 "IRQ %d\n",
811 dev->name,
812 board_info[ent->driver_data].name,
813 dev->base_addr,
814 dev->dev_addr[0], dev->dev_addr[1],
815 dev->dev_addr[2], dev->dev_addr[3],
816 dev->dev_addr[4], dev->dev_addr[5],
817 dev->irq);
818
819 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
820 dev->name, rtl_chip_info[tp->chipset].name);
821
822 /* Put the chip into low-power mode. */
823 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
824
825 /* The lower four bits are the media type. */
826 option = (board_idx > 7) ? 0 : media[board_idx];
827 if (option > 0) {
828 tp->full_duplex = (option & 0x200) ? 1 : 0;
829 tp->default_port = option & 15;
830 if (tp->default_port)
831 tp->medialock = 1;
832 }
833
834 if (tp->full_duplex) {
835 printk (KERN_INFO
836 "%s: Media type forced to Full Duplex.\n",
837 dev->name);
838 mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
839 tp->duplex_lock = 1;
840 }
841
842 DPRINTK ("EXIT - returning 0\n");
843 return 0;
844 }
845
846
847 static void __devexit netdrv_remove_one (struct pci_dev *pdev)
848 {
849 struct net_device *dev = pci_get_drvdata (pdev);
850 struct netdrv_private *np;
851
852 DPRINTK ("ENTER\n");
853
854 assert (dev != NULL);
855
856 np = dev->priv;
857 assert (np != NULL);
858
859 unregister_netdev (dev);
860
861 #ifndef USE_IO_OPS
862 iounmap (np->mmio_addr);
863 #endif /* !USE_IO_OPS */
864
865 pci_release_regions (pdev);
866
867 #ifndef NETDRV_NDEBUG
868 /* poison memory before freeing */
869 memset (dev, 0xBC,
870 sizeof (struct net_device) +
871 sizeof (struct netdrv_private));
872 #endif /* NETDRV_NDEBUG */
873
874 kfree (dev);
875
876 pci_set_drvdata (pdev, NULL);
877
878 pci_power_off (pdev, -1);
879
880 DPRINTK ("EXIT\n");
881 }
882
883
884 /* Serial EEPROM section. */
885
886 /* EEPROM_Ctrl bits. */
887 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
888 #define EE_CS 0x08 /* EEPROM chip select. */
889 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
890 #define EE_WRITE_0 0x00
891 #define EE_WRITE_1 0x02
892 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
893 #define EE_ENB (0x80 | EE_CS)
894
895 /* Delay between EEPROM clock transitions.
896 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
897 */
898
899 #define eeprom_delay() readl(ee_addr)
900
901 /* The EEPROM commands include the alway-set leading bit. */
902 #define EE_WRITE_CMD (5)
903 #define EE_READ_CMD (6)
904 #define EE_ERASE_CMD (7)
905
906 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
907 {
908 int i;
909 unsigned retval = 0;
910 void *ee_addr = ioaddr + Cfg9346;
911 int read_cmd = location | (EE_READ_CMD << addr_len);
912
913 DPRINTK ("ENTER\n");
914
915 writeb (EE_ENB & ~EE_CS, ee_addr);
916 writeb (EE_ENB, ee_addr);
917 eeprom_delay ();
918
919 /* Shift the read command bits out. */
920 for (i = 4 + addr_len; i >= 0; i--) {
921 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
922 writeb (EE_ENB | dataval, ee_addr);
923 eeprom_delay ();
924 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
925 eeprom_delay ();
926 }
927 writeb (EE_ENB, ee_addr);
928 eeprom_delay ();
929
930 for (i = 16; i > 0; i--) {
931 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
932 eeprom_delay ();
933 retval =
934 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
935 0);
936 writeb (EE_ENB, ee_addr);
937 eeprom_delay ();
938 }
939
940 /* Terminate the EEPROM access. */
941 writeb (~EE_CS, ee_addr);
942 eeprom_delay ();
943
944 DPRINTK ("EXIT - returning %d\n", retval);
945 return retval;
946 }
947
948 /* MII serial management: mostly bogus for now. */
949 /* Read and write the MII management registers using software-generated
950 serial MDIO protocol.
951 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
952 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
953 "overclocking" issues. */
954 #define MDIO_DIR 0x80
955 #define MDIO_DATA_OUT 0x04
956 #define MDIO_DATA_IN 0x02
957 #define MDIO_CLK 0x01
958 #define MDIO_WRITE0 (MDIO_DIR)
959 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
960
961 #define mdio_delay() readb(mdio_addr)
962
963
964 static char mii_2_8139_map[8] = {
965 BasicModeCtrl,
966 BasicModeStatus,
967 0,
968 0,
969 NWayAdvert,
970 NWayLPAR,
971 NWayExpansion,
972 0
973 };
974
975
976 /* Syncronize the MII management interface by shifting 32 one bits out. */
977 static void mdio_sync (void *mdio_addr)
978 {
979 int i;
980
981 DPRINTK ("ENTER\n");
982
983 for (i = 32; i >= 0; i--) {
984 writeb (MDIO_WRITE1, mdio_addr);
985 mdio_delay ();
986 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
987 mdio_delay ();
988 }
989
990 DPRINTK ("EXIT\n");
991 }
992
993
994 static int mdio_read (struct net_device *dev, int phy_id, int location)
995 {
996 struct netdrv_private *tp = dev->priv;
997 void *mdio_addr = tp->mmio_addr + Config4;
998 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
999 int retval = 0;
1000 int i;
1001
1002 DPRINTK ("ENTER\n");
1003
1004 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1005 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1006 return location < 8 && mii_2_8139_map[location] ?
1007 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1008 }
1009 mdio_sync (mdio_addr);
1010 /* Shift the read command bits out. */
1011 for (i = 15; i >= 0; i--) {
1012 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1013
1014 writeb (MDIO_DIR | dataval, mdio_addr);
1015 mdio_delay ();
1016 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1017 mdio_delay ();
1018 }
1019
1020 /* Read the two transition, 16 data, and wire-idle bits. */
1021 for (i = 19; i > 0; i--) {
1022 writeb (0, mdio_addr);
1023 mdio_delay ();
1024 retval =
1025 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1026 : 0);
1027 writeb (MDIO_CLK, mdio_addr);
1028 mdio_delay ();
1029 }
1030
1031 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1032 return (retval >> 1) & 0xffff;
1033 }
1034
1035
1036 static void mdio_write (struct net_device *dev, int phy_id, int location,
1037 int value)
1038 {
1039 struct netdrv_private *tp = dev->priv;
1040 void *mdio_addr = tp->mmio_addr + Config4;
1041 int mii_cmd =
1042 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1043 int i;
1044
1045 DPRINTK ("ENTER\n");
1046
1047 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1048 if (location < 8 && mii_2_8139_map[location]) {
1049 writew (value,
1050 tp->mmio_addr + mii_2_8139_map[location]);
1051 readw (tp->mmio_addr + mii_2_8139_map[location]);
1052 }
1053 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1054 return;
1055 }
1056 mdio_sync (mdio_addr);
1057
1058 /* Shift the command bits out. */
1059 for (i = 31; i >= 0; i--) {
1060 int dataval =
1061 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1062 writeb (dataval, mdio_addr);
1063 mdio_delay ();
1064 writeb (dataval | MDIO_CLK, mdio_addr);
1065 mdio_delay ();
1066 }
1067
1068 /* Clear out extra bits. */
1069 for (i = 2; i > 0; i--) {
1070 writeb (0, mdio_addr);
1071 mdio_delay ();
1072 writeb (MDIO_CLK, mdio_addr);
1073 mdio_delay ();
1074 }
1075
1076 DPRINTK ("EXIT\n");
1077 }
1078
1079
1080 static int netdrv_open (struct net_device *dev)
1081 {
1082 struct netdrv_private *tp = dev->priv;
1083 int retval;
1084 #ifdef NETDRV_DEBUG
1085 void *ioaddr = tp->mmio_addr;
1086 #endif
1087
1088 DPRINTK ("ENTER\n");
1089
1090 retval = request_irq (dev->irq, netdrv_interrupt, SA_SHIRQ, dev->name, dev);
1091 if (retval) {
1092 DPRINTK ("EXIT, returning %d\n", retval);
1093 return retval;
1094 }
1095
1096 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1097 &tp->tx_bufs_dma);
1098 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1099 &tp->rx_ring_dma);
1100 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1101 free_irq(dev->irq, dev);
1102
1103 if (tp->tx_bufs)
1104 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1105 tp->tx_bufs, tp->tx_bufs_dma);
1106 if (tp->rx_ring)
1107 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1108 tp->rx_ring, tp->rx_ring_dma);
1109
1110 DPRINTK ("EXIT, returning -ENOMEM\n");
1111 return -ENOMEM;
1112
1113 }
1114
1115 tp->full_duplex = tp->duplex_lock;
1116 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1117
1118 netdrv_init_ring (dev);
1119 netdrv_hw_start (dev);
1120
1121 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1122 " GP Pins %2.2x %s-duplex.\n",
1123 dev->name, pci_resource_start (tp->pci_dev, 1),
1124 dev->irq, NETDRV_R8 (MediaStatus),
1125 tp->full_duplex ? "full" : "half");
1126
1127 /* Set the timer to switch to check for link beat and perhaps switch
1128 to an alternate media type. */
1129 init_timer (&tp->timer);
1130 tp->timer.expires = jiffies + 3 * HZ;
1131 tp->timer.data = (unsigned long) dev;
1132 tp->timer.function = &netdrv_timer;
1133 add_timer (&tp->timer);
1134
1135 DPRINTK ("EXIT, returning 0\n");
1136 return 0;
1137 }
1138
1139
1140 /* Start the hardware at open or resume. */
1141 static void netdrv_hw_start (struct net_device *dev)
1142 {
1143 struct netdrv_private *tp = dev->priv;
1144 void *ioaddr = tp->mmio_addr;
1145 u32 i;
1146 u8 tmp;
1147
1148 DPRINTK ("ENTER\n");
1149
1150 /* Soft reset the chip. */
1151 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1152 udelay (100);
1153
1154 /* Check that the chip has finished the reset. */
1155 for (i = 1000; i > 0; i--)
1156 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1157 break;
1158
1159 /* Restore our idea of the MAC address. */
1160 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1161 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1162
1163 /* Must enable Tx/Rx before setting transfer thresholds! */
1164 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1165 CmdRxEnb | CmdTxEnb);
1166
1167 i = netdrv_rx_config |
1168 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1169 NETDRV_W32_F (RxConfig, i);
1170
1171 /* Check this value: the documentation for IFG contradicts ifself. */
1172 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1173
1174 /* unlock Config[01234] and BMCR register writes */
1175 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1176 udelay (10);
1177
1178 tp->cur_rx = 0;
1179
1180 /* Lock Config[01234] and BMCR register writes */
1181 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1182 udelay (10);
1183
1184 /* init Rx ring buffer DMA address */
1185 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1186
1187 /* init Tx buffer DMA addresses */
1188 for (i = 0; i < NUM_TX_DESC; i++)
1189 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1190
1191 NETDRV_W32_F (RxMissed, 0);
1192
1193 netdrv_set_rx_mode (dev);
1194
1195 /* no early-rx interrupts */
1196 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1197
1198 /* make sure RxTx has started */
1199 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1200 CmdRxEnb | CmdTxEnb);
1201
1202 /* Enable all known interrupts by setting the interrupt mask. */
1203 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1204
1205 netif_start_queue (dev);
1206
1207 DPRINTK ("EXIT\n");
1208 }
1209
1210
1211 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1212 static void netdrv_init_ring (struct net_device *dev)
1213 {
1214 struct netdrv_private *tp = dev->priv;
1215 int i;
1216
1217 DPRINTK ("ENTER\n");
1218
1219 tp->cur_rx = 0;
1220 atomic_set (&tp->cur_tx, 0);
1221 atomic_set (&tp->dirty_tx, 0);
1222
1223 for (i = 0; i < NUM_TX_DESC; i++) {
1224 tp->tx_info[i].skb = NULL;
1225 tp->tx_info[i].mapping = 0;
1226 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1227 }
1228
1229 DPRINTK ("EXIT\n");
1230 }
1231
1232
1233 static void netdrv_timer (unsigned long data)
1234 {
1235 struct net_device *dev = (struct net_device *) data;
1236 struct netdrv_private *tp = dev->priv;
1237 void *ioaddr = tp->mmio_addr;
1238 int next_tick = 60 * HZ;
1239 int mii_lpa;
1240
1241 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1242
1243 if (!tp->duplex_lock && mii_lpa != 0xffff) {
1244 int duplex = (mii_lpa & LPA_100FULL)
1245 || (mii_lpa & 0x01C0) == 0x0040;
1246 if (tp->full_duplex != duplex) {
1247 tp->full_duplex = duplex;
1248 printk (KERN_INFO
1249 "%s: Setting %s-duplex based on MII #%d link"
1250 " partner ability of %4.4x.\n", dev->name,
1251 tp->full_duplex ? "full" : "half",
1252 tp->phys[0], mii_lpa);
1253 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1254 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1255 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1256 }
1257 }
1258
1259 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1260 dev->name, NETDRV_R16 (NWayLPAR));
1261 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1262 " RxStatus %4.4x.\n", dev->name,
1263 NETDRV_R16 (IntrMask),
1264 NETDRV_R16 (IntrStatus),
1265 NETDRV_R32 (RxEarlyStatus));
1266 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1267 dev->name, NETDRV_R8 (Config0),
1268 NETDRV_R8 (Config1));
1269
1270 tp->timer.expires = jiffies + next_tick;
1271 add_timer (&tp->timer);
1272 }
1273
1274
1275 static void netdrv_tx_clear (struct netdrv_private *tp)
1276 {
1277 int i;
1278
1279 atomic_set (&tp->cur_tx, 0);
1280 atomic_set (&tp->dirty_tx, 0);
1281
1282 /* Dump the unsent Tx packets. */
1283 for (i = 0; i < NUM_TX_DESC; i++) {
1284 struct ring_info *rp = &tp->tx_info[i];
1285 if (rp->mapping != 0) {
1286 pci_unmap_single (tp->pci_dev, rp->mapping,
1287 rp->skb->len, PCI_DMA_TODEVICE);
1288 rp->mapping = 0;
1289 }
1290 if (rp->skb) {
1291 dev_kfree_skb (rp->skb);
1292 rp->skb = NULL;
1293 tp->stats.tx_dropped++;
1294 }
1295 }
1296 }
1297
1298
1299 static void netdrv_tx_timeout (struct net_device *dev)
1300 {
1301 struct netdrv_private *tp = dev->priv;
1302 void *ioaddr = tp->mmio_addr;
1303 int i;
1304 u8 tmp8;
1305 unsigned long flags;
1306
1307 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1308 "media %2.2x.\n", dev->name,
1309 NETDRV_R8 (ChipCmd),
1310 NETDRV_R16 (IntrStatus),
1311 NETDRV_R8 (MediaStatus));
1312
1313 /* disable Tx ASAP, if not already */
1314 tmp8 = NETDRV_R8 (ChipCmd);
1315 if (tmp8 & CmdTxEnb)
1316 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1317
1318 /* Disable interrupts by clearing the interrupt mask. */
1319 NETDRV_W16 (IntrMask, 0x0000);
1320
1321 /* Emit info to figure out what went wrong. */
1322 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1323 dev->name, atomic_read (&tp->cur_tx),
1324 atomic_read (&tp->dirty_tx));
1325 for (i = 0; i < NUM_TX_DESC; i++)
1326 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1327 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1328 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1329 " (queue head)" : "");
1330
1331 /* Stop a shared interrupt from scavenging while we are. */
1332 spin_lock_irqsave (&tp->lock, flags);
1333
1334 netdrv_tx_clear (tp);
1335
1336 spin_unlock_irqrestore (&tp->lock, flags);
1337
1338 /* ...and finally, reset everything */
1339 netdrv_hw_start (dev);
1340
1341 netif_wake_queue (dev);
1342 }
1343
1344
1345
1346 static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1347 {
1348 struct netdrv_private *tp = dev->priv;
1349 void *ioaddr = tp->mmio_addr;
1350 int entry;
1351
1352 /* Calculate the next Tx descriptor entry. */
1353 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1354
1355 assert (tp->tx_info[entry].skb == NULL);
1356 assert (tp->tx_info[entry].mapping == 0);
1357
1358 tp->tx_info[entry].skb = skb;
1359 /* tp->tx_info[entry].mapping = 0; */
1360 memcpy (tp->tx_buf[entry], skb->data, skb->len);
1361
1362 /* Note: the chip doesn't have auto-pad! */
1363 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1364 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1365
1366 dev->trans_start = jiffies;
1367 atomic_inc (&tp->cur_tx);
1368 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1369 netif_stop_queue (dev);
1370
1371 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1372 dev->name, skb->data, skb->len, entry);
1373
1374 return 0;
1375 }
1376
1377
1378 static void netdrv_tx_interrupt (struct net_device *dev,
1379 struct netdrv_private *tp,
1380 void *ioaddr)
1381 {
1382 int cur_tx, dirty_tx, tx_left;
1383
1384 assert (dev != NULL);
1385 assert (tp != NULL);
1386 assert (ioaddr != NULL);
1387
1388 dirty_tx = atomic_read (&tp->dirty_tx);
1389
1390 cur_tx = atomic_read (&tp->cur_tx);
1391 tx_left = cur_tx - dirty_tx;
1392 while (tx_left > 0) {
1393 int entry = dirty_tx % NUM_TX_DESC;
1394 int txstatus;
1395
1396 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1397
1398 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1399 break; /* It still hasn't been Txed */
1400
1401 /* Note: TxCarrierLost is always asserted at 100mbps. */
1402 if (txstatus & (TxOutOfWindow | TxAborted)) {
1403 /* There was an major error, log it. */
1404 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1405 dev->name, txstatus);
1406 tp->stats.tx_errors++;
1407 if (txstatus & TxAborted) {
1408 tp->stats.tx_aborted_errors++;
1409 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1410 }
1411 if (txstatus & TxCarrierLost)
1412 tp->stats.tx_carrier_errors++;
1413 if (txstatus & TxOutOfWindow)
1414 tp->stats.tx_window_errors++;
1415 } else {
1416 if (txstatus & TxUnderrun) {
1417 /* Add 64 to the Tx FIFO threshold. */
1418 if (tp->tx_flag < 0x00300000)
1419 tp->tx_flag += 0x00020000;
1420 tp->stats.tx_fifo_errors++;
1421 }
1422 tp->stats.collisions += (txstatus >> 24) & 15;
1423 tp->stats.tx_bytes += txstatus & 0x7ff;
1424 tp->stats.tx_packets++;
1425 }
1426
1427 /* Free the original skb. */
1428 if (tp->tx_info[entry].mapping != 0) {
1429 pci_unmap_single(tp->pci_dev,
1430 tp->tx_info[entry].mapping,
1431 tp->tx_info[entry].skb->len,
1432 PCI_DMA_TODEVICE);
1433 tp->tx_info[entry].mapping = 0;
1434 }
1435 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1436 tp->tx_info[entry].skb = NULL;
1437 dirty_tx++;
1438 if (dirty_tx < 0) { /* handle signed int overflow */
1439 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1440 dirty_tx = cur_tx - tx_left + 1;
1441 }
1442 if (netif_queue_stopped (dev))
1443 netif_wake_queue (dev);
1444
1445 cur_tx = atomic_read (&tp->cur_tx);
1446 tx_left = cur_tx - dirty_tx;
1447
1448 }
1449
1450 #ifndef NETDRV_NDEBUG
1451 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1452 printk (KERN_ERR
1453 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1454 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1455 dirty_tx += NUM_TX_DESC;
1456 }
1457 #endif /* NETDRV_NDEBUG */
1458
1459 atomic_set (&tp->dirty_tx, dirty_tx);
1460 }
1461
1462
1463 /* TODO: clean this up! Rx reset need not be this intensive */
1464 static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1465 struct netdrv_private *tp, void *ioaddr)
1466 {
1467 u8 tmp8;
1468 int tmp_work = 1000;
1469
1470 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1471 dev->name, rx_status);
1472 if (rx_status & RxTooLong) {
1473 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1474 dev->name, rx_status);
1475 /* A.C.: The chip hangs here. */
1476 }
1477 tp->stats.rx_errors++;
1478 if (rx_status & (RxBadSymbol | RxBadAlign))
1479 tp->stats.rx_frame_errors++;
1480 if (rx_status & (RxRunt | RxTooLong))
1481 tp->stats.rx_length_errors++;
1482 if (rx_status & RxCRCErr)
1483 tp->stats.rx_crc_errors++;
1484 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1485 tp->cur_rx = 0;
1486
1487 /* disable receive */
1488 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1489 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1490
1491 /* A.C.: Reset the multicast list. */
1492 netdrv_set_rx_mode (dev);
1493
1494 /* XXX potentially temporary hack to
1495 * restart hung receiver */
1496 while (--tmp_work > 0) {
1497 tmp8 = NETDRV_R8 (ChipCmd);
1498 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1499 break;
1500 NETDRV_W8_F (ChipCmd,
1501 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1502 }
1503
1504 /* G.S.: Re-enable receiver */
1505 /* XXX temporary hack to work around receiver hang */
1506 netdrv_set_rx_mode (dev);
1507
1508 if (tmp_work <= 0)
1509 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1510 }
1511
1512
1513 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1514 field alignments and semantics. */
1515 static void netdrv_rx_interrupt (struct net_device *dev,
1516 struct netdrv_private *tp, void *ioaddr)
1517 {
1518 unsigned char *rx_ring;
1519 u16 cur_rx;
1520
1521 assert (dev != NULL);
1522 assert (tp != NULL);
1523 assert (ioaddr != NULL);
1524
1525 rx_ring = tp->rx_ring;
1526 cur_rx = tp->cur_rx;
1527
1528 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1529 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1530 NETDRV_R16 (RxBufAddr),
1531 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1532
1533 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1534 int ring_offset = cur_rx % RX_BUF_LEN;
1535 u32 rx_status;
1536 unsigned int rx_size;
1537 unsigned int pkt_size;
1538 struct sk_buff *skb;
1539
1540 /* read size+status of next frame from DMA ring buffer */
1541 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1542 rx_size = rx_status >> 16;
1543 pkt_size = rx_size - 4;
1544
1545 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1546 " cur %4.4x.\n", dev->name, rx_status,
1547 rx_size, cur_rx);
1548 #if NETDRV_DEBUG > 2
1549 {
1550 int i;
1551 DPRINTK ("%s: Frame contents ", dev->name);
1552 for (i = 0; i < 70; i++)
1553 printk (" %2.2x",
1554 rx_ring[ring_offset + i]);
1555 printk (".\n");
1556 }
1557 #endif
1558
1559 /* If Rx err or invalid rx_size/rx_status received
1560 * (which happens if we get lost in the ring),
1561 * Rx process gets reset, so we abort any further
1562 * Rx processing.
1563 */
1564 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1565 (!(rx_status & RxStatusOK))) {
1566 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1567 return;
1568 }
1569
1570 /* Malloc up new buffer, compatible with net-2e. */
1571 /* Omit the four octet CRC from the length. */
1572
1573 /* TODO: consider allocating skb's outside of
1574 * interrupt context, both to speed interrupt processing,
1575 * and also to reduce the chances of having to
1576 * drop packets here under memory pressure.
1577 */
1578
1579 skb = dev_alloc_skb (pkt_size + 2);
1580 if (skb) {
1581 skb->dev = dev;
1582 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1583
1584 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1585 skb_put (skb, pkt_size);
1586
1587 skb->protocol = eth_type_trans (skb, dev);
1588 netif_rx (skb);
1589 dev->last_rx = jiffies;
1590 tp->stats.rx_bytes += pkt_size;
1591 tp->stats.rx_packets++;
1592 } else {
1593 printk (KERN_WARNING
1594 "%s: Memory squeeze, dropping packet.\n",
1595 dev->name);
1596 tp->stats.rx_dropped++;
1597 }
1598
1599 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1600 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1601 }
1602
1603 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1604 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1605 NETDRV_R16 (RxBufAddr),
1606 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1607
1608 tp->cur_rx = cur_rx;
1609 }
1610
1611
1612 static void netdrv_weird_interrupt (struct net_device *dev,
1613 struct netdrv_private *tp,
1614 void *ioaddr,
1615 int status, int link_changed)
1616 {
1617 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1618 dev->name, status);
1619
1620 assert (dev != NULL);
1621 assert (tp != NULL);
1622 assert (ioaddr != NULL);
1623
1624 /* Update the error count. */
1625 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1626 NETDRV_W32 (RxMissed, 0);
1627
1628 if ((status & RxUnderrun) && link_changed &&
1629 (tp->drv_flags & HAS_LNK_CHNG)) {
1630 /* Really link-change on new chips. */
1631 int lpar = NETDRV_R16 (NWayLPAR);
1632 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1633 || tp->duplex_lock;
1634 if (tp->full_duplex != duplex) {
1635 tp->full_duplex = duplex;
1636 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1637 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1638 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1639 }
1640 status &= ~RxUnderrun;
1641 }
1642
1643 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1644 if (status &
1645 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1646 tp->stats.rx_errors++;
1647
1648 if (status & (PCSTimeout))
1649 tp->stats.rx_length_errors++;
1650 if (status & (RxUnderrun | RxFIFOOver))
1651 tp->stats.rx_fifo_errors++;
1652 if (status & RxOverflow) {
1653 tp->stats.rx_over_errors++;
1654 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1655 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1656 }
1657 if (status & PCIErr) {
1658 u16 pci_cmd_status;
1659 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1660
1661 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1662 dev->name, pci_cmd_status);
1663 }
1664 }
1665
1666
1667 /* The interrupt handler does all of the Rx thread work and cleans up
1668 after the Tx thread. */
1669 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance,
1670 struct pt_regs *regs)
1671 {
1672 struct net_device *dev = (struct net_device *) dev_instance;
1673 struct netdrv_private *tp = dev->priv;
1674 int boguscnt = max_interrupt_work;
1675 void *ioaddr = tp->mmio_addr;
1676 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1677 int handled = 0;
1678
1679 spin_lock (&tp->lock);
1680
1681 do {
1682 status = NETDRV_R16 (IntrStatus);
1683
1684 /* h/w no longer present (hotplug?) or major error, bail */
1685 if (status == 0xFFFF)
1686 break;
1687
1688 handled = 1;
1689 /* Acknowledge all of the current interrupt sources ASAP */
1690 NETDRV_W16_F (IntrStatus, status);
1691
1692 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1693 dev->name, status,
1694 NETDRV_R16 (IntrStatus));
1695
1696 if ((status &
1697 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1698 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1699 break;
1700
1701 /* Check uncommon events with one test. */
1702 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1703 RxFIFOOver | TxErr | RxErr))
1704 netdrv_weird_interrupt (dev, tp, ioaddr,
1705 status, link_changed);
1706
1707 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1708 netdrv_rx_interrupt (dev, tp, ioaddr);
1709
1710 if (status & (TxOK | TxErr))
1711 netdrv_tx_interrupt (dev, tp, ioaddr);
1712
1713 boguscnt--;
1714 } while (boguscnt > 0);
1715
1716 if (boguscnt <= 0) {
1717 printk (KERN_WARNING
1718 "%s: Too much work at interrupt, "
1719 "IntrStatus=0x%4.4x.\n", dev->name,
1720 status);
1721
1722 /* Clear all interrupt sources. */
1723 NETDRV_W16 (IntrStatus, 0xffff);
1724 }
1725
1726 spin_unlock (&tp->lock);
1727
1728 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1729 dev->name, NETDRV_R16 (IntrStatus));
1730 return IRQ_RETVAL(handled);
1731 }
1732
1733
1734 static int netdrv_close (struct net_device *dev)
1735 {
1736 struct netdrv_private *tp = dev->priv;
1737 void *ioaddr = tp->mmio_addr;
1738 unsigned long flags;
1739
1740 DPRINTK ("ENTER\n");
1741
1742 netif_stop_queue (dev);
1743
1744 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1745 dev->name, NETDRV_R16 (IntrStatus));
1746
1747 del_timer_sync (&tp->timer);
1748
1749 spin_lock_irqsave (&tp->lock, flags);
1750
1751 /* Stop the chip's Tx and Rx DMA processes. */
1752 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1753
1754 /* Disable interrupts by clearing the interrupt mask. */
1755 NETDRV_W16 (IntrMask, 0x0000);
1756
1757 /* Update the error counts. */
1758 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1759 NETDRV_W32 (RxMissed, 0);
1760
1761 spin_unlock_irqrestore (&tp->lock, flags);
1762
1763 synchronize_irq ();
1764 free_irq (dev->irq, dev);
1765
1766 netdrv_tx_clear (tp);
1767
1768 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1769 tp->rx_ring, tp->rx_ring_dma);
1770 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1771 tp->tx_bufs, tp->tx_bufs_dma);
1772 tp->rx_ring = NULL;
1773 tp->tx_bufs = NULL;
1774
1775 /* Green! Put the chip in low-power mode. */
1776 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1777 NETDRV_W8 (Config1, 0x03);
1778 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1779
1780 DPRINTK ("EXIT\n");
1781 return 0;
1782 }
1783
1784
1785 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1786 {
1787 struct netdrv_private *tp = dev->priv;
1788 struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
1789 unsigned long flags;
1790 int rc = 0;
1791
1792 DPRINTK ("ENTER\n");
1793
1794 switch (cmd) {
1795 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1796 data->phy_id = tp->phys[0] & 0x3f;
1797 /* Fall Through */
1798
1799 case SIOCGMIIREG: /* Read MII PHY register. */
1800 spin_lock_irqsave (&tp->lock, flags);
1801 data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1802 spin_unlock_irqrestore (&tp->lock, flags);
1803 break;
1804
1805 case SIOCSMIIREG: /* Write MII PHY register. */
1806 if (!capable (CAP_NET_ADMIN)) {
1807 rc = -EPERM;
1808 break;
1809 }
1810
1811 spin_lock_irqsave (&tp->lock, flags);
1812 mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1813 spin_unlock_irqrestore (&tp->lock, flags);
1814 break;
1815
1816 default:
1817 rc = -EOPNOTSUPP;
1818 break;
1819 }
1820
1821 DPRINTK ("EXIT, returning %d\n", rc);
1822 return rc;
1823 }
1824
1825
1826 static struct net_device_stats *netdrv_get_stats (struct net_device *dev)
1827 {
1828 struct netdrv_private *tp = dev->priv;
1829 void *ioaddr = tp->mmio_addr;
1830
1831 DPRINTK ("ENTER\n");
1832
1833 assert (tp != NULL);
1834
1835 if (netif_running(dev)) {
1836 unsigned long flags;
1837
1838 spin_lock_irqsave (&tp->lock, flags);
1839
1840 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1841 NETDRV_W32 (RxMissed, 0);
1842
1843 spin_unlock_irqrestore (&tp->lock, flags);
1844 }
1845
1846 DPRINTK ("EXIT\n");
1847 return &tp->stats;
1848 }
1849
1850 /* Set or clear the multicast filter for this adaptor.
1851 This routine is not state sensitive and need not be SMP locked. */
1852
1853 static void netdrv_set_rx_mode (struct net_device *dev)
1854 {
1855 struct netdrv_private *tp = dev->priv;
1856 void *ioaddr = tp->mmio_addr;
1857 u32 mc_filter[2]; /* Multicast hash filter */
1858 int i, rx_mode;
1859 u32 tmp;
1860
1861 DPRINTK ("ENTER\n");
1862
1863 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1864 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1865
1866 /* Note: do not reorder, GCC is clever about common statements. */
1867 if (dev->flags & IFF_PROMISC) {
1868 /* Unconditionally log net taps. */
1869 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1870 dev->name);
1871 rx_mode =
1872 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1873 AcceptAllPhys;
1874 mc_filter[1] = mc_filter[0] = 0xffffffff;
1875 } else if ((dev->mc_count > multicast_filter_limit)
1876 || (dev->flags & IFF_ALLMULTI)) {
1877 /* Too many to filter perfectly -- accept all multicasts. */
1878 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1879 mc_filter[1] = mc_filter[0] = 0xffffffff;
1880 } else {
1881 struct dev_mc_list *mclist;
1882 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1883 mc_filter[1] = mc_filter[0] = 0;
1884 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1885 i++, mclist = mclist->next)
1886 set_bit (ether_crc (ETH_ALEN, mclist->dmi_addr) >> 26,
1887 mc_filter);
1888 }
1889
1890 /* if called from irq handler, lock already acquired */
1891 if (!in_irq ())
1892 spin_lock_irq (&tp->lock);
1893
1894 /* We can safely update without stopping the chip. */
1895 tmp = netdrv_rx_config | rx_mode |
1896 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1897 NETDRV_W32_F (RxConfig, tmp);
1898 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1899 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1900
1901 if (!in_irq ())
1902 spin_unlock_irq (&tp->lock);
1903
1904 DPRINTK ("EXIT\n");
1905 }
1906
1907
1908 #ifdef CONFIG_PM
1909
1910 static int netdrv_suspend (struct pci_dev *pdev, u32 state)
1911 {
1912 struct net_device *dev = pci_get_drvdata (pdev);
1913 struct netdrv_private *tp = dev->priv;
1914 void *ioaddr = tp->mmio_addr;
1915 unsigned long flags;
1916
1917 if (!netif_running(dev))
1918 return;
1919 netif_device_detach (dev);
1920
1921 spin_lock_irqsave (&tp->lock, flags);
1922
1923 /* Disable interrupts, stop Tx and Rx. */
1924 NETDRV_W16 (IntrMask, 0x0000);
1925 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1926
1927 /* Update the error counts. */
1928 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1929 NETDRV_W32 (RxMissed, 0);
1930
1931 spin_unlock_irqrestore (&tp->lock, flags);
1932
1933 pci_power_off (pdev, -1);
1934
1935 return 0;
1936 }
1937
1938
1939 static int netdrv_resume (struct pci_dev *pdev)
1940 {
1941 struct net_device *dev = pci_get_drvdata (pdev);
1942
1943 if (!netif_running(dev))
1944 return;
1945 pci_power_on (pdev);
1946 netif_device_attach (dev);
1947 netdrv_hw_start (dev);
1948
1949 return 0;
1950 }
1951
1952 #endif /* CONFIG_PM */
1953
1954
1955 static struct pci_driver netdrv_pci_driver = {
1956 .name = MODNAME,
1957 .id_table = netdrv_pci_tbl,
1958 .probe = netdrv_init_one,
1959 .remove = __devexit_p(netdrv_remove_one),
1960 #ifdef CONFIG_PM
1961 .suspend = netdrv_suspend,
1962 .resume = netdrv_resume,
1963 #endif /* CONFIG_PM */
1964 };
1965
1966
1967 static int __init netdrv_init_module (void)
1968 {
1969 /* when a module, this is printed whether or not devices are found in probe */
1970 #ifdef MODULE
1971 printk(version);
1972 #endif
1973 return pci_module_init (&netdrv_pci_driver);
1974 }
1975
1976
1977 static void __exit netdrv_cleanup_module (void)
1978 {
1979 pci_unregister_driver (&netdrv_pci_driver);
1980 }
1981
1982
1983 module_init(netdrv_init_module);
1984 module_exit(netdrv_cleanup_module);
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