drivers/net/mace.c

   1 /*
   2  * Network device driver for the MACE ethernet controller on
   3  * Apple Powermacs.  Assumes it's under a DBDMA controller.
   4  *
   5  * Copyright (C) 1996 Paul Mackerras.
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/module.h>
  10 #include <linux/version.h>
  11 #include <linux/kernel.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/etherdevice.h>
  14 #include <linux/delay.h>
  15 #include <linux/string.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/crc32.h>
  19 #include <linux/spinlock.h>
  20 #include <asm/prom.h>
  21 #include <asm/dbdma.h>
  22 #include <asm/io.h>
  23 #include <asm/pgtable.h>
  24 #include "mace.h"
  25
  26 static struct net_device *mace_devs;
  27 static int port_aaui = -1;
  28
  29 #define N_RX_RING       8
  30 #define N_TX_RING       6
  31 #define MAX_TX_ACTIVE   1
  32 #define NCMDS_TX        1       /* dma commands per element in tx ring */
  33 #define RX_BUFLEN       (ETH_FRAME_LEN + 8)
  34 #define TX_TIMEOUT      HZ      /* 1 second */
  35
  36 /* Chip rev needs workaround on HW & multicast addr change */
  37 #define BROKEN_ADDRCHG_REV      0x0941
  38
  39 /* Bits in transmit DMA status */
  40 #define TX_DMA_ERR      0x80
  41
  42 struct mace_data {
  43     volatile struct mace *mace;
  44     volatile struct dbdma_regs *tx_dma;
  45     int tx_dma_intr;
  46     volatile struct dbdma_regs *rx_dma;
  47     int rx_dma_intr;
  48     volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
  49     volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
  50     struct sk_buff *rx_bufs[N_RX_RING];
  51     int rx_fill;
  52     int rx_empty;
  53     struct sk_buff *tx_bufs[N_TX_RING];
  54     int tx_fill;
  55     int tx_empty;
  56     unsigned char maccc;
  57     unsigned char tx_fullup;
  58     unsigned char tx_active;
  59     unsigned char tx_bad_runt;
  60     struct net_device_stats stats;
  61     struct timer_list tx_timeout;
  62     int timeout_active;
  63     int port_aaui;
  64     int chipid;
  65     struct device_node* of_node;
  66     struct net_device *next_mace;
  67     spinlock_t lock;
  68 };
  69
  70 /*
  71  * Number of bytes of private data per MACE: allow enough for
  72  * the rx and tx dma commands plus a branch dma command each,
  73  * and another 16 bytes to allow us to align the dma command
  74  * buffers on a 16 byte boundary.
  75  */
  76 #define PRIV_BYTES      (sizeof(struct mace_data) \
  77         + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
  78
  79 static int bitrev(int);
  80 static int mace_probe(void);
  81 static void mace_probe1(struct device_node *mace);
  82 static int mace_open(struct net_device *dev);
  83 static int mace_close(struct net_device *dev);
  84 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
  85 static struct net_device_stats *mace_stats(struct net_device *dev);
  86 static void mace_set_multicast(struct net_device *dev);
  87 static void mace_reset(struct net_device *dev);
  88 static int mace_set_address(struct net_device *dev, void *addr);
  89 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  90 static irqreturn_t mace_txdma_intr(int irq, void *dev_id, struct pt_regs *regs);
  91 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs);
  92 static void mace_set_timeout(struct net_device *dev);
  93 static void mace_tx_timeout(unsigned long data);
  94 static inline void dbdma_reset(volatile struct dbdma_regs *dma);
  95 static inline void mace_clean_rings(struct mace_data *mp);
  96 static void __mace_set_address(struct net_device *dev, void *addr);
  97
  98 /*
  99  * If we can't get a skbuff when we need it, we use this area for DMA.
 100  */
 101 static unsigned char *dummy_buf;
 102
 103 /* Bit-reverse one byte of an ethernet hardware address. */
 104 static inline int
 105 bitrev(int b)
 106 {
 107     int d = 0, i;
 108
 109     for (i = 0; i < 8; ++i, b >>= 1)
 110         d = (d << 1) | (b & 1);
 111     return d;
 112 }
 113
 114 static int __init mace_probe(void)
 115 {
 116         struct device_node *mace;
 117
 118         for (mace = find_devices("mace"); mace != NULL; mace = mace->next)
 119                 mace_probe1(mace);
 120         return mace_devs? 0: -ENODEV;
 121 }
 122
 123 static void __init mace_probe1(struct device_node *mace)
 124 {
 125         int j, rev;
 126         struct net_device *dev;
 127         struct mace_data *mp;
 128         unsigned char *addr;
 129
 130         if (mace->n_addrs != 3 || mace->n_intrs != 3) {
 131                 printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n",
 132                        mace->full_name);
 133                 return;
 134         }
 135
 136         addr = get_property(mace, "mac-address", NULL);
 137         if (addr == NULL) {
 138                 addr = get_property(mace, "local-mac-address", NULL);
 139                 if (addr == NULL) {
 140                         printk(KERN_ERR "Can't get mac-address for MACE %s\n",
 141                                mace->full_name);
 142                         return;
 143                 }
 144         }
 145
 146         if (dummy_buf == NULL) {
 147                 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
 148                 if (dummy_buf == NULL) {
 149                         printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n");
 150                         return;
 151                 }
 152         }
 153
 154         dev = init_etherdev(0, PRIV_BYTES);
 155         if (!dev)
 156                 return;
 157         SET_MODULE_OWNER(dev);
 158
 159         mp = dev->priv;
 160         mp->of_node = mace;
 161
 162         if (!request_OF_resource(mace, 0, " (mace)")) {
 163                 printk(KERN_ERR "MACE: can't request IO resource !\n");
 164                 goto err_out;
 165         }
 166         if (!request_OF_resource(mace, 1, " (mace tx dma)")) {
 167                 printk(KERN_ERR "MACE: can't request TX DMA resource !\n");
 168                 goto err_out;
 169         }
 170
 171         if (!request_OF_resource(mace, 2, " (mace tx dma)")) {
 172                 printk(KERN_ERR "MACE: can't request RX DMA resource !\n");
 173                 goto err_out;
 174         }
 175
 176         dev->base_addr = mace->addrs[0].address;
 177         mp->mace = (volatile struct mace *)
 178                 ioremap(mace->addrs[0].address, 0x1000);
 179         dev->irq = mace->intrs[0].line;
 180
 181         printk(KERN_INFO "%s: MACE at", dev->name);
 182         rev = addr[0] == 0 && addr[1] == 0xA0;
 183         for (j = 0; j < 6; ++j) {
 184                 dev->dev_addr[j] = rev? bitrev(addr[j]): addr[j];
 185                 printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
 186         }
 187         mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
 188                         in_8(&mp->mace->chipid_lo);
 189         printk(", chip revision %d.%d\n", mp->chipid >> 8, mp->chipid & 0xff);
 190
 191
 192         mp = (struct mace_data *) dev->priv;
 193         mp->maccc = ENXMT | ENRCV;
 194         mp->tx_dma = (volatile struct dbdma_regs *)
 195                 ioremap(mace->addrs[1].address, 0x1000);
 196         mp->tx_dma_intr = mace->intrs[1].line;
 197         mp->rx_dma = (volatile struct dbdma_regs *)
 198                 ioremap(mace->addrs[2].address, 0x1000);
 199         mp->rx_dma_intr = mace->intrs[2].line;
 200
 201         mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
 202         mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
 203
 204         memset(&mp->stats, 0, sizeof(mp->stats));
 205         memset((char *) mp->tx_cmds, 0,
 206                (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
 207         init_timer(&mp->tx_timeout);
 208         spin_lock_init(&mp->lock);
 209         mp->timeout_active = 0;
 210
 211         if (port_aaui >= 0)
 212                 mp->port_aaui = port_aaui;
 213         else {
 214                 /* Apple Network Server uses the AAUI port */
 215                 if (machine_is_compatible("AAPL,ShinerESB"))
 216                         mp->port_aaui = 1;
 217                 else {
 218 #ifdef CONFIG_MACE_AAUI_PORT
 219                         mp->port_aaui = 1;
 220 #else
 221                         mp->port_aaui = 0;
 222 #endif
 223                 }
 224         }
 225
 226         dev->open = mace_open;
 227         dev->stop = mace_close;
 228         dev->hard_start_xmit = mace_xmit_start;
 229         dev->get_stats = mace_stats;
 230         dev->set_multicast_list = mace_set_multicast;
 231         dev->set_mac_address = mace_set_address;
 232
 233         ether_setup(dev);
 234
 235         mace_reset(dev);
 236
 237         if (request_irq(dev->irq, mace_interrupt, 0, "MACE", dev))
 238                 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
 239         if (request_irq(mace->intrs[1].line, mace_txdma_intr, 0, "MACE-txdma",
 240                         dev))
 241                 printk(KERN_ERR "MACE: can't get irq %d\n", mace->intrs[1].line);
 242         if (request_irq(mace->intrs[2].line, mace_rxdma_intr, 0, "MACE-rxdma",
 243                         dev))
 244                 printk(KERN_ERR "MACE: can't get irq %d\n", mace->intrs[2].line);
 245
 246         mp->next_mace = mace_devs;
 247         mace_devs = dev;
 248         return;
 249
 250 err_out:
 251         unregister_netdev(dev);
 252         if (mp->of_node) {
 253                 release_OF_resource(mp->of_node, 0);
 254                 release_OF_resource(mp->of_node, 1);
 255                 release_OF_resource(mp->of_node, 2);
 256         }
 257         kfree(dev);
 258 }
 259
 260 static void dbdma_reset(volatile struct dbdma_regs *dma)
 261 {
 262     int i;
 263
 264     out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
 265
 266     /*
 267      * Yes this looks peculiar, but apparently it needs to be this
 268      * way on some machines.
 269      */
 270     for (i = 200; i > 0; --i)
 271         if (ld_le32(&dma->control) & RUN)
 272             udelay(1);
 273 }
 274
 275 static void mace_reset(struct net_device *dev)
 276 {
 277     struct mace_data *mp = (struct mace_data *) dev->priv;
 278     volatile struct mace *mb = mp->mace;
 279     int i;
 280
 281     /* soft-reset the chip */
 282     i = 200;
 283     while (--i) {
 284         out_8(&mb->biucc, SWRST);
 285         if (in_8(&mb->biucc) & SWRST) {
 286             udelay(10);
 287             continue;
 288         }
 289         break;
 290     }
 291     if (!i) {
 292         printk(KERN_ERR "mace: cannot reset chip!\n");
 293         return;
 294     }
 295
 296     out_8(&mb->imr, 0xff);      /* disable all intrs for now */
 297     i = in_8(&mb->ir);
 298     out_8(&mb->maccc, 0);       /* turn off tx, rx */
 299
 300     out_8(&mb->biucc, XMTSP_64);
 301     out_8(&mb->utr, RTRD);
 302     out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
 303     out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
 304     out_8(&mb->rcvfc, 0);
 305
 306     /* load up the hardware address */
 307     __mace_set_address(dev, dev->dev_addr);
 308
 309     /* clear the multicast filter */
 310     if (mp->chipid == BROKEN_ADDRCHG_REV)
 311         out_8(&mb->iac, LOGADDR);
 312     else {
 313         out_8(&mb->iac, ADDRCHG | LOGADDR);
 314         while ((in_8(&mb->iac) & ADDRCHG) != 0)
 315                 ;
 316     }
 317     for (i = 0; i < 8; ++i)
 318         out_8(&mb->ladrf, 0);
 319
 320     /* done changing address */
 321     if (mp->chipid != BROKEN_ADDRCHG_REV)
 322         out_8(&mb->iac, 0);
 323
 324     if (mp->port_aaui)
 325         out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
 326     else
 327         out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
 328 }
 329
 330 static void __mace_set_address(struct net_device *dev, void *addr)
 331 {
 332     struct mace_data *mp = (struct mace_data *) dev->priv;
 333     volatile struct mace *mb = mp->mace;
 334     unsigned char *p = addr;
 335     int i;
 336
 337     /* load up the hardware address */
 338     if (mp->chipid == BROKEN_ADDRCHG_REV)
 339         out_8(&mb->iac, PHYADDR);
 340     else {
 341         out_8(&mb->iac, ADDRCHG | PHYADDR);
 342         while ((in_8(&mb->iac) & ADDRCHG) != 0)
 343             ;
 344     }
 345     for (i = 0; i < 6; ++i)
 346         out_8(&mb->padr, dev->dev_addr[i] = p[i]);
 347     if (mp->chipid != BROKEN_ADDRCHG_REV)
 348         out_8(&mb->iac, 0);
 349 }
 350
 351 static int mace_set_address(struct net_device *dev, void *addr)
 352 {
 353     struct mace_data *mp = (struct mace_data *) dev->priv;
 354     volatile struct mace *mb = mp->mace;
 355     unsigned long flags;
 356
 357     spin_lock_irqsave(&mp->lock, flags);
 358
 359     __mace_set_address(dev, addr);
 360
 361     /* note: setting ADDRCHG clears ENRCV */
 362     out_8(&mb->maccc, mp->maccc);
 363
 364     spin_unlock_irqrestore(&mp->lock, flags);
 365     return 0;
 366 }
 367
 368 static inline void mace_clean_rings(struct mace_data *mp)
 369 {
 370     int i;
 371
 372     /* free some skb's */
 373     for (i = 0; i < N_RX_RING; ++i) {
 374         if (mp->rx_bufs[i] != 0) {
 375             dev_kfree_skb(mp->rx_bufs[i]);
 376             mp->rx_bufs[i] = 0;
 377         }
 378     }
 379     for (i = mp->tx_empty; i != mp->tx_fill; ) {
 380         dev_kfree_skb(mp->tx_bufs[i]);
 381         if (++i >= N_TX_RING)
 382             i = 0;
 383     }
 384 }
 385
 386 static int mace_open(struct net_device *dev)
 387 {
 388     struct mace_data *mp = (struct mace_data *) dev->priv;
 389     volatile struct mace *mb = mp->mace;
 390     volatile struct dbdma_regs *rd = mp->rx_dma;
 391     volatile struct dbdma_regs *td = mp->tx_dma;
 392     volatile struct dbdma_cmd *cp;
 393     int i;
 394     struct sk_buff *skb;
 395     unsigned char *data;
 396
 397     /* reset the chip */
 398     mace_reset(dev);
 399
 400     /* initialize list of sk_buffs for receiving and set up recv dma */
 401     mace_clean_rings(mp);
 402     memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
 403     cp = mp->rx_cmds;
 404     for (i = 0; i < N_RX_RING - 1; ++i) {
 405         skb = dev_alloc_skb(RX_BUFLEN + 2);
 406         if (skb == 0) {
 407             data = dummy_buf;
 408         } else {
 409             skb_reserve(skb, 2);        /* so IP header lands on 4-byte bdry */
 410             data = skb->data;
 411         }
 412         mp->rx_bufs[i] = skb;
 413         st_le16(&cp->req_count, RX_BUFLEN);
 414         st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
 415         st_le32(&cp->phy_addr, virt_to_bus(data));
 416         cp->xfer_status = 0;
 417         ++cp;
 418     }
 419     mp->rx_bufs[i] = 0;
 420     st_le16(&cp->command, DBDMA_STOP);
 421     mp->rx_fill = i;
 422     mp->rx_empty = 0;
 423
 424     /* Put a branch back to the beginning of the receive command list */
 425     ++cp;
 426     st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
 427     st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds));
 428
 429     /* start rx dma */
 430     out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
 431     out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
 432     out_le32(&rd->control, (RUN << 16) | RUN);
 433
 434     /* put a branch at the end of the tx command list */
 435     cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
 436     st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
 437     st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds));
 438
 439     /* reset tx dma */
 440     out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
 441     out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
 442     mp->tx_fill = 0;
 443     mp->tx_empty = 0;
 444     mp->tx_fullup = 0;
 445     mp->tx_active = 0;
 446     mp->tx_bad_runt = 0;
 447
 448     /* turn it on! */
 449     out_8(&mb->maccc, mp->maccc);
 450     /* enable all interrupts except receive interrupts */
 451     out_8(&mb->imr, RCVINT);
 452
 453     return 0;
 454 }
 455
 456 static int mace_close(struct net_device *dev)
 457 {
 458     struct mace_data *mp = (struct mace_data *) dev->priv;
 459     volatile struct mace *mb = mp->mace;
 460     volatile struct dbdma_regs *rd = mp->rx_dma;
 461     volatile struct dbdma_regs *td = mp->tx_dma;
 462
 463     /* disable rx and tx */
 464     out_8(&mb->maccc, 0);
 465     out_8(&mb->imr, 0xff);              /* disable all intrs */
 466
 467     /* disable rx and tx dma */
 468     st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
 469     st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
 470
 471     mace_clean_rings(mp);
 472
 473     return 0;
 474 }
 475
 476 static inline void mace_set_timeout(struct net_device *dev)
 477 {
 478     struct mace_data *mp = (struct mace_data *) dev->priv;
 479
 480     if (mp->timeout_active)
 481         del_timer(&mp->tx_timeout);
 482     mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
 483     mp->tx_timeout.function = mace_tx_timeout;
 484     mp->tx_timeout.data = (unsigned long) dev;
 485     add_timer(&mp->tx_timeout);
 486     mp->timeout_active = 1;
 487 }
 488
 489 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
 490 {
 491     struct mace_data *mp = (struct mace_data *) dev->priv;
 492     volatile struct dbdma_regs *td = mp->tx_dma;
 493     volatile struct dbdma_cmd *cp, *np;
 494     unsigned long flags;
 495     int fill, next, len;
 496
 497     /* see if there's a free slot in the tx ring */
 498     spin_lock_irqsave(&mp->lock, flags);
 499     fill = mp->tx_fill;
 500     next = fill + 1;
 501     if (next >= N_TX_RING)
 502         next = 0;
 503     if (next == mp->tx_empty) {
 504         netif_stop_queue(dev);
 505         mp->tx_fullup = 1;
 506         spin_unlock_irqrestore(&mp->lock, flags);
 507         return 1;               /* can't take it at the moment */
 508     }
 509     spin_unlock_irqrestore(&mp->lock, flags);
 510
 511     /* partially fill in the dma command block */
 512     len = skb->len;
 513     if (len > ETH_FRAME_LEN) {
 514         printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
 515         len = ETH_FRAME_LEN;
 516     }
 517     mp->tx_bufs[fill] = skb;
 518     cp = mp->tx_cmds + NCMDS_TX * fill;
 519     st_le16(&cp->req_count, len);
 520     st_le32(&cp->phy_addr, virt_to_bus(skb->data));
 521
 522     np = mp->tx_cmds + NCMDS_TX * next;
 523     out_le16(&np->command, DBDMA_STOP);
 524
 525     /* poke the tx dma channel */
 526     spin_lock_irqsave(&mp->lock, flags);
 527     mp->tx_fill = next;
 528     if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
 529         out_le16(&cp->xfer_status, 0);
 530         out_le16(&cp->command, OUTPUT_LAST);
 531         out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
 532         ++mp->tx_active;
 533         mace_set_timeout(dev);
 534     }
 535     if (++next >= N_TX_RING)
 536         next = 0;
 537     if (next == mp->tx_empty)
 538         netif_stop_queue(dev);
 539     spin_unlock_irqrestore(&mp->lock, flags);
 540
 541     return 0;
 542 }
 543
 544 static struct net_device_stats *mace_stats(struct net_device *dev)
 545 {
 546     struct mace_data *p = (struct mace_data *) dev->priv;
 547
 548     return &p->stats;
 549 }
 550
 551 static void mace_set_multicast(struct net_device *dev)
 552 {
 553     struct mace_data *mp = (struct mace_data *) dev->priv;
 554     volatile struct mace *mb = mp->mace;
 555     int i, j;
 556     u32 crc;
 557     unsigned long flags;
 558
 559     spin_lock_irqsave(&mp->lock, flags);
 560     mp->maccc &= ~PROM;
 561     if (dev->flags & IFF_PROMISC) {
 562         mp->maccc |= PROM;
 563     } else {
 564         unsigned char multicast_filter[8];
 565         struct dev_mc_list *dmi = dev->mc_list;
 566
 567         if (dev->flags & IFF_ALLMULTI) {
 568             for (i = 0; i < 8; i++)
 569                 multicast_filter[i] = 0xff;
 570         } else {
 571             for (i = 0; i < 8; i++)
 572                 multicast_filter[i] = 0;
 573             for (i = 0; i < dev->mc_count; i++) {
 574                 crc = ether_crc_le(6, dmi->dmi_addr);
 575                 j = crc >> 26;  /* bit number in multicast_filter */
 576                 multicast_filter[j >> 3] |= 1 << (j & 7);
 577                 dmi = dmi->next;
 578             }
 579         }
 580 #if 0
 581         printk("Multicast filter :");
 582         for (i = 0; i < 8; i++)
 583             printk("%02x ", multicast_filter[i]);
 584         printk("\n");
 585 #endif
 586
 587         if (mp->chipid == BROKEN_ADDRCHG_REV)
 588             out_8(&mb->iac, LOGADDR);
 589         else {
 590             out_8(&mb->iac, ADDRCHG | LOGADDR);
 591             while ((in_8(&mb->iac) & ADDRCHG) != 0)
 592                 ;
 593         }
 594         for (i = 0; i < 8; ++i)
 595             out_8(&mb->ladrf, multicast_filter[i]);
 596         if (mp->chipid != BROKEN_ADDRCHG_REV)
 597             out_8(&mb->iac, 0);
 598     }
 599     /* reset maccc */
 600     out_8(&mb->maccc, mp->maccc);
 601     spin_unlock_irqrestore(&mp->lock, flags);
 602 }
 603
 604 static void mace_handle_misc_intrs(struct mace_data *mp, int intr)
 605 {
 606     volatile struct mace *mb = mp->mace;
 607     static int mace_babbles, mace_jabbers;
 608
 609     if (intr & MPCO)
 610         mp->stats.rx_missed_errors += 256;
 611     mp->stats.rx_missed_errors += in_8(&mb->mpc);   /* reading clears it */
 612     if (intr & RNTPCO)
 613         mp->stats.rx_length_errors += 256;
 614     mp->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
 615     if (intr & CERR)
 616         ++mp->stats.tx_heartbeat_errors;
 617     if (intr & BABBLE)
 618         if (mace_babbles++ < 4)
 619             printk(KERN_DEBUG "mace: babbling transmitter\n");
 620     if (intr & JABBER)
 621         if (mace_jabbers++ < 4)
 622             printk(KERN_DEBUG "mace: jabbering transceiver\n");
 623 }
 624
 625 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 626 {
 627     struct net_device *dev = (struct net_device *) dev_id;
 628     struct mace_data *mp = (struct mace_data *) dev->priv;
 629     volatile struct mace *mb = mp->mace;
 630     volatile struct dbdma_regs *td = mp->tx_dma;
 631     volatile struct dbdma_cmd *cp;
 632     int intr, fs, i, stat, x;
 633     int xcount, dstat;
 634     unsigned long flags;
 635     /* static int mace_last_fs, mace_last_xcount; */
 636
 637     spin_lock_irqsave(&mp->lock, flags);
 638     intr = in_8(&mb->ir);               /* read interrupt register */
 639     in_8(&mb->xmtrc);                   /* get retries */
 640     mace_handle_misc_intrs(mp, intr);
 641
 642     i = mp->tx_empty;
 643     while (in_8(&mb->pr) & XMTSV) {
 644         del_timer(&mp->tx_timeout);
 645         mp->timeout_active = 0;
 646         /*
 647          * Clear any interrupt indication associated with this status
 648          * word.  This appears to unlatch any error indication from
 649          * the DMA controller.
 650          */
 651         intr = in_8(&mb->ir);
 652         if (intr != 0)
 653             mace_handle_misc_intrs(mp, intr);
 654         if (mp->tx_bad_runt) {
 655             fs = in_8(&mb->xmtfs);
 656             mp->tx_bad_runt = 0;
 657             out_8(&mb->xmtfc, AUTO_PAD_XMIT);
 658             continue;
 659         }
 660         dstat = ld_le32(&td->status);
 661         /* stop DMA controller */
 662         out_le32(&td->control, RUN << 16);
 663         /*
 664          * xcount is the number of complete frames which have been
 665          * written to the fifo but for which status has not been read.
 666          */
 667         xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
 668         if (xcount == 0 || (dstat & DEAD)) {
 669             /*
 670              * If a packet was aborted before the DMA controller has
 671              * finished transferring it, it seems that there are 2 bytes
 672              * which are stuck in some buffer somewhere.  These will get
 673              * transmitted as soon as we read the frame status (which
 674              * reenables the transmit data transfer request).  Turning
 675              * off the DMA controller and/or resetting the MACE doesn't
 676              * help.  So we disable auto-padding and FCS transmission
 677              * so the two bytes will only be a runt packet which should
 678              * be ignored by other stations.
 679              */
 680             out_8(&mb->xmtfc, DXMTFCS);
 681         }
 682         fs = in_8(&mb->xmtfs);
 683         if ((fs & XMTSV) == 0) {
 684             printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
 685                    fs, xcount, dstat);
 686             mace_reset(dev);
 687                 /*
 688                  * XXX mace likes to hang the machine after a xmtfs error.
 689                  * This is hard to reproduce, reseting *may* help
 690                  */
 691         }
 692         cp = mp->tx_cmds + NCMDS_TX * i;
 693         stat = ld_le16(&cp->xfer_status);
 694         if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
 695             /*
 696              * Check whether there were in fact 2 bytes written to
 697              * the transmit FIFO.
 698              */
 699             udelay(1);
 700             x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
 701             if (x != 0) {
 702                 /* there were two bytes with an end-of-packet indication */
 703                 mp->tx_bad_runt = 1;
 704                 mace_set_timeout(dev);
 705             } else {
 706                 /*
 707                  * Either there weren't the two bytes buffered up, or they
 708                  * didn't have an end-of-packet indication.
 709                  * We flush the transmit FIFO just in case (by setting the
 710                  * XMTFWU bit with the transmitter disabled).
 711                  */
 712                 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
 713                 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
 714                 udelay(1);
 715                 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
 716                 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
 717             }
 718         }
 719         /* dma should have finished */
 720         if (i == mp->tx_fill) {
 721             printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
 722                    fs, xcount, dstat);
 723             continue;
 724         }
 725         /* Update stats */
 726         if (fs & (UFLO|LCOL|LCAR|RTRY)) {
 727             ++mp->stats.tx_errors;
 728             if (fs & LCAR)
 729                 ++mp->stats.tx_carrier_errors;
 730             if (fs & (UFLO|LCOL|RTRY))
 731                 ++mp->stats.tx_aborted_errors;
 732         } else {
 733             mp->stats.tx_bytes += mp->tx_bufs[i]->len;
 734             ++mp->stats.tx_packets;
 735         }
 736         dev_kfree_skb_irq(mp->tx_bufs[i]);
 737         --mp->tx_active;
 738         if (++i >= N_TX_RING)
 739             i = 0;
 740 #if 0
 741         mace_last_fs = fs;
 742         mace_last_xcount = xcount;
 743 #endif
 744     }
 745
 746     if (i != mp->tx_empty) {
 747         mp->tx_fullup = 0;
 748         netif_wake_queue(dev);
 749     }
 750     mp->tx_empty = i;
 751     i += mp->tx_active;
 752     if (i >= N_TX_RING)
 753         i -= N_TX_RING;
 754     if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
 755         do {
 756             /* set up the next one */
 757             cp = mp->tx_cmds + NCMDS_TX * i;
 758             out_le16(&cp->xfer_status, 0);
 759             out_le16(&cp->command, OUTPUT_LAST);
 760             ++mp->tx_active;
 761             if (++i >= N_TX_RING)
 762                 i = 0;
 763         } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
 764         out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
 765         mace_set_timeout(dev);
 766     }
 767     spin_unlock_irqrestore(&mp->lock, flags);
 768     return IRQ_HANDLED;
 769 }
 770
 771 static void mace_tx_timeout(unsigned long data)
 772 {
 773     struct net_device *dev = (struct net_device *) data;
 774     struct mace_data *mp = (struct mace_data *) dev->priv;
 775     volatile struct mace *mb = mp->mace;
 776     volatile struct dbdma_regs *td = mp->tx_dma;
 777     volatile struct dbdma_regs *rd = mp->rx_dma;
 778     volatile struct dbdma_cmd *cp;
 779     unsigned long flags;
 780     int i;
 781
 782     spin_lock_irqsave(&mp->lock, flags);
 783     mp->timeout_active = 0;
 784     if (mp->tx_active == 0 && !mp->tx_bad_runt)
 785         goto out;
 786
 787     /* update various counters */
 788     mace_handle_misc_intrs(mp, in_8(&mb->ir));
 789
 790     cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
 791
 792     /* turn off both tx and rx and reset the chip */
 793     out_8(&mb->maccc, 0);
 794     printk(KERN_ERR "mace: transmit timeout - resetting\n");
 795     dbdma_reset(td);
 796     mace_reset(dev);
 797
 798     /* restart rx dma */
 799     cp = bus_to_virt(ld_le32(&rd->cmdptr));
 800     dbdma_reset(rd);
 801     out_le16(&cp->xfer_status, 0);
 802     out_le32(&rd->cmdptr, virt_to_bus(cp));
 803     out_le32(&rd->control, (RUN << 16) | RUN);
 804
 805     /* fix up the transmit side */
 806     i = mp->tx_empty;
 807     mp->tx_active = 0;
 808     ++mp->stats.tx_errors;
 809     if (mp->tx_bad_runt) {
 810         mp->tx_bad_runt = 0;
 811     } else if (i != mp->tx_fill) {
 812         dev_kfree_skb(mp->tx_bufs[i]);
 813         if (++i >= N_TX_RING)
 814             i = 0;
 815         mp->tx_empty = i;
 816     }
 817     mp->tx_fullup = 0;
 818     netif_wake_queue(dev);
 819     if (i != mp->tx_fill) {
 820         cp = mp->tx_cmds + NCMDS_TX * i;
 821         out_le16(&cp->xfer_status, 0);
 822         out_le16(&cp->command, OUTPUT_LAST);
 823         out_le32(&td->cmdptr, virt_to_bus(cp));
 824         out_le32(&td->control, (RUN << 16) | RUN);
 825         ++mp->tx_active;
 826         mace_set_timeout(dev);
 827     }
 828
 829     /* turn it back on */
 830     out_8(&mb->imr, RCVINT);
 831     out_8(&mb->maccc, mp->maccc);
 832
 833 out:
 834     spin_unlock_irqrestore(&mp->lock, flags);
 835 }
 836
 837 static irqreturn_t mace_txdma_intr(int irq, void *dev_id, struct pt_regs *regs)
 838 {
 839         return IRQ_HANDLED;
 840 }
 841
 842 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs)
 843 {
 844     struct net_device *dev = (struct net_device *) dev_id;
 845     struct mace_data *mp = (struct mace_data *) dev->priv;
 846     volatile struct dbdma_regs *rd = mp->rx_dma;
 847     volatile struct dbdma_cmd *cp, *np;
 848     int i, nb, stat, next;
 849     struct sk_buff *skb;
 850     unsigned frame_status;
 851     static int mace_lost_status;
 852     unsigned char *data;
 853     unsigned long flags;
 854
 855     spin_lock_irqsave(&mp->lock, flags);
 856     for (i = mp->rx_empty; i != mp->rx_fill; ) {
 857         cp = mp->rx_cmds + i;
 858         stat = ld_le16(&cp->xfer_status);
 859         if ((stat & ACTIVE) == 0) {
 860             next = i + 1;
 861             if (next >= N_RX_RING)
 862                 next = 0;
 863             np = mp->rx_cmds + next;
 864             if (next != mp->rx_fill
 865                 && (ld_le16(&np->xfer_status) & ACTIVE) != 0) {
 866                 printk(KERN_DEBUG "mace: lost a status word\n");
 867                 ++mace_lost_status;
 868             } else
 869                 break;
 870         }
 871         nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count);
 872         out_le16(&cp->command, DBDMA_STOP);
 873         /* got a packet, have a look at it */
 874         skb = mp->rx_bufs[i];
 875         if (skb == 0) {
 876             ++mp->stats.rx_dropped;
 877         } else if (nb > 8) {
 878             data = skb->data;
 879             frame_status = (data[nb-3] << 8) + data[nb-4];
 880             if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
 881                 ++mp->stats.rx_errors;
 882                 if (frame_status & RS_OFLO)
 883                     ++mp->stats.rx_over_errors;
 884                 if (frame_status & RS_FRAMERR)
 885                     ++mp->stats.rx_frame_errors;
 886                 if (frame_status & RS_FCSERR)
 887                     ++mp->stats.rx_crc_errors;
 888             } else {
 889                 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
 890                  * FCS on frames with 802.3 headers. This means that Ethernet
 891                  * frames have 8 extra octets at the end, while 802.3 frames
 892                  * have only 4. We need to correctly account for this. */
 893                 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
 894                     nb -= 4;
 895                 else    /* Ethernet header; mace includes FCS */
 896                     nb -= 8;
 897                 skb_put(skb, nb);
 898                 skb->dev = dev;
 899                 skb->protocol = eth_type_trans(skb, dev);
 900                 mp->stats.rx_bytes += skb->len;
 901                 netif_rx(skb);
 902                 dev->last_rx = jiffies;
 903                 mp->rx_bufs[i] = 0;
 904                 ++mp->stats.rx_packets;
 905             }
 906         } else {
 907             ++mp->stats.rx_errors;
 908             ++mp->stats.rx_length_errors;
 909         }
 910
 911         /* advance to next */
 912         if (++i >= N_RX_RING)
 913             i = 0;
 914     }
 915     mp->rx_empty = i;
 916
 917     i = mp->rx_fill;
 918     for (;;) {
 919         next = i + 1;
 920         if (next >= N_RX_RING)
 921             next = 0;
 922         if (next == mp->rx_empty)
 923             break;
 924         cp = mp->rx_cmds + i;
 925         skb = mp->rx_bufs[i];
 926         if (skb == 0) {
 927             skb = dev_alloc_skb(RX_BUFLEN + 2);
 928             if (skb != 0) {
 929                 skb_reserve(skb, 2);
 930                 mp->rx_bufs[i] = skb;
 931             }
 932         }
 933         st_le16(&cp->req_count, RX_BUFLEN);
 934         data = skb? skb->data: dummy_buf;
 935         st_le32(&cp->phy_addr, virt_to_bus(data));
 936         out_le16(&cp->xfer_status, 0);
 937         out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
 938 #if 0
 939         if ((ld_le32(&rd->status) & ACTIVE) != 0) {
 940             out_le32(&rd->control, (PAUSE << 16) | PAUSE);
 941             while ((in_le32(&rd->status) & ACTIVE) != 0)
 942                 ;
 943         }
 944 #endif
 945         i = next;
 946     }
 947     if (i != mp->rx_fill) {
 948         out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
 949         mp->rx_fill = i;
 950     }
 951     spin_unlock_irqrestore(&mp->lock, flags);
 952     return IRQ_HANDLED;
 953 }
 954
 955 MODULE_AUTHOR("Paul Mackerras");
 956 MODULE_DESCRIPTION("PowerMac MACE driver.");
 957 MODULE_PARM(port_aaui, "i");
 958 MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
 959 MODULE_LICENSE("GPL");
 960
 961 static void __exit mace_cleanup (void)
 962 {
 963     struct net_device *dev;
 964     struct mace_data *mp;
 965
 966     while ((dev = mace_devs) != 0) {
 967                 mp = (struct mace_data *) mace_devs->priv;
 968                 mace_devs = mp->next_mace;
 969
 970                 unregister_netdev(dev);
 971                 free_irq(dev->irq, dev);
 972                 free_irq(mp->tx_dma_intr, dev);
 973                 free_irq(mp->rx_dma_intr, dev);
 974
 975                 release_OF_resource(mp->of_node, 0);
 976                 release_OF_resource(mp->of_node, 1);
 977                 release_OF_resource(mp->of_node, 2);
 978
 979                 kfree(dev);
 980     }
 981     if (dummy_buf != NULL) {
 982                 kfree(dummy_buf);
 983                 dummy_buf = NULL;
 984     }
 985 }
 986
 987 module_init(mace_probe);
 988 module_exit(mace_cleanup);