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More meth updates.
[linux-2.6/linux-mips.git] / drivers / net / fealnx.c
blob4c5d647a526f09421bdc31402ef78b626c5d1084
1 /*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25 */
26
27 #define DRV_NAME "fealnx"
28 #define DRV_VERSION "2.51"
29 #define DRV_RELDATE "Nov-17-2001"
30
31 static int debug; /* 1-> print debug message */
32 static int max_interrupt_work = 20;
33
34 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35 static int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38 /* Setting to > 1518 effectively disables this feature. */
39 static int rx_copybreak;
40
41 /* Used to pass the media type, etc. */
42 /* Both 'options[]' and 'full_duplex[]' should exist for driver */
43 /* interoperability. */
44 /* The media type is usually passed in 'options[]'. */
45 #define MAX_UNITS 8 /* More are supported, limit only on options */
46 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49 /* Operational parameters that are set at compile time. */
50 /* Keep the ring sizes a power of two for compile efficiency. */
51 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52 /* Making the Tx ring too large decreases the effectiveness of channel */
53 /* bonding and packet priority. */
54 /* There are no ill effects from too-large receive rings. */
55 // 88-12-9 modify,
56 // #define TX_RING_SIZE 16
57 // #define RX_RING_SIZE 32
58 #define TX_RING_SIZE 6
59 #define RX_RING_SIZE 12
60 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63 /* Operational parameters that usually are not changed. */
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (2*HZ)
66
67 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70 /* Include files, designed to support most kernel versions 2.0.0 and later. */
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/slab.h>
78 #include <linux/interrupt.h>
79 #include <linux/pci.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/init.h>
84 #include <linux/mii.h>
85 #include <linux/ethtool.h>
86 #include <linux/crc32.h>
87
88 #include <asm/processor.h> /* Processor type for cache alignment. */
89 #include <asm/bitops.h>
90 #include <asm/io.h>
91 #include <asm/uaccess.h>
92
93 /* These identify the driver base version and may not be removed. */
94 static char version[] __devinitdata =
95 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
96
97
98 /* This driver was written to use PCI memory space, however some x86 systems
99 work only with I/O space accesses. */
100 #ifndef __alpha__
101 #define USE_IO_OPS
102 #endif
103
104 #ifdef USE_IO_OPS
105 #undef readb
106 #undef readw
107 #undef readl
108 #undef writeb
109 #undef writew
110 #undef writel
111 #define readb inb
112 #define readw inw
113 #define readl inl
114 #define writeb outb
115 #define writew outw
116 #define writel outl
117 #endif
118
119 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
120 /* This is only in the support-all-kernels source code. */
121
122 #define RUN_AT(x) (jiffies + (x))
123
124 MODULE_AUTHOR("Myson or whoever");
125 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
126 MODULE_LICENSE("GPL");
127 MODULE_PARM(max_interrupt_work, "i");
128 //MODULE_PARM(min_pci_latency, "i");
129 MODULE_PARM(debug, "i");
130 MODULE_PARM(rx_copybreak, "i");
131 MODULE_PARM(multicast_filter_limit, "i");
132 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
133 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
134 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
135 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
136 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
137 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
138 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
139 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
140
141 #define MIN_REGION_SIZE 136
142
143 enum pci_flags_bit {
144 PCI_USES_IO = 1,
145 PCI_USES_MEM = 2,
146 PCI_USES_MASTER = 4,
147 PCI_ADDR0 = 0x10 << 0,
148 PCI_ADDR1 = 0x10 << 1,
149 PCI_ADDR2 = 0x10 << 2,
150 PCI_ADDR3 = 0x10 << 3,
151 };
152
153 /* A chip capabilities table, matching the entries in pci_tbl[] above. */
154 enum chip_capability_flags {
155 HAS_MII_XCVR,
156 HAS_CHIP_XCVR,
157 };
158
159 /* 89/6/13 add, */
160 /* for different PHY */
161 enum phy_type_flags {
162 MysonPHY = 1,
163 AhdocPHY = 2,
164 SeeqPHY = 3,
165 MarvellPHY = 4,
166 Myson981 = 5,
167 LevelOnePHY = 6,
168 OtherPHY = 10,
169 };
170
171 struct chip_info {
172 char *chip_name;
173 int io_size;
174 int flags;
175 };
176
177 static struct chip_info skel_netdrv_tbl[] = {
178 {"100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
179 {"100/10M Ethernet PCI Adapter", 136, HAS_CHIP_XCVR},
180 {"1000/100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
181 };
182
183 /* Offsets to the Command and Status Registers. */
184 enum fealnx_offsets {
185 PAR0 = 0x0, /* physical address 0-3 */
186 PAR1 = 0x04, /* physical address 4-5 */
187 MAR0 = 0x08, /* multicast address 0-3 */
188 MAR1 = 0x0C, /* multicast address 4-7 */
189 FAR0 = 0x10, /* flow-control address 0-3 */
190 FAR1 = 0x14, /* flow-control address 4-5 */
191 TCRRCR = 0x18, /* receive & transmit configuration */
192 BCR = 0x1C, /* bus command */
193 TXPDR = 0x20, /* transmit polling demand */
194 RXPDR = 0x24, /* receive polling demand */
195 RXCWP = 0x28, /* receive current word pointer */
196 TXLBA = 0x2C, /* transmit list base address */
197 RXLBA = 0x30, /* receive list base address */
198 ISR = 0x34, /* interrupt status */
199 IMR = 0x38, /* interrupt mask */
200 FTH = 0x3C, /* flow control high/low threshold */
201 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
202 TALLY = 0x44, /* tally counters for crc and mpa */
203 TSR = 0x48, /* tally counter for transmit status */
204 BMCRSR = 0x4c, /* basic mode control and status */
205 PHYIDENTIFIER = 0x50, /* phy identifier */
206 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
207 partner ability */
208 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
209 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
210 };
211
212 /* Bits in the interrupt status/enable registers. */
213 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
214 enum intr_status_bits {
215 RFCON = 0x00020000, /* receive flow control xon packet */
216 RFCOFF = 0x00010000, /* receive flow control xoff packet */
217 LSCStatus = 0x00008000, /* link status change */
218 ANCStatus = 0x00004000, /* autonegotiation completed */
219 FBE = 0x00002000, /* fatal bus error */
220 FBEMask = 0x00001800, /* mask bit12-11 */
221 ParityErr = 0x00000000, /* parity error */
222 TargetErr = 0x00001000, /* target abort */
223 MasterErr = 0x00000800, /* master error */
224 TUNF = 0x00000400, /* transmit underflow */
225 ROVF = 0x00000200, /* receive overflow */
226 ETI = 0x00000100, /* transmit early int */
227 ERI = 0x00000080, /* receive early int */
228 CNTOVF = 0x00000040, /* counter overflow */
229 RBU = 0x00000020, /* receive buffer unavailable */
230 TBU = 0x00000010, /* transmit buffer unavilable */
231 TI = 0x00000008, /* transmit interrupt */
232 RI = 0x00000004, /* receive interrupt */
233 RxErr = 0x00000002, /* receive error */
234 };
235
236 /* Bits in the NetworkConfig register. */
237 enum rx_mode_bits {
238 RxModeMask = 0xe0,
239 PROM = 0x80, /* promiscuous mode */
240 AB = 0x40, /* accept broadcast */
241 AM = 0x20, /* accept mutlicast */
242 ARP = 0x08, /* receive runt pkt */
243 ALP = 0x04, /* receive long pkt */
244 SEP = 0x02, /* receive error pkt */
245 };
246
247 /* The Tulip Rx and Tx buffer descriptors. */
248 struct fealnx_desc {
249 s32 status;
250 s32 control;
251 u32 buffer;
252 u32 next_desc;
253 struct fealnx_desc *next_desc_logical;
254 struct sk_buff *skbuff;
255 u32 reserved1;
256 u32 reserved2;
257 };
258
259 /* Bits in network_desc.status */
260 enum rx_desc_status_bits {
261 RXOWN = 0x80000000, /* own bit */
262 FLNGMASK = 0x0fff0000, /* frame length */
263 FLNGShift = 16,
264 MARSTATUS = 0x00004000, /* multicast address received */
265 BARSTATUS = 0x00002000, /* broadcast address received */
266 PHYSTATUS = 0x00001000, /* physical address received */
267 RXFSD = 0x00000800, /* first descriptor */
268 RXLSD = 0x00000400, /* last descriptor */
269 ErrorSummary = 0x80, /* error summary */
270 RUNT = 0x40, /* runt packet received */
271 LONG = 0x20, /* long packet received */
272 FAE = 0x10, /* frame align error */
273 CRC = 0x08, /* crc error */
274 RXER = 0x04, /* receive error */
275 };
276
277 enum rx_desc_control_bits {
278 RXIC = 0x00800000, /* interrupt control */
279 RBSShift = 0,
280 };
281
282 enum tx_desc_status_bits {
283 TXOWN = 0x80000000, /* own bit */
284 JABTO = 0x00004000, /* jabber timeout */
285 CSL = 0x00002000, /* carrier sense lost */
286 LC = 0x00001000, /* late collision */
287 EC = 0x00000800, /* excessive collision */
288 UDF = 0x00000400, /* fifo underflow */
289 DFR = 0x00000200, /* deferred */
290 HF = 0x00000100, /* heartbeat fail */
291 NCRMask = 0x000000ff, /* collision retry count */
292 NCRShift = 0,
293 };
294
295 enum tx_desc_control_bits {
296 TXIC = 0x80000000, /* interrupt control */
297 ETIControl = 0x40000000, /* early transmit interrupt */
298 TXLD = 0x20000000, /* last descriptor */
299 TXFD = 0x10000000, /* first descriptor */
300 CRCEnable = 0x08000000, /* crc control */
301 PADEnable = 0x04000000, /* padding control */
302 RetryTxLC = 0x02000000, /* retry late collision */
303 PKTSMask = 0x3ff800, /* packet size bit21-11 */
304 PKTSShift = 11,
305 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
306 TBSShift = 0,
307 };
308
309 /* BootROM/EEPROM/MII Management Register */
310 #define MASK_MIIR_MII_READ 0x00000000
311 #define MASK_MIIR_MII_WRITE 0x00000008
312 #define MASK_MIIR_MII_MDO 0x00000004
313 #define MASK_MIIR_MII_MDI 0x00000002
314 #define MASK_MIIR_MII_MDC 0x00000001
315
316 /* ST+OP+PHYAD+REGAD+TA */
317 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
318 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
319
320 /* ------------------------------------------------------------------------- */
321 /* Constants for Myson PHY */
322 /* ------------------------------------------------------------------------- */
323 #define MysonPHYID 0xd0000302
324 /* 89-7-27 add, (begin) */
325 #define MysonPHYID0 0x0302
326 #define StatusRegister 18
327 #define SPEED100 0x0400 // bit10
328 #define FULLMODE 0x0800 // bit11
329 /* 89-7-27 add, (end) */
330
331 /* ------------------------------------------------------------------------- */
332 /* Constants for Seeq 80225 PHY */
333 /* ------------------------------------------------------------------------- */
334 #define SeeqPHYID0 0x0016
335
336 #define MIIRegister18 18
337 #define SPD_DET_100 0x80
338 #define DPLX_DET_FULL 0x40
339
340 /* ------------------------------------------------------------------------- */
341 /* Constants for Ahdoc 101 PHY */
342 /* ------------------------------------------------------------------------- */
343 #define AhdocPHYID0 0x0022
344
345 #define DiagnosticReg 18
346 #define DPLX_FULL 0x0800
347 #define Speed_100 0x0400
348
349 /* 89/6/13 add, */
350 /* -------------------------------------------------------------------------- */
351 /* Constants */
352 /* -------------------------------------------------------------------------- */
353 #define MarvellPHYID0 0x0141
354 #define LevelOnePHYID0 0x0013
355
356 #define MII1000BaseTControlReg 9
357 #define MII1000BaseTStatusReg 10
358 #define SpecificReg 17
359
360 /* for 1000BaseT Control Register */
361 #define PHYAbletoPerform1000FullDuplex 0x0200
362 #define PHYAbletoPerform1000HalfDuplex 0x0100
363 #define PHY1000AbilityMask 0x300
364
365 // for phy specific status register, marvell phy.
366 #define SpeedMask 0x0c000
367 #define Speed_1000M 0x08000
368 #define Speed_100M 0x4000
369 #define Speed_10M 0
370 #define Full_Duplex 0x2000
371
372 // 89/12/29 add, for phy specific status register, levelone phy, (begin)
373 #define LXT1000_100M 0x08000
374 #define LXT1000_1000M 0x0c000
375 #define LXT1000_Full 0x200
376 // 89/12/29 add, for phy specific status register, levelone phy, (end)
377
378 /* for 3-in-1 case */
379 #define PS10 0x00080000
380 #define FD 0x00100000
381 #define PS1000 0x00010000
382 #define LinkIsUp2 0x00040000
383
384 /* for PHY */
385 #define LinkIsUp 0x0004
386
387
388 struct netdev_private {
389 /* Descriptor rings first for alignment. */
390 struct fealnx_desc *rx_ring;
391 struct fealnx_desc *tx_ring;
392
393 dma_addr_t rx_ring_dma;
394 dma_addr_t tx_ring_dma;
395
396 spinlock_t lock;
397
398 struct net_device_stats stats;
399
400 /* Media monitoring timer. */
401 struct timer_list timer;
402
403 /* Frequently used values: keep some adjacent for cache effect. */
404 int flags;
405 struct pci_dev *pci_dev;
406 unsigned long crvalue;
407 unsigned long bcrvalue;
408 unsigned long imrvalue;
409 struct fealnx_desc *cur_rx;
410 struct fealnx_desc *lack_rxbuf;
411 int really_rx_count;
412 struct fealnx_desc *cur_tx;
413 struct fealnx_desc *cur_tx_copy;
414 int really_tx_count;
415 int free_tx_count;
416 unsigned int rx_buf_sz; /* Based on MTU+slack. */
417
418 /* These values are keep track of the transceiver/media in use. */
419 unsigned int linkok;
420 unsigned int line_speed;
421 unsigned int duplexmode;
422 unsigned int default_port:4; /* Last dev->if_port value. */
423 unsigned int PHYType;
424
425 /* MII transceiver section. */
426 int mii_cnt; /* MII device addresses. */
427 unsigned char phys[2]; /* MII device addresses. */
428 struct mii_if_info mii;
429 };
430
431
432 static int mdio_read(struct net_device *dev, int phy_id, int location);
433 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
434 static int netdev_open(struct net_device *dev);
435 static void getlinktype(struct net_device *dev);
436 static void getlinkstatus(struct net_device *dev);
437 static void netdev_timer(unsigned long data);
438 static void tx_timeout(struct net_device *dev);
439 static void init_ring(struct net_device *dev);
440 static int start_tx(struct sk_buff *skb, struct net_device *dev);
441 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
442 static int netdev_rx(struct net_device *dev);
443 static void set_rx_mode(struct net_device *dev);
444 static struct net_device_stats *get_stats(struct net_device *dev);
445 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
446 static int netdev_close(struct net_device *dev);
447 static void reset_rx_descriptors(struct net_device *dev);
448
449 void stop_nic_tx(long ioaddr, long crvalue)
450 {
451 writel(crvalue & (~0x40000), ioaddr + TCRRCR);
452
453 /* wait for tx stop */
454 {
455 int i = 0, delay = 0x1000;
456
457 while ((!(readl(ioaddr + TCRRCR) & 0x04000000)) && (i < delay)) {
458 ++i;
459 }
460 }
461 }
462
463
464 void stop_nic_rx(long ioaddr, long crvalue)
465 {
466 writel(crvalue & (~0x1), ioaddr + TCRRCR);
467
468 /* wait for rx stop */
469 {
470 int i = 0, delay = 0x1000;
471
472 while ((!(readl(ioaddr + TCRRCR) & 0x00008000)) && (i < delay)) {
473 ++i;
474 }
475 }
476 }
477
478
479
480 static int __devinit fealnx_init_one(struct pci_dev *pdev,
481 const struct pci_device_id *ent)
482 {
483 struct netdev_private *np;
484 int i, option, err, irq;
485 static int card_idx = -1;
486 char boardname[12];
487 long ioaddr;
488 unsigned int chip_id = ent->driver_data;
489 struct net_device *dev;
490 void *ring_space;
491 dma_addr_t ring_dma;
492
493 /* when built into the kernel, we only print version if device is found */
494 #ifndef MODULE
495 static int printed_version;
496 if (!printed_version++)
497 printk (version);
498 #endif
499
500 card_idx++;
501 sprintf(boardname, "fealnx%d", card_idx);
502
503 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
504
505 i = pci_enable_device(pdev);
506 if (i) return i;
507 pci_set_master(pdev);
508
509 #ifdef USE_IO_OPS
510 ioaddr = pci_resource_len(pdev, 0);
511 #else
512 ioaddr = pci_resource_len(pdev, 1);
513 #endif
514 if (ioaddr < MIN_REGION_SIZE) {
515 printk(KERN_ERR "%s: region size %ld too small, aborting\n",
516 boardname, ioaddr);
517 return -ENODEV;
518 }
519
520 i = pci_request_regions(pdev, boardname);
521 if (i) return i;
522
523 irq = pdev->irq;
524
525 #ifdef USE_IO_OPS
526 ioaddr = pci_resource_start(pdev, 0);
527 #else
528 ioaddr = (long) ioremap(pci_resource_start(pdev, 1),
529 pci_resource_len(pdev, 1));
530 if (!ioaddr) {
531 err = -ENOMEM;
532 goto err_out_res;
533 }
534 #endif
535
536 dev = alloc_etherdev(sizeof(struct netdev_private));
537 if (!dev) {
538 err = -ENOMEM;
539 goto err_out_unmap;
540 }
541 SET_MODULE_OWNER(dev);
542 SET_NETDEV_DEV(dev, &pdev->dev);
543
544 /* read ethernet id */
545 for (i = 0; i < 6; ++i)
546 dev->dev_addr[i] = readb(ioaddr + PAR0 + i);
547
548 /* Reset the chip to erase previous misconfiguration. */
549 writel(0x00000001, ioaddr + BCR);
550
551 dev->base_addr = ioaddr;
552 dev->irq = irq;
553
554 /* Make certain the descriptor lists are aligned. */
555 np = dev->priv;
556 spin_lock_init(&np->lock);
557 np->pci_dev = pdev;
558 np->flags = skel_netdrv_tbl[chip_id].flags;
559 pci_set_drvdata(pdev, dev);
560 np->mii.dev = dev;
561 np->mii.mdio_read = mdio_read;
562 np->mii.mdio_write = mdio_write;
563 np->mii.phy_id_mask = 0x1f;
564 np->mii.reg_num_mask = 0x1f;
565
566 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
567 if (!ring_space) {
568 err = -ENOMEM;
569 goto err_out_free_dev;
570 }
571 np->rx_ring = (struct fealnx_desc *)ring_space;
572 np->rx_ring_dma = ring_dma;
573
574 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
575 if (!ring_space) {
576 err = -ENOMEM;
577 goto err_out_free_rx;
578 }
579 np->tx_ring = (struct fealnx_desc *)ring_space;
580 np->tx_ring_dma = ring_dma;
581
582 /* find the connected MII xcvrs */
583 if (np->flags == HAS_MII_XCVR) {
584 int phy, phy_idx = 0;
585
586 for (phy = 1; phy < 32 && phy_idx < 4; phy++) {
587 int mii_status = mdio_read(dev, phy, 1);
588
589 if (mii_status != 0xffff && mii_status != 0x0000) {
590 np->phys[phy_idx++] = phy;
591 printk(KERN_INFO
592 "%s: MII PHY found at address %d, status "
593 "0x%4.4x.\n", dev->name, phy, mii_status);
594 /* get phy type */
595 {
596 unsigned int data;
597
598 data = mdio_read(dev, np->phys[0], 2);
599 if (data == SeeqPHYID0)
600 np->PHYType = SeeqPHY;
601 else if (data == AhdocPHYID0)
602 np->PHYType = AhdocPHY;
603 else if (data == MarvellPHYID0)
604 np->PHYType = MarvellPHY;
605 else if (data == MysonPHYID0)
606 np->PHYType = Myson981;
607 else if (data == LevelOnePHYID0)
608 np->PHYType = LevelOnePHY;
609 else
610 np->PHYType = OtherPHY;
611 }
612 }
613 }
614
615 np->mii_cnt = phy_idx;
616 if (phy_idx == 0) {
617 printk(KERN_WARNING "%s: MII PHY not found -- this device may "
618 "not operate correctly.\n", dev->name);
619 }
620 } else {
621 np->phys[0] = 32;
622 /* 89/6/23 add, (begin) */
623 /* get phy type */
624 if (readl(dev->base_addr + PHYIDENTIFIER) == MysonPHYID)
625 np->PHYType = MysonPHY;
626 else
627 np->PHYType = OtherPHY;
628 }
629 np->mii.phy_id = np->phys[0];
630
631 if (dev->mem_start)
632 option = dev->mem_start;
633
634 /* The lower four bits are the media type. */
635 if (option > 0) {
636 if (option & 0x200)
637 np->mii.full_duplex = 1;
638 np->default_port = option & 15;
639 }
640
641 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
642 np->mii.full_duplex = full_duplex[card_idx];
643
644 if (np->mii.full_duplex) {
645 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
646 /* 89/6/13 add, (begin) */
647 // if (np->PHYType==MarvellPHY)
648 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
649 unsigned int data;
650
651 data = mdio_read(dev, np->phys[0], 9);
652 data = (data & 0xfcff) | 0x0200;
653 mdio_write(dev, np->phys[0], 9, data);
654 }
655 /* 89/6/13 add, (end) */
656 if (np->flags == HAS_MII_XCVR)
657 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
658 else
659 writel(ADVERTISE_FULL, dev->base_addr + ANARANLPAR);
660 np->mii.force_media = 1;
661 }
662
663 /* The chip-specific entries in the device structure. */
664 dev->open = &netdev_open;
665 dev->hard_start_xmit = &start_tx;
666 dev->stop = &netdev_close;
667 dev->get_stats = &get_stats;
668 dev->set_multicast_list = &set_rx_mode;
669 dev->do_ioctl = &mii_ioctl;
670 dev->tx_timeout = tx_timeout;
671 dev->watchdog_timeo = TX_TIMEOUT;
672
673 err = register_netdev(dev);
674 if (err)
675 goto err_out_free_tx;
676
677 printk(KERN_INFO "%s: %s at 0x%lx, ",
678 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr);
679 for (i = 0; i < 5; i++)
680 printk("%2.2x:", dev->dev_addr[i]);
681 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
682
683 return 0;
684
685 err_out_free_tx:
686 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
687 err_out_free_rx:
688 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
689 err_out_free_dev:
690 kfree(dev);
691 err_out_unmap:
692 #ifndef USE_IO_OPS
693 iounmap((void *)ioaddr);
694 err_out_res:
695 #endif
696 pci_release_regions(pdev);
697 return err;
698 }
699
700 static void __devexit fealnx_remove_one(struct pci_dev *pdev)
701 {
702 struct net_device *dev = pci_get_drvdata(pdev);
703
704 if (dev) {
705 struct netdev_private *np = dev->priv;
706
707 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
708 np->tx_ring_dma);
709 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
710 np->rx_ring_dma);
711 unregister_netdev(dev);
712 #ifndef USE_IO_OPS
713 iounmap((void *)dev->base_addr);
714 #endif
715 kfree(dev);
716 pci_release_regions(pdev);
717 pci_set_drvdata(pdev, NULL);
718 } else
719 printk(KERN_ERR "fealnx: remove for unknown device\n");
720 }
721
722 unsigned int m80x_read_tick(void)
723 /* function: Reads the Timer tick count register which decrements by 2 from */
724 /* 65536 to 0 every 1/36.414 of a second. Each 2 decrements of the *//* count represents 838 nsec's. */
725 /* input : none. */
726 /* output : none. */
727 {
728 unsigned char tmp;
729 int value;
730
731 writeb((char) 0x06, 0x43); // Command 8254 to latch T0's count
732
733 // now read the count.
734 tmp = (unsigned char) readb(0x40);
735 value = ((int) tmp) << 8;
736 tmp = (unsigned char) readb(0x40);
737 value |= (((int) tmp) & 0xff);
738 return (value);
739 }
740
741
742 void m80x_delay(unsigned int interval)
743 /* function: to wait for a specified time. */
744 /* input : interval ... the specified time. */
745 /* output : none. */
746 {
747 unsigned int interval1, interval2, i = 0;
748
749 interval1 = m80x_read_tick(); // get initial value
750 do {
751 interval2 = m80x_read_tick();
752 if (interval1 < interval2)
753 interval1 = interval2;
754 ++i;
755 } while (((interval1 - interval2) < (ushort) interval) && (i < 65535));
756 }
757
758
759 static ulong m80x_send_cmd_to_phy(long miiport, int opcode, int phyad, int regad)
760 {
761 ulong miir;
762 int i;
763 unsigned int mask, data;
764
765 /* enable MII output */
766 miir = (ulong) readl(miiport);
767 miir &= 0xfffffff0;
768
769 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
770
771 /* send 32 1's preamble */
772 for (i = 0; i < 32; i++) {
773 /* low MDC; MDO is already high (miir) */
774 miir &= ~MASK_MIIR_MII_MDC;
775 writel(miir, miiport);
776
777 /* high MDC */
778 miir |= MASK_MIIR_MII_MDC;
779 writel(miir, miiport);
780 }
781
782 /* calculate ST+OP+PHYAD+REGAD+TA */
783 data = opcode | (phyad << 7) | (regad << 2);
784
785 /* sent out */
786 mask = 0x8000;
787 while (mask) {
788 /* low MDC, prepare MDO */
789 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
790 if (mask & data)
791 miir |= MASK_MIIR_MII_MDO;
792
793 writel(miir, miiport);
794 /* high MDC */
795 miir |= MASK_MIIR_MII_MDC;
796 writel(miir, miiport);
797 m80x_delay(30);
798
799 /* next */
800 mask >>= 1;
801 if (mask == 0x2 && opcode == OP_READ)
802 miir &= ~MASK_MIIR_MII_WRITE;
803 }
804 return miir;
805 }
806
807
808 static int mdio_read(struct net_device *dev, int phyad, int regad)
809 {
810 long miiport = dev->base_addr + MANAGEMENT;
811 ulong miir;
812 unsigned int mask, data;
813
814 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
815
816 /* read data */
817 mask = 0x8000;
818 data = 0;
819 while (mask) {
820 /* low MDC */
821 miir &= ~MASK_MIIR_MII_MDC;
822 writel(miir, miiport);
823
824 /* read MDI */
825 miir = readl(miiport);
826 if (miir & MASK_MIIR_MII_MDI)
827 data |= mask;
828
829 /* high MDC, and wait */
830 miir |= MASK_MIIR_MII_MDC;
831 writel(miir, miiport);
832 m80x_delay((int) 30);
833
834 /* next */
835 mask >>= 1;
836 }
837
838 /* low MDC */
839 miir &= ~MASK_MIIR_MII_MDC;
840 writel(miir, miiport);
841
842 return data & 0xffff;
843 }
844
845
846 static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
847 {
848 long miiport = dev->base_addr + MANAGEMENT;
849 ulong miir;
850 unsigned int mask;
851
852 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
853
854 /* write data */
855 mask = 0x8000;
856 while (mask) {
857 /* low MDC, prepare MDO */
858 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
859 if (mask & data)
860 miir |= MASK_MIIR_MII_MDO;
861 writel(miir, miiport);
862
863 /* high MDC */
864 miir |= MASK_MIIR_MII_MDC;
865 writel(miir, miiport);
866
867 /* next */
868 mask >>= 1;
869 }
870
871 /* low MDC */
872 miir &= ~MASK_MIIR_MII_MDC;
873 writel(miir, miiport);
874
875 return;
876 }
877
878
879 static int netdev_open(struct net_device *dev)
880 {
881 struct netdev_private *np = dev->priv;
882 long ioaddr = dev->base_addr;
883
884 writel(0x00000001, ioaddr + BCR); /* Reset */
885
886 if (request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev))
887 return -EAGAIN;
888
889 init_ring(dev);
890
891 writel(np->rx_ring_dma, ioaddr + RXLBA);
892 writel(np->tx_ring_dma, ioaddr + TXLBA);
893
894 /* Initialize other registers. */
895 /* Configure the PCI bus bursts and FIFO thresholds.
896 486: Set 8 longword burst.
897 586: no burst limit.
898 Burst length 5:3
899 0 0 0 1
900 0 0 1 4
901 0 1 0 8
902 0 1 1 16
903 1 0 0 32
904 1 0 1 64
905 1 1 0 128
906 1 1 1 256
907 Wait the specified 50 PCI cycles after a reset by initializing
908 Tx and Rx queues and the address filter list.
909 FIXME (Ueimor): optimistic for alpha + posted writes ? */
910 #if defined(__powerpc__) || defined(__sparc__)
911 // 89/9/1 modify,
912 // np->bcrvalue=0x04 | 0x0x38; /* big-endian, 256 burst length */
913 np->bcrvalue = 0x04 | 0x10; /* big-endian, tx 8 burst length */
914 np->crvalue = 0xe00; /* rx 128 burst length */
915 #elif defined(__alpha__) || defined(__x86_64__)
916 // 89/9/1 modify,
917 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
918 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
919 np->crvalue = 0xe00; /* rx 128 burst length */
920 #elif defined(__i386__)
921 #if defined(MODULE)
922 // 89/9/1 modify,
923 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
924 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
925 np->crvalue = 0xe00; /* rx 128 burst length */
926 #else
927 /* When not a module we can work around broken '486 PCI boards. */
928 #define x86 boot_cpu_data.x86
929 // 89/9/1 modify,
930 // np->bcrvalue=(x86 <= 4 ? 0x10 : 0x38);
931 np->bcrvalue = 0x10;
932 np->crvalue = (x86 <= 4 ? 0xa00 : 0xe00);
933 if (x86 <= 4)
934 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting burst "
935 "length to %x.\n", dev->name, (x86 <= 4 ? 0x10 : 0x38));
936 #endif
937 #else
938 // 89/9/1 modify,
939 // np->bcrvalue=0x38;
940 np->bcrvalue = 0x10;
941 np->cralue = 0xe00; /* rx 128 burst length */
942 #warning Processor architecture undefined!
943 #endif
944 // 89/12/29 add,
945 // 90/1/16 modify,
946 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
947 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
948 if (np->pci_dev->device == 0x891) {
949 np->bcrvalue |= 0x200; /* set PROG bit */
950 np->crvalue |= 0x02000000; /* set enhanced bit */
951 np->imrvalue |= ETI;
952 }
953 writel(np->bcrvalue, ioaddr + BCR);
954
955 if (dev->if_port == 0)
956 dev->if_port = np->default_port;
957
958 writel(0, dev->base_addr + RXPDR);
959 // 89/9/1 modify,
960 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
961 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
962 np->mii.full_duplex = np->mii.force_media;
963 getlinkstatus(dev);
964 if (np->linkok)
965 getlinktype(dev);
966 set_rx_mode(dev);
967
968 netif_start_queue(dev);
969
970 /* Clear and Enable interrupts by setting the interrupt mask. */
971 writel(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
972 writel(np->imrvalue, ioaddr + IMR);
973
974 if (debug)
975 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
976
977 /* Set the timer to check for link beat. */
978 init_timer(&np->timer);
979 np->timer.expires = RUN_AT(3 * HZ);
980 np->timer.data = (unsigned long) dev;
981 np->timer.function = &netdev_timer;
982
983 /* timer handler */
984 add_timer(&np->timer);
985
986 return 0;
987 }
988
989
990 static void getlinkstatus(struct net_device *dev)
991 /* function: Routine will read MII Status Register to get link status. */
992 /* input : dev... pointer to the adapter block. */
993 /* output : none. */
994 {
995 struct netdev_private *np = dev->priv;
996 unsigned int i, DelayTime = 0x1000;
997
998 np->linkok = 0;
999
1000 if (np->PHYType == MysonPHY) {
1001 for (i = 0; i < DelayTime; ++i) {
1002 if (readl(dev->base_addr + BMCRSR) & LinkIsUp2) {
1003 np->linkok = 1;
1004 return;
1005 }
1006 // delay
1007 m80x_delay(100);
1008 }
1009 } else {
1010 for (i = 0; i < DelayTime; ++i) {
1011 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
1012 np->linkok = 1;
1013 return;
1014 }
1015 // delay
1016 m80x_delay(100);
1017 }
1018 }
1019 }
1020
1021
1022 static void getlinktype(struct net_device *dev)
1023 {
1024 struct netdev_private *np = dev->priv;
1025
1026 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
1027 if (readl(dev->base_addr + TCRRCR) & FD)
1028 np->duplexmode = 2; /* full duplex */
1029 else
1030 np->duplexmode = 1; /* half duplex */
1031 if (readl(dev->base_addr + TCRRCR) & PS10)
1032 np->line_speed = 1; /* 10M */
1033 else
1034 np->line_speed = 2; /* 100M */
1035 } else {
1036 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
1037 unsigned int data;
1038
1039 data = mdio_read(dev, np->phys[0], MIIRegister18);
1040 if (data & SPD_DET_100)
1041 np->line_speed = 2; /* 100M */
1042 else
1043 np->line_speed = 1; /* 10M */
1044 if (data & DPLX_DET_FULL)
1045 np->duplexmode = 2; /* full duplex mode */
1046 else
1047 np->duplexmode = 1; /* half duplex mode */
1048 } else if (np->PHYType == AhdocPHY) {
1049 unsigned int data;
1050
1051 data = mdio_read(dev, np->phys[0], DiagnosticReg);
1052 if (data & Speed_100)
1053 np->line_speed = 2; /* 100M */
1054 else
1055 np->line_speed = 1; /* 10M */
1056 if (data & DPLX_FULL)
1057 np->duplexmode = 2; /* full duplex mode */
1058 else
1059 np->duplexmode = 1; /* half duplex mode */
1060 }
1061 /* 89/6/13 add, (begin) */
1062 else if (np->PHYType == MarvellPHY) {
1063 unsigned int data;
1064
1065 data = mdio_read(dev, np->phys[0], SpecificReg);
1066 if (data & Full_Duplex)
1067 np->duplexmode = 2; /* full duplex mode */
1068 else
1069 np->duplexmode = 1; /* half duplex mode */
1070 data &= SpeedMask;
1071 if (data == Speed_1000M)
1072 np->line_speed = 3; /* 1000M */
1073 else if (data == Speed_100M)
1074 np->line_speed = 2; /* 100M */
1075 else
1076 np->line_speed = 1; /* 10M */
1077 }
1078 /* 89/6/13 add, (end) */
1079 /* 89/7/27 add, (begin) */
1080 else if (np->PHYType == Myson981) {
1081 unsigned int data;
1082
1083 data = mdio_read(dev, np->phys[0], StatusRegister);
1084
1085 if (data & SPEED100)
1086 np->line_speed = 2;
1087 else
1088 np->line_speed = 1;
1089
1090 if (data & FULLMODE)
1091 np->duplexmode = 2;
1092 else
1093 np->duplexmode = 1;
1094 }
1095 /* 89/7/27 add, (end) */
1096 /* 89/12/29 add */
1097 else if (np->PHYType == LevelOnePHY) {
1098 unsigned int data;
1099
1100 data = mdio_read(dev, np->phys[0], SpecificReg);
1101 if (data & LXT1000_Full)
1102 np->duplexmode = 2; /* full duplex mode */
1103 else
1104 np->duplexmode = 1; /* half duplex mode */
1105 data &= SpeedMask;
1106 if (data == LXT1000_1000M)
1107 np->line_speed = 3; /* 1000M */
1108 else if (data == LXT1000_100M)
1109 np->line_speed = 2; /* 100M */
1110 else
1111 np->line_speed = 1; /* 10M */
1112 }
1113 // chage crvalue
1114 // np->crvalue&=(~PS10)&(~FD);
1115 np->crvalue &= (~PS10) & (~FD) & (~PS1000);
1116 if (np->line_speed == 1)
1117 np->crvalue |= PS10;
1118 else if (np->line_speed == 3)
1119 np->crvalue |= PS1000;
1120 if (np->duplexmode == 2)
1121 np->crvalue |= FD;
1122 }
1123 }
1124
1125
1126 static void allocate_rx_buffers(struct net_device *dev)
1127 {
1128 struct netdev_private *np = dev->priv;
1129
1130 /* allocate skb for rx buffers */
1131 while (np->really_rx_count != RX_RING_SIZE) {
1132 struct sk_buff *skb;
1133
1134 skb = dev_alloc_skb(np->rx_buf_sz);
1135 np->lack_rxbuf->skbuff = skb;
1136
1137 if (skb == NULL)
1138 break; /* Better luck next round. */
1139
1140 skb->dev = dev; /* Mark as being used by this device. */
1141 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->tail,
1142 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1143 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1144 ++np->really_rx_count;
1145 }
1146 }
1147
1148
1149 static void netdev_timer(unsigned long data)
1150 {
1151 struct net_device *dev = (struct net_device *) data;
1152 struct netdev_private *np = dev->priv;
1153 long ioaddr = dev->base_addr;
1154 int next_tick = 10 * HZ;
1155 int old_crvalue = np->crvalue;
1156 unsigned int old_linkok = np->linkok;
1157
1158 if (debug)
1159 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1160 "config %8.8x.\n", dev->name, readl(ioaddr + ISR),
1161 readl(ioaddr + TCRRCR));
1162
1163 if (np->flags == HAS_MII_XCVR) {
1164 getlinkstatus(dev);
1165 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1166 getlinktype(dev);
1167 if (np->crvalue != old_crvalue) {
1168 stop_nic_tx(ioaddr, np->crvalue);
1169 stop_nic_rx(ioaddr, np->crvalue & (~0x40000));
1170 writel(np->crvalue, ioaddr + TCRRCR);
1171 }
1172 }
1173 }
1174
1175 allocate_rx_buffers(dev);
1176
1177 np->timer.expires = RUN_AT(next_tick);
1178 add_timer(&np->timer);
1179 }
1180
1181
1182 static void tx_timeout(struct net_device *dev)
1183 {
1184 struct netdev_private *np = dev->priv;
1185 long ioaddr = dev->base_addr;
1186 int i;
1187
1188 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
1189 " resetting...\n", dev->name, readl(ioaddr + ISR));
1190
1191 {
1192
1193 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1194 for (i = 0; i < RX_RING_SIZE; i++)
1195 printk(" %8.8x", (unsigned int) np->rx_ring[i].status);
1196 printk("\n" KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1197 for (i = 0; i < TX_RING_SIZE; i++)
1198 printk(" %4.4x", np->tx_ring[i].status);
1199 printk("\n");
1200 }
1201
1202 /* Reinit. Gross */
1203
1204 /* Reset the chip's Tx and Rx processes. */
1205 stop_nic_tx(ioaddr, 0);
1206 reset_rx_descriptors(dev);
1207
1208 /* Disable interrupts by clearing the interrupt mask. */
1209 writel(0x0000, ioaddr + IMR);
1210
1211 /* Reset the chip to erase previous misconfiguration. */
1212 writel(0x00000001, ioaddr + BCR);
1213
1214 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1215 We surely wait too long (address+data phase). Who cares ? */
1216 for (i = 0; i < 50; i++) {
1217 readl(ioaddr + BCR);
1218 rmb();
1219 }
1220
1221 writel((np->cur_tx - np->tx_ring)*sizeof(struct fealnx_desc) +
1222 np->tx_ring_dma, ioaddr + TXLBA);
1223 writel((np->cur_rx - np->rx_ring)*sizeof(struct fealnx_desc) +
1224 np->rx_ring_dma, ioaddr + RXLBA);
1225
1226 writel(np->bcrvalue, ioaddr + BCR);
1227
1228 writel(0, dev->base_addr + RXPDR);
1229 set_rx_mode(dev);
1230 /* Clear and Enable interrupts by setting the interrupt mask. */
1231 writel(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1232 writel(np->imrvalue, ioaddr + IMR);
1233
1234 writel(0, dev->base_addr + TXPDR);
1235
1236 dev->trans_start = jiffies;
1237 np->stats.tx_errors++;
1238
1239 return;
1240 }
1241
1242
1243 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1244 static void init_ring(struct net_device *dev)
1245 {
1246 struct netdev_private *np = dev->priv;
1247 int i;
1248
1249 /* initialize rx variables */
1250 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1251 np->cur_rx = &np->rx_ring[0];
1252 np->lack_rxbuf = NULL;
1253 np->really_rx_count = 0;
1254
1255 /* initial rx descriptors. */
1256 for (i = 0; i < RX_RING_SIZE; i++) {
1257 np->rx_ring[i].status = 0;
1258 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1259 np->rx_ring[i].next_desc = np->rx_ring_dma +
1260 (i + 1)*sizeof(struct fealnx_desc);
1261 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1262 np->rx_ring[i].skbuff = NULL;
1263 }
1264
1265 /* for the last rx descriptor */
1266 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1267 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1268
1269 /* allocate skb for rx buffers */
1270 for (i = 0; i < RX_RING_SIZE; i++) {
1271 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1272
1273 if (skb == NULL) {
1274 np->lack_rxbuf = &np->rx_ring[i];
1275 break;
1276 }
1277
1278 ++np->really_rx_count;
1279 np->rx_ring[i].skbuff = skb;
1280 skb->dev = dev; /* Mark as being used by this device. */
1281 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->tail,
1282 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1283 np->rx_ring[i].status = RXOWN;
1284 np->rx_ring[i].control |= RXIC;
1285 }
1286
1287 /* initialize tx variables */
1288 np->cur_tx = &np->tx_ring[0];
1289 np->cur_tx_copy = &np->tx_ring[0];
1290 np->really_tx_count = 0;
1291 np->free_tx_count = TX_RING_SIZE;
1292
1293 for (i = 0; i < TX_RING_SIZE; i++) {
1294 np->tx_ring[i].status = 0;
1295 np->tx_ring[i].next_desc = np->tx_ring_dma +
1296 (i + 1)*sizeof(struct fealnx_desc);
1297 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1298 np->tx_ring[i].skbuff = NULL;
1299 }
1300
1301 /* for the last tx descriptor */
1302 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1303 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1304
1305 return;
1306 }
1307
1308
1309 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1310 {
1311 struct netdev_private *np = dev->priv;
1312
1313 np->cur_tx_copy->skbuff = skb;
1314
1315 #define one_buffer
1316 #define BPT 1022
1317 #if defined(one_buffer)
1318 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1319 skb->len, PCI_DMA_TODEVICE);
1320 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1321 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1322 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1323 // 89/12/29 add,
1324 if (np->pci_dev->device == 0x891)
1325 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1326 np->cur_tx_copy->status = TXOWN;
1327 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1328 --np->free_tx_count;
1329 #elif defined(two_buffer)
1330 if (skb->len > BPT) {
1331 struct fealnx_desc *next;
1332
1333 /* for the first descriptor */
1334 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1335 BPT, PCI_DMA_TODEVICE);
1336 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1337 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1338 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1339
1340 /* for the last descriptor */
1341 next = (struct fealnx *) np->cur_tx_copy.next_desc_logical;
1342 next->skbuff = skb;
1343 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1344 next->control |= (skb->len << PKTSShift); /* pkt size */
1345 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1346 // 89/12/29 add,
1347 if (np->pci_dev->device == 0x891)
1348 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1349 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1350 skb->len - BPT, PCI_DMA_TODEVICE);
1351
1352 next->status = TXOWN;
1353 np->cur_tx_copy->status = TXOWN;
1354
1355 np->cur_tx_copy = next->next_desc_logical;
1356 np->free_tx_count -= 2;
1357 } else {
1358 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1359 skb->len, PCI_DMA_TODEVICE);
1360 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1361 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1362 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1363 // 89/12/29 add,
1364 if (np->pci_dev->device == 0x891)
1365 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1366 np->cur_tx_copy->status = TXOWN;
1367 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1368 --np->free_tx_count;
1369 }
1370 #endif
1371
1372 if (np->free_tx_count < 2)
1373 netif_stop_queue(dev);
1374 ++np->really_tx_count;
1375 writel(0, dev->base_addr + TXPDR);
1376 dev->trans_start = jiffies;
1377
1378 return 0;
1379 }
1380
1381
1382 void free_one_rx_descriptor(struct netdev_private *np)
1383 {
1384 if (np->really_rx_count == RX_RING_SIZE)
1385 np->cur_rx->status = RXOWN;
1386 else {
1387 np->lack_rxbuf->skbuff = np->cur_rx->skbuff;
1388 np->lack_rxbuf->buffer = np->cur_rx->buffer;
1389 np->lack_rxbuf->status = RXOWN;
1390 ++np->really_rx_count;
1391 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1392 }
1393 np->cur_rx = np->cur_rx->next_desc_logical;
1394 }
1395
1396
1397 void reset_rx_descriptors(struct net_device *dev)
1398 {
1399 struct netdev_private *np = dev->priv;
1400
1401 stop_nic_rx(dev->base_addr, np->crvalue);
1402
1403 while (!(np->cur_rx->status & RXOWN))
1404 free_one_rx_descriptor(np);
1405
1406 allocate_rx_buffers(dev);
1407
1408 writel(np->rx_ring_dma + (np->cur_rx - np->rx_ring),
1409 dev->base_addr + RXLBA);
1410 writel(np->crvalue, dev->base_addr + TCRRCR);
1411 }
1412
1413
1414 /* The interrupt handler does all of the Rx thread work and cleans up
1415 after the Tx thread. */
1416 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
1417 {
1418 struct net_device *dev = (struct net_device *) dev_instance;
1419 struct netdev_private *np = dev->priv;
1420 long ioaddr, boguscnt = max_interrupt_work;
1421 unsigned int num_tx = 0;
1422 int handled = 0;
1423
1424 writel(0, dev->base_addr + IMR);
1425
1426 ioaddr = dev->base_addr;
1427 np = (struct netdev_private *) dev->priv;
1428
1429 do {
1430 u32 intr_status = readl(ioaddr + ISR);
1431
1432 /* Acknowledge all of the current interrupt sources ASAP. */
1433 writel(intr_status, ioaddr + ISR);
1434
1435 if (debug)
1436 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1437 intr_status);
1438
1439 if (!(intr_status & np->imrvalue))
1440 break;
1441
1442 handled = 1;
1443
1444 // 90/1/16 delete,
1445 //
1446 // if (intr_status & FBE)
1447 // { /* fatal error */
1448 // stop_nic_tx(ioaddr, 0);
1449 // stop_nic_rx(ioaddr, 0);
1450 // break;
1451 // };
1452
1453 if (intr_status & TUNF)
1454 writel(0, ioaddr + TXPDR);
1455
1456 if (intr_status & CNTOVF) {
1457 /* missed pkts */
1458 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1459
1460 /* crc error */
1461 np->stats.rx_crc_errors +=
1462 (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1463 }
1464
1465 if (intr_status & (RI | RBU)) {
1466 if (intr_status & RI)
1467 netdev_rx(dev);
1468 else
1469 reset_rx_descriptors(dev);
1470 }
1471
1472 while (np->really_tx_count) {
1473 long tx_status = np->cur_tx->status;
1474 long tx_control = np->cur_tx->control;
1475
1476 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1477 struct fealnx_desc *next;
1478
1479 next = np->cur_tx->next_desc_logical;
1480 tx_status = next->status;
1481 tx_control = next->control;
1482 }
1483
1484 if (tx_status & TXOWN)
1485 break;
1486
1487 if (!(np->crvalue & 0x02000000)) {
1488 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1489 np->stats.tx_errors++;
1490 if (tx_status & EC)
1491 np->stats.tx_aborted_errors++;
1492 if (tx_status & CSL)
1493 np->stats.tx_carrier_errors++;
1494 if (tx_status & LC)
1495 np->stats.tx_window_errors++;
1496 if (tx_status & UDF)
1497 np->stats.tx_fifo_errors++;
1498 if ((tx_status & HF) && np->mii.full_duplex == 0)
1499 np->stats.tx_heartbeat_errors++;
1500
1501 } else {
1502 np->stats.tx_bytes +=
1503 ((tx_control & PKTSMask) >> PKTSShift);
1504
1505 np->stats.collisions +=
1506 ((tx_status & NCRMask) >> NCRShift);
1507 np->stats.tx_packets++;
1508 }
1509 } else {
1510 np->stats.tx_bytes +=
1511 ((tx_control & PKTSMask) >> PKTSShift);
1512 np->stats.tx_packets++;
1513 }
1514
1515 /* Free the original skb. */
1516 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1517 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1518 dev_kfree_skb_irq(np->cur_tx->skbuff);
1519 np->cur_tx->skbuff = NULL;
1520 --np->really_tx_count;
1521 if (np->cur_tx->control & TXLD) {
1522 np->cur_tx = np->cur_tx->next_desc_logical;
1523 ++np->free_tx_count;
1524 } else {
1525 np->cur_tx = np->cur_tx->next_desc_logical;
1526 np->cur_tx = np->cur_tx->next_desc_logical;
1527 np->free_tx_count += 2;
1528 }
1529 num_tx++;
1530 } /* end of for loop */
1531
1532 if (num_tx && np->free_tx_count >= 2)
1533 netif_wake_queue(dev);
1534
1535 /* read transmit status for enhanced mode only */
1536 if (np->crvalue & 0x02000000) {
1537 long data;
1538
1539 data = readl(ioaddr + TSR);
1540 np->stats.tx_errors += (data & 0xff000000) >> 24;
1541 np->stats.tx_aborted_errors += (data & 0xff000000) >> 24;
1542 np->stats.tx_window_errors += (data & 0x00ff0000) >> 16;
1543 np->stats.collisions += (data & 0x0000ffff);
1544 }
1545
1546 if (--boguscnt < 0) {
1547 printk(KERN_WARNING "%s: Too much work at interrupt, "
1548 "status=0x%4.4x.\n", dev->name, intr_status);
1549 break;
1550 }
1551 } while (1);
1552
1553 /* read the tally counters */
1554 /* missed pkts */
1555 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1556
1557 /* crc error */
1558 np->stats.rx_crc_errors += (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1559
1560 if (debug)
1561 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1562 dev->name, readl(ioaddr + ISR));
1563
1564 writel(np->imrvalue, ioaddr + IMR);
1565
1566 return IRQ_RETVAL(handled);
1567 }
1568
1569
1570 /* This routine is logically part of the interrupt handler, but separated
1571 for clarity and better register allocation. */
1572 static int netdev_rx(struct net_device *dev)
1573 {
1574 struct netdev_private *np = dev->priv;
1575
1576 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1577 while (!(np->cur_rx->status & RXOWN)) {
1578 s32 rx_status = np->cur_rx->status;
1579
1580 if (np->really_rx_count == 0)
1581 break;
1582
1583 if (debug)
1584 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1585
1586 if ((!((rx_status & RXFSD) && (rx_status & RXLSD)))
1587 || (rx_status & ErrorSummary)) {
1588 if (rx_status & ErrorSummary) { /* there was a fatal error */
1589 if (debug)
1590 printk(KERN_DEBUG
1591 "%s: Receive error, Rx status %8.8x.\n",
1592 dev->name, rx_status);
1593
1594 np->stats.rx_errors++; /* end of a packet. */
1595 if (rx_status & (LONG | RUNT))
1596 np->stats.rx_length_errors++;
1597 if (rx_status & RXER)
1598 np->stats.rx_frame_errors++;
1599 if (rx_status & CRC)
1600 np->stats.rx_crc_errors++;
1601 } else {
1602 int need_to_reset = 0;
1603 int desno = 0;
1604
1605 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1606 struct fealnx_desc *cur;
1607
1608 /* check this packet is received completely? */
1609 cur = np->cur_rx;
1610 while (desno <= np->really_rx_count) {
1611 ++desno;
1612 if ((!(cur->status & RXOWN))
1613 && (cur->status & RXLSD))
1614 break;
1615 /* goto next rx descriptor */
1616 cur = cur->next_desc_logical;
1617 }
1618 if (desno > np->really_rx_count)
1619 need_to_reset = 1;
1620 } else /* RXLSD did not find, something error */
1621 need_to_reset = 1;
1622
1623 if (need_to_reset == 0) {
1624 int i;
1625
1626 np->stats.rx_length_errors++;
1627
1628 /* free all rx descriptors related this long pkt */
1629 for (i = 0; i < desno; ++i)
1630 free_one_rx_descriptor(np);
1631 continue;
1632 } else { /* something error, need to reset this chip */
1633 reset_rx_descriptors(dev);
1634 }
1635 break; /* exit the while loop */
1636 }
1637 } else { /* this received pkt is ok */
1638
1639 struct sk_buff *skb;
1640 /* Omit the four octet CRC from the length. */
1641 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1642
1643 #ifndef final_version
1644 if (debug)
1645 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1646 " status %x.\n", pkt_len, rx_status);
1647 #endif
1648 pci_dma_sync_single(np->pci_dev, np->cur_rx->buffer,
1649 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1650 pci_unmap_single(np->pci_dev, np->cur_rx->buffer,
1651 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1652
1653 /* Check if the packet is long enough to accept without copying
1654 to a minimally-sized skbuff. */
1655 if (pkt_len < rx_copybreak &&
1656 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1657 skb->dev = dev;
1658 skb_reserve(skb, 2); /* 16 byte align the IP header */
1659 /* Call copy + cksum if available. */
1660
1661 #if ! defined(__alpha__)
1662 eth_copy_and_sum(skb,
1663 np->cur_rx->skbuff->tail, pkt_len, 0);
1664 skb_put(skb, pkt_len);
1665 #else
1666 memcpy(skb_put(skb, pkt_len),
1667 np->cur_rx->skbuff->tail, pkt_len);
1668 #endif
1669 } else {
1670 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1671 np->cur_rx->skbuff = NULL;
1672 if (np->really_rx_count == RX_RING_SIZE)
1673 np->lack_rxbuf = np->cur_rx;
1674 --np->really_rx_count;
1675 }
1676 skb->protocol = eth_type_trans(skb, dev);
1677 netif_rx(skb);
1678 dev->last_rx = jiffies;
1679 np->stats.rx_packets++;
1680 np->stats.rx_bytes += pkt_len;
1681 }
1682
1683 if (np->cur_rx->skbuff == NULL) {
1684 struct sk_buff *skb;
1685
1686 skb = dev_alloc_skb(np->rx_buf_sz);
1687
1688 if (skb != NULL) {
1689 skb->dev = dev; /* Mark as being used by this device. */
1690 np->cur_rx->buffer = pci_map_single(np->pci_dev, skb->tail,
1691 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1692 np->cur_rx->skbuff = skb;
1693 ++np->really_rx_count;
1694 }
1695 }
1696
1697 if (np->cur_rx->skbuff != NULL)
1698 free_one_rx_descriptor(np);
1699 } /* end of while loop */
1700
1701 /* allocate skb for rx buffers */
1702 allocate_rx_buffers(dev);
1703
1704 return 0;
1705 }
1706
1707
1708 static struct net_device_stats *get_stats(struct net_device *dev)
1709 {
1710 long ioaddr = dev->base_addr;
1711 struct netdev_private *np = dev->priv;
1712
1713 /* The chip only need report frame silently dropped. */
1714 if (netif_running(dev)) {
1715 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1716 np->stats.rx_crc_errors += (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1717 }
1718
1719 return &np->stats;
1720 }
1721
1722 static void set_rx_mode(struct net_device *dev)
1723 {
1724 struct netdev_private *np = dev->priv;
1725 long ioaddr = dev->base_addr;
1726 u32 mc_filter[2]; /* Multicast hash filter */
1727 u32 rx_mode;
1728
1729 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1730 /* Unconditionally log net taps. */
1731 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1732 memset(mc_filter, 0xff, sizeof(mc_filter));
1733 rx_mode = PROM | AB | AM;
1734 } else if ((dev->mc_count > multicast_filter_limit)
1735 || (dev->flags & IFF_ALLMULTI)) {
1736 /* Too many to match, or accept all multicasts. */
1737 memset(mc_filter, 0xff, sizeof(mc_filter));
1738 rx_mode = AB | AM;
1739 } else {
1740 struct dev_mc_list *mclist;
1741 int i;
1742
1743 memset(mc_filter, 0, sizeof(mc_filter));
1744 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1745 i++, mclist = mclist->next) {
1746 unsigned int bit;
1747 bit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1748 mc_filter[bit >> 5] |= (1 << bit);
1749 }
1750 rx_mode = AB | AM;
1751 }
1752
1753 stop_nic_tx(ioaddr, np->crvalue);
1754 stop_nic_rx(ioaddr, np->crvalue & (~0x40000));
1755
1756 writel(mc_filter[0], ioaddr + MAR0);
1757 writel(mc_filter[1], ioaddr + MAR1);
1758 np->crvalue &= ~RxModeMask;
1759 np->crvalue |= rx_mode;
1760 writel(np->crvalue, ioaddr + TCRRCR);
1761 }
1762
1763 static int netdev_ethtool_ioctl (struct net_device *dev, void *useraddr)
1764 {
1765 struct netdev_private *np = dev->priv;
1766 u32 ethcmd;
1767
1768 if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
1769 return -EFAULT;
1770
1771 switch (ethcmd) {
1772 case ETHTOOL_GDRVINFO: {
1773 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1774 strcpy (info.driver, DRV_NAME);
1775 strcpy (info.version, DRV_VERSION);
1776 strcpy (info.bus_info, np->pci_dev->slot_name);
1777 if (copy_to_user (useraddr, &info, sizeof (info)))
1778 return -EFAULT;
1779 return 0;
1780 }
1781
1782 /* get settings */
1783 case ETHTOOL_GSET: {
1784 struct ethtool_cmd ecmd = { ETHTOOL_GSET };
1785 spin_lock_irq(&np->lock);
1786 mii_ethtool_gset(&np->mii, &ecmd);
1787 spin_unlock_irq(&np->lock);
1788 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
1789 return -EFAULT;
1790 return 0;
1791 }
1792 /* set settings */
1793 case ETHTOOL_SSET: {
1794 int r;
1795 struct ethtool_cmd ecmd;
1796 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
1797 return -EFAULT;
1798 spin_lock_irq(&np->lock);
1799 r = mii_ethtool_sset(&np->mii, &ecmd);
1800 spin_unlock_irq(&np->lock);
1801 return r;
1802 }
1803 /* restart autonegotiation */
1804 case ETHTOOL_NWAY_RST: {
1805 return mii_nway_restart(&np->mii);
1806 }
1807 /* get link status */
1808 case ETHTOOL_GLINK: {
1809 struct ethtool_value edata = {ETHTOOL_GLINK};
1810 edata.data = mii_link_ok(&np->mii);
1811 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1812 return -EFAULT;
1813 return 0;
1814 }
1815
1816 /* get message-level */
1817 case ETHTOOL_GMSGLVL: {
1818 struct ethtool_value edata = {ETHTOOL_GMSGLVL};
1819 edata.data = debug;
1820 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1821 return -EFAULT;
1822 return 0;
1823 }
1824 /* set message-level */
1825 case ETHTOOL_SMSGLVL: {
1826 struct ethtool_value edata;
1827 if (copy_from_user(&edata, useraddr, sizeof(edata)))
1828 return -EFAULT;
1829 debug = edata.data;
1830 return 0;
1831 }
1832 default:
1833 break;
1834 }
1835
1836 return -EOPNOTSUPP;
1837 }
1838
1839
1840 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1841 {
1842 struct netdev_private *np = dev->priv;
1843 struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
1844 int rc;
1845
1846 if (!netif_running(dev))
1847 return -EINVAL;
1848
1849 if (cmd == SIOCETHTOOL)
1850 rc = netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
1851
1852 else {
1853 spin_lock_irq(&np->lock);
1854 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1855 spin_unlock_irq(&np->lock);
1856 }
1857
1858 return rc;
1859 }
1860
1861
1862 static int netdev_close(struct net_device *dev)
1863 {
1864 long ioaddr = dev->base_addr;
1865 struct netdev_private *np = dev->priv;
1866 int i;
1867
1868 netif_stop_queue(dev);
1869
1870 /* Disable interrupts by clearing the interrupt mask. */
1871 writel(0x0000, ioaddr + IMR);
1872
1873 /* Stop the chip's Tx and Rx processes. */
1874 stop_nic_tx(ioaddr, 0);
1875 stop_nic_rx(ioaddr, 0);
1876
1877 del_timer_sync(&np->timer);
1878
1879 free_irq(dev->irq, dev);
1880
1881 /* Free all the skbuffs in the Rx queue. */
1882 for (i = 0; i < RX_RING_SIZE; i++) {
1883 struct sk_buff *skb = np->rx_ring[i].skbuff;
1884
1885 np->rx_ring[i].status = 0;
1886 if (skb) {
1887 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1888 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1889 dev_kfree_skb(skb);
1890 np->rx_ring[i].skbuff = NULL;
1891 }
1892 }
1893
1894 for (i = 0; i < TX_RING_SIZE; i++) {
1895 struct sk_buff *skb = np->tx_ring[i].skbuff;
1896
1897 if (skb) {
1898 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1899 skb->len, PCI_DMA_TODEVICE);
1900 dev_kfree_skb(skb);
1901 np->tx_ring[i].skbuff = NULL;
1902 }
1903 }
1904
1905 return 0;
1906 }
1907
1908 static struct pci_device_id fealnx_pci_tbl[] __devinitdata = {
1909 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1910 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1911 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1912 {} /* terminate list */
1913 };
1914 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1915
1916
1917 static struct pci_driver fealnx_driver = {
1918 .name = "fealnx",
1919 .id_table = fealnx_pci_tbl,
1920 .probe = fealnx_init_one,
1921 .remove = __devexit_p(fealnx_remove_one),
1922 };
1923
1924 static int __init fealnx_init(void)
1925 {
1926 /* when a module, this is printed whether or not devices are found in probe */
1927 #ifdef MODULE
1928 printk (version);
1929 #endif
1930
1931 return pci_module_init(&fealnx_driver);
1932 }
1933
1934 static void __exit fealnx_exit(void)
1935 {
1936 pci_unregister_driver(&fealnx_driver);
1937 }
1938
1939 module_init(fealnx_init);
1940 module_exit(fealnx_exit);
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