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1 /*
2 * File Name:
3 * defxx.c
4 *
5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference.
10 *
11 * Abstract:
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
14 *
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
17 *
18 * Maintainers:
19 * LVS Lawrence V. Stefani
20 *
21 * Contact:
22 * The author may be reached at:
23 *
24 * Inet: stefani@lkg.dec.com
25 * (NOTE! this address no longer works -jgarzik)
26 *
27 * Mail: Digital Equipment Corporation
28 * 550 King Street
29 * M/S: LKG1-3/M07
30 * Littleton, MA 01460
31 *
32 * Credits:
33 * I'd like to thank Patricia Cross for helping me get started with
34 * Linux, David Davies for a lot of help upgrading and configuring
35 * my development system and for answering many OS and driver
36 * development questions, and Alan Cox for recommendations and
37 * integration help on getting FDDI support into Linux. LVS
38 *
39 * Driver Architecture:
40 * The driver architecture is largely based on previous driver work
41 * for other operating systems. The upper edge interface and
42 * functions were largely taken from existing Linux device drivers
43 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
44 * driver.
45 *
46 * Adapter Probe -
47 * The driver scans for supported EISA adapters by reading the
48 * SLOT ID register for each EISA slot and making a match
49 * against the expected value.
50 *
51 * Bus-Specific Initialization -
52 * This driver currently supports both EISA and PCI controller
53 * families. While the custom DMA chip and FDDI logic is similar
54 * or identical, the bus logic is very different. After
55 * initialization, the only bus-specific differences is in how the
56 * driver enables and disables interrupts. Other than that, the
57 * run-time critical code behaves the same on both families.
58 * It's important to note that both adapter families are configured
59 * to I/O map, rather than memory map, the adapter registers.
60 *
61 * Driver Open/Close -
62 * In the driver open routine, the driver ISR (interrupt service
63 * routine) is registered and the adapter is brought to an
64 * operational state. In the driver close routine, the opposite
65 * occurs; the driver ISR is deregistered and the adapter is
66 * brought to a safe, but closed state. Users may use consecutive
67 * commands to bring the adapter up and down as in the following
68 * example:
69 * ifconfig fddi0 up
70 * ifconfig fddi0 down
71 * ifconfig fddi0 up
72 *
73 * Driver Shutdown -
74 * Apparently, there is no shutdown or halt routine support under
75 * Linux. This routine would be called during "reboot" or
76 * "shutdown" to allow the driver to place the adapter in a safe
77 * state before a warm reboot occurs. To be really safe, the user
78 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
79 * to ensure that the adapter DMA engine is taken off-line. However,
80 * the current driver code anticipates this problem and always issues
81 * a soft reset of the adapter at the beginning of driver initialization.
82 * A future driver enhancement in this area may occur in 2.1.X where
83 * Alan indicated that a shutdown handler may be implemented.
84 *
85 * Interrupt Service Routine -
86 * The driver supports shared interrupts, so the ISR is registered for
87 * each board with the appropriate flag and the pointer to that board's
88 * device structure. This provides the context during interrupt
89 * processing to support shared interrupts and multiple boards.
90 *
91 * Interrupt enabling/disabling can occur at many levels. At the host
92 * end, you can disable system interrupts, or disable interrupts at the
93 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
94 * have a bus-logic chip interrupt enable/disable as well as a DMA
95 * controller interrupt enable/disable.
96 *
97 * The driver currently enables and disables adapter interrupts at the
98 * bus-logic chip and assumes that Linux will take care of clearing or
99 * acknowledging any host-based interrupt chips.
100 *
101 * Control Functions -
102 * Control functions are those used to support functions such as adding
103 * or deleting multicast addresses, enabling or disabling packet
104 * reception filters, or other custom/proprietary commands. Presently,
105 * the driver supports the "get statistics", "set multicast list", and
106 * "set mac address" functions defined by Linux. A list of possible
107 * enhancements include:
108 *
109 * - Custom ioctl interface for executing port interface commands
110 * - Custom ioctl interface for adding unicast addresses to
111 * adapter CAM (to support bridge functions).
112 * - Custom ioctl interface for supporting firmware upgrades.
113 *
114 * Hardware (port interface) Support Routines -
115 * The driver function names that start with "dfx_hw_" represent
116 * low-level port interface routines that are called frequently. They
117 * include issuing a DMA or port control command to the adapter,
118 * resetting the adapter, or reading the adapter state. Since the
119 * driver initialization and run-time code must make calls into the
120 * port interface, these routines were written to be as generic and
121 * usable as possible.
122 *
123 * Receive Path -
124 * The adapter DMA engine supports a 256 entry receive descriptor block
125 * of which up to 255 entries can be used at any given time. The
126 * architecture is a standard producer, consumer, completion model in
127 * which the driver "produces" receive buffers to the adapter, the
128 * adapter "consumes" the receive buffers by DMAing incoming packet data,
129 * and the driver "completes" the receive buffers by servicing the
130 * incoming packet, then "produces" a new buffer and starts the cycle
131 * again. Receive buffers can be fragmented in up to 16 fragments
132 * (descriptor entries). For simplicity, this driver posts
133 * single-fragment receive buffers of 4608 bytes, then allocates a
134 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
135 * utilization, a better approach would be to pass up the receive
136 * buffer (no extra copy) then allocate and post a replacement buffer.
137 * This is a performance enhancement that should be looked into at
138 * some point.
139 *
140 * Transmit Path -
141 * Like the receive path, the adapter DMA engine supports a 256 entry
142 * transmit descriptor block of which up to 255 entries can be used at
143 * any given time. Transmit buffers can be fragmented in up to 255
144 * fragments (descriptor entries). This driver always posts one
145 * fragment per transmit packet request.
146 *
147 * The fragment contains the entire packet from FC to end of data.
148 * Before posting the buffer to the adapter, the driver sets a three-byte
149 * packet request header (PRH) which is required by the Motorola MAC chip
150 * used on the adapters. The PRH tells the MAC the type of token to
151 * receive/send, whether or not to generate and append the CRC, whether
152 * synchronous or asynchronous framing is used, etc. Since the PRH
153 * definition is not necessarily consistent across all FDDI chipsets,
154 * the driver, rather than the common FDDI packet handler routines,
155 * sets these bytes.
156 *
157 * To reduce the amount of descriptor fetches needed per transmit request,
158 * the driver takes advantage of the fact that there are at least three
159 * bytes available before the skb->data field on the outgoing transmit
160 * request. This is guaranteed by having fddi_setup() in net_init.c set
161 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
162 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
163 * bytes which we'll use to store the PRH.
164 *
165 * There's a subtle advantage to adding these pad bytes to the
166 * hard_header_len, it ensures that the data portion of the packet for
167 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
168 * implementations may not need the extra padding and can start copying
169 * or DMAing directly from the FC byte which starts at skb->data. Should
170 * another driver implementation need ADDITIONAL padding, the net_init.c
171 * module should be updated and dev->hard_header_len should be increased.
172 * NOTE: To maintain the alignment on the data portion of the packet,
173 * dev->hard_header_len should always be evenly divisible by 4 and at
174 * least 24 bytes in size.
175 *
176 * Modification History:
177 * Date Name Description
178 * 16-Aug-96 LVS Created.
179 * 20-Aug-96 LVS Updated dfx_probe so that version information
180 * string is only displayed if 1 or more cards are
181 * found. Changed dfx_rcv_queue_process to copy
182 * 3 NULL bytes before FC to ensure that data is
183 * longword aligned in receive buffer.
184 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
185 * LLC group promiscuous mode if multicast list
186 * is too large. LLC individual/group promiscuous
187 * mode is now disabled if IFF_PROMISC flag not set.
188 * dfx_xmt_queue_pkt no longer checks for NULL skb
189 * on Alan Cox recommendation. Added node address
190 * override support.
191 * 12-Sep-96 LVS Reset current address to factory address during
192 * device open. Updated transmit path to post a
193 * single fragment which includes PRH->end of data.
194 * Mar 2000 AC Did various cleanups for 2.3.x
195 * Jun 2000 jgarzik PCI and resource alloc cleanups
196 * Jul 2000 tjeerd Much cleanup and some bug fixes
197 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
198 * Feb 2001 Skb allocation fixes
199 * Feb 2001 davej PCI enable cleanups.
200 */
202 #error Please convert me to Documentation/DMA-mapping.txt
204 /* Include files */
206 #include <linux/module.h>
207 #include <linux/kernel.h>
208 #include <linux/string.h>
209 #include <linux/errno.h>
210 #include <linux/ioport.h>
211 #include <linux/slab.h>
212 #include <linux/interrupt.h>
213 #include <linux/pci.h>
214 #include <linux/delay.h>
215 #include <linux/init.h>
216 #include <linux/netdevice.h>
217 #include <linux/fddidevice.h>
218 #include <linux/skbuff.h>
220 #include <asm/byteorder.h>
221 #include <asm/bitops.h>
222 #include <asm/io.h>
226 /* Version information string - should be updated prior to each new release!!! */
231 #define DYNAMIC_BUFFERS 1
233 #define SKBUFF_RX_COPYBREAK 200
234 /*
235 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
236 * alignment for compatibility with old EISA boards.
237 */
238 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
240 /* Define module-wide (static) routines */
263 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
276 /* Define module-wide (static) variables */
280 \f
281 /*
282 * =======================
283 * = dfx_port_write_byte =
284 * = dfx_port_read_byte =
285 * = dfx_port_write_long =
286 * = dfx_port_read_long =
287 * =======================
288 *
289 * Overview:
290 * Routines for reading and writing values from/to adapter
291 *
292 * Returns:
293 * None
294 *
295 * Arguments:
296 * bp - pointer to board information
297 * offset - register offset from base I/O address
298 * data - for dfx_port_write_byte and dfx_port_write_long, this
299 * is a value to write.
300 * for dfx_port_read_byte and dfx_port_read_byte, this
301 * is a pointer to store the read value.
302 *
303 * Functional Description:
304 * These routines perform the correct operation to read or write
305 * the adapter register.
306 *
307 * EISA port block base addresses are based on the slot number in which the
308 * controller is installed. For example, if the EISA controller is installed
309 * in slot 4, the port block base address is 0x4000. If the controller is
310 * installed in slot 2, the port block base address is 0x2000, and so on.
311 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
312 * registers using the register offsets defined in DEFXX.H.
313 *
314 * PCI port block base addresses are assigned by the PCI BIOS or system
315 * firmware. There is one 128 byte port block which can be accessed. It
316 * allows for I/O mapping of both PDQ and PFI registers using the register
317 * offsets defined in DEFXX.H.
318 *
319 * Return Codes:
320 * None
321 *
322 * Assumptions:
323 * bp->base_addr is a valid base I/O address for this adapter.
324 * offset is a valid register offset for this adapter.
325 *
326 * Side Effects:
327 * Rather than produce macros for these functions, these routines
328 * are defined using "inline" to ensure that the compiler will
329 * generate inline code and not waste a procedure call and return.
330 * This provides all the benefits of macros, but with the
331 * advantage of strict data type checking.
332 */
337 u8 data
338 )
340 {
344 }
349 u8 *data
350 )
352 {
356 }
361 u32 data
362 )
364 {
368 }
373 u32 *data
374 )
376 {
380 }
382 \f
383 /*
384 * =============
385 * = dfx_init_one_pci_or_eisa =
386 * =============
387 *
388 * Overview:
389 * Initializes a supported FDDI EISA or PCI controller
390 *
391 * Returns:
392 * Condition code
393 *
394 * Arguments:
395 * pdev - pointer to pci device information (NULL for EISA)
396 * ioaddr - pointer to port (NULL for PCI)
397 *
398 * Functional Description:
399 *
400 * Return Codes:
401 * 0 - This device (fddi0, fddi1, etc) configured successfully
402 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
403 *
404 * Assumptions:
405 * It compiles so it should work :-( (PCI cards do :-)
406 *
407 * Side Effects:
408 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
409 * initialized and the board resources are read and stored in
410 * the device structure.
411 */
413 {
418 #ifndef MODULE
422 {
425 }
426 #endif
432 }
434 /* Enable PCI device. */
439 }
451 }
453 /* Initialize new device structure */
465 /* EISA board */
470 /* PCI board */
475 }
480 }
488 err_out_kfree:
490 err_out_region:
492 err_out:
495 }
498 {
500 }
503 {
511 /* Scan for FDDI EISA controllers */
514 {
518 {
522 }
523 }
525 }
526 \f
527 /*
528 * ================
529 * = dfx_bus_init =
530 * ================
531 *
532 * Overview:
533 * Initializes EISA and PCI controller bus-specific logic.
534 *
535 * Returns:
536 * None
537 *
538 * Arguments:
539 * dev - pointer to device information
540 *
541 * Functional Description:
542 * Determine and save adapter IRQ in device table,
543 * then perform bus-specific logic initialization.
544 *
545 * Return Codes:
546 * None
547 *
548 * Assumptions:
549 * dev->base_addr has already been set with the proper
550 * base I/O address for this device.
551 *
552 * Side Effects:
553 * Interrupts are enabled at the adapter bus-specific logic.
554 * Note: Interrupts at the DMA engine (PDQ chip) are not
555 * enabled yet.
556 */
559 {
565 /*
566 * Initialize base I/O address field in bp structure
567 *
568 * Note: bp->base_addr is the same as dev->base_addr.
569 * It's useful because often we'll need to read
570 * or write registers where we already have the
571 * bp pointer instead of the dev pointer. Having
572 * the base address in the bp structure will
573 * save a pointer dereference.
574 *
575 * IMPORTANT!! This field must be defined before
576 * any of the dfx_port_* inline functions are
577 * called.
578 */
582 /* And a pointer back to the net_device struct */
585 /* Initialize adapter based on bus type */
588 {
589 /* Get the interrupt level from the ESIC chip */
593 {
609 }
611 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
615 /* Set the I/O decode range of the board */
621 /* Enable access to rest of module (including PDQ and packet memory) */
625 /*
626 * Map PDQ registers into I/O space. This is done by clearing a bit
627 * in Burst Holdoff register.
628 */
633 /* Enable interrupts at EISA bus interface chip (ESIC) */
637 }
638 else
639 {
642 /* Get the interrupt level from the PCI Configuration Table */
646 /* Check Latency Timer and set if less than minimal */
650 {
653 }
655 /* Enable interrupts at PCI bus interface chip (PFI) */
658 }
659 }
661 \f
662 /*
663 * ========================
664 * = dfx_bus_config_check =
665 * ========================
666 *
667 * Overview:
668 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
669 * are illegal, then this routine will set new defaults.
670 *
671 * Returns:
672 * None
673 *
674 * Arguments:
675 * bp - pointer to board information
676 *
677 * Functional Description:
678 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
679 * PDQ, and all FDDI PCI controllers, all values are legal.
680 *
681 * Return Codes:
682 * None
683 *
684 * Assumptions:
685 * dfx_adap_init has NOT been called yet so burst size and other items have
686 * not been set.
687 *
688 * Side Effects:
689 * None
690 */
693 {
700 /* Configuration check only valid for EISA adapter */
703 {
706 /*
707 * First check if revision 2 EISA controller. Rev. 1 cards used
708 * PDQ revision B, so no workaround needed in this case. Rev. 3
709 * cards used PDQ revision E, so no workaround needed in this
710 * case, either. Only Rev. 2 cards used either Rev. D or E
711 * chips, so we must verify the chip revision on Rev. 2 cards.
712 */
715 {
716 /*
717 * Revision 2 FDDI EISA controller found, so let's check PDQ
718 * revision of adapter.
719 */
722 PI_PCTRL_M_SUB_CMD,
723 PI_SUB_CMD_K_PDQ_REV_GET,
727 {
728 /*
729 * Either we couldn't determine the PDQ revision, or
730 * we determined that it is at revision D. In either case,
731 * we need to implement the workaround.
732 */
734 /* Ensure that the burst size is set to 8 longwords or less */
737 {
745 }
747 /* Ensure that full-duplex mode is not enabled */
750 }
751 }
752 }
753 }
755 \f
756 /*
757 * ===================
758 * = dfx_driver_init =
759 * ===================
760 *
761 * Overview:
762 * Initializes remaining adapter board structure information
763 * and makes sure adapter is in a safe state prior to dfx_open().
764 *
765 * Returns:
766 * Condition code
767 *
768 * Arguments:
769 * dev - pointer to device information
770 *
771 * Functional Description:
772 * This function allocates additional resources such as the host memory
773 * blocks needed by the adapter (eg. descriptor and consumer blocks).
774 * Remaining bus initialization steps are also completed. The adapter
775 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
776 * must call dfx_open() to open the adapter and bring it on-line.
777 *
778 * Return Codes:
779 * DFX_K_SUCCESS - initialization succeeded
780 * DFX_K_FAILURE - initialization failed - could not allocate memory
781 * or read adapter MAC address
782 *
783 * Assumptions:
784 * Memory allocated from kmalloc() call is physically contiguous, locked
785 * memory whose physical address equals its virtual address.
786 *
787 * Side Effects:
788 * Adapter is reset and should be in DMA_UNAVAILABLE state before
789 * returning from this routine.
790 */
793 {
802 /* Initialize bus-specific hardware registers */
806 /*
807 * Initialize default values for configurable parameters
808 *
809 * Note: All of these parameters are ones that a user may
810 * want to customize. It'd be nice to break these
811 * out into Space.c or someplace else that's more
812 * accessible/understandable than this file.
813 */
820 /*
821 * Ensure that HW configuration is OK
822 *
823 * Note: Depending on the hardware revision, we may need to modify
824 * some of the configurable parameters to workaround hardware
825 * limitations. We'll perform this configuration check AFTER
826 * setting the parameters to their default values.
827 */
831 /* Disable PDQ interrupts first */
835 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
839 /* Read the factory MAC address from the adapter then save it */
842 PI_PCTRL_M_MLA,
843 PI_PDATA_A_MLA_K_LO,
846 {
849 }
853 PI_PCTRL_M_MLA,
854 PI_PDATA_A_MLA_K_HI,
857 {
860 }
863 /*
864 * Set current address to factory address
865 *
866 * Note: Node address override support is handled through
867 * dfx_ctl_set_mac_address.
868 */
872 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
882 else
883 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
894 /*
895 * Get memory for descriptor block, consumer block, and other buffers
896 * that need to be DMA read or written to by the adapter.
897 */
900 PI_CMD_REQ_K_SIZE_MAX +
901 PI_CMD_RSP_K_SIZE_MAX +
902 #ifndef DYNAMIC_BUFFERS
904 #endif
909 {
912 }
916 /*
917 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
918 * plus the amount of memory needed was allocated. The physical address
919 * is now 8K aligned. By carving up the memory in a specific order,
920 * we'll guarantee the alignment requirements for all other structures.
921 *
922 * Note: If the assumptions change regarding the non-paged, non-cached,
923 * physically contiguous nature of the memory block or the address
924 * alignments, then we'll need to implement a different algorithm
925 * for allocating the needed memory.
926 */
931 /* Reserve space for descriptor block */
938 /* Reserve space for command request buffer */
945 /* Reserve space for command response buffer */
952 /* Reserve space for the LLC host receive queue buffers */
957 #ifndef DYNAMIC_BUFFERS
960 #endif
962 /* Reserve space for the consumer block */
967 /* Display virtual and physical addresses if debug driver */
969 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", dev->name, (long)bp->descr_block_virt, bp->descr_block_phys);
970 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
971 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
972 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
973 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->cons_block_virt, bp->cons_block_phys);
976 }
978 \f
979 /*
980 * =================
981 * = dfx_adap_init =
982 * =================
983 *
984 * Overview:
985 * Brings the adapter to the link avail/link unavailable state.
986 *
987 * Returns:
988 * Condition code
989 *
990 * Arguments:
991 * bp - pointer to board information
992 * get_buffers - non-zero if buffers to be allocated
993 *
994 * Functional Description:
995 * Issues the low-level firmware/hardware calls necessary to bring
996 * the adapter up, or to properly reset and restore adapter during
997 * run-time.
998 *
999 * Return Codes:
1000 * DFX_K_SUCCESS - Adapter brought up successfully
1001 * DFX_K_FAILURE - Adapter initialization failed
1002 *
1003 * Assumptions:
1004 * bp->reset_type should be set to a valid reset type value before
1005 * calling this routine.
1006 *
1007 * Side Effects:
1008 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1009 * upon a successful return of this routine.
1010 */
1013 {
1016 /* Disable PDQ interrupts first */
1020 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1023 {
1026 }
1028 /*
1029 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1030 * so we'll acknowledge all Type 0 interrupts now before continuing.
1031 */
1035 /*
1036 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1037 *
1038 * Note: We only need to clear host copies of these registers. The PDQ reset
1039 * takes care of the on-board register values.
1040 */
1046 /* Clear consumer block before going to DMA_AVAILABLE state */
1050 /* Initialize the DMA Burst Size */
1053 PI_PCTRL_M_SUB_CMD,
1054 PI_SUB_CMD_K_BURST_SIZE_SET,
1057 {
1060 }
1062 /*
1063 * Set base address of Consumer Block
1064 *
1065 * Assumption: 32-bit physical address of consumer block is 64 byte
1066 * aligned. That is, bits 0-5 of the address must be zero.
1067 */
1070 PI_PCTRL_M_CONS_BLOCK,
1074 {
1077 }
1079 /*
1080 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
1081 *
1082 * Note: We also set the literal and data swapping requirements in this
1083 * command. Since this driver presently runs on Intel platforms
1084 * which are Little Endian, we'll tell the adapter to byte swap
1085 * data only. This code will need to change when we support
1086 * Big Endian systems (eg. PowerPC).
1087 *
1088 * Assumption: 32-bit physical address of descriptor block is 8Kbyte
1089 * aligned. That is, bits 0-12 of the address must be zero.
1090 */
1093 PI_PCTRL_M_INIT,
1097 {
1100 }
1102 /* Set transmit flush timeout value */
1110 {
1113 }
1115 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1126 {
1129 }
1131 /* Initialize adapter CAM */
1134 {
1137 }
1139 /* Initialize adapter filters */
1142 {
1145 }
1147 /*
1148 * Remove any existing dynamic buffers (i.e. if the adapter is being
1149 * reinitialized)
1150 */
1155 /* Initialize receive descriptor block and produce buffers */
1158 {
1163 }
1165 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1169 {
1174 }
1176 /* Initialization succeeded, reenable PDQ interrupts */
1180 }
1182 \f
1183 /*
1184 * ============
1185 * = dfx_open =
1186 * ============
1187 *
1188 * Overview:
1189 * Opens the adapter
1190 *
1191 * Returns:
1192 * Condition code
1193 *
1194 * Arguments:
1195 * dev - pointer to device information
1196 *
1197 * Functional Description:
1198 * This function brings the adapter to an operational state.
1199 *
1200 * Return Codes:
1201 * 0 - Adapter was successfully opened
1202 * -EAGAIN - Could not register IRQ or adapter initialization failed
1203 *
1204 * Assumptions:
1205 * This routine should only be called for a device that was
1206 * initialized successfully.
1207 *
1208 * Side Effects:
1209 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1210 * if the open is successful.
1211 */
1214 {
1220 /* Register IRQ - support shared interrupts by passing device ptr */
1226 }
1228 /*
1229 * Set current address to factory MAC address
1230 *
1231 * Note: We've already done this step in dfx_driver_init.
1232 * However, it's possible that a user has set a node
1233 * address override, then closed and reopened the
1234 * adapter. Unless we reset the device address field
1235 * now, we'll continue to use the existing modified
1236 * address.
1237 */
1241 /* Clear local unicast/multicast address tables and counts */
1248 /* Disable promiscuous filter settings */
1255 /* Reset and initialize adapter */
1259 {
1263 }
1265 /* Set device structure info */
1268 }
1270 \f
1271 /*
1272 * =============
1273 * = dfx_close =
1274 * =============
1275 *
1276 * Overview:
1277 * Closes the device/module.
1278 *
1279 * Returns:
1280 * Condition code
1281 *
1282 * Arguments:
1283 * dev - pointer to device information
1284 *
1285 * Functional Description:
1286 * This routine closes the adapter and brings it to a safe state.
1287 * The interrupt service routine is deregistered with the OS.
1288 * The adapter can be opened again with another call to dfx_open().
1289 *
1290 * Return Codes:
1291 * Always return 0.
1292 *
1293 * Assumptions:
1294 * No further requests for this adapter are made after this routine is
1295 * called. dfx_open() can be called to reset and reinitialize the
1296 * adapter.
1297 *
1298 * Side Effects:
1299 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1300 * routine.
1301 */
1304 {
1309 /* Disable PDQ interrupts first */
1313 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1317 /*
1318 * Flush any pending transmit buffers
1319 *
1320 * Note: It's important that we flush the transmit buffers
1321 * BEFORE we clear our copy of the Type 2 register.
1322 * Otherwise, we'll have no idea how many buffers
1323 * we need to free.
1324 */
1328 /*
1329 * Clear Type 1 and Type 2 registers after adapter reset
1330 *
1331 * Note: Even though we're closing the adapter, it's
1332 * possible that an interrupt will occur after
1333 * dfx_close is called. Without some assurance to
1334 * the contrary we want to make sure that we don't
1335 * process receive and transmit LLC frames and update
1336 * the Type 2 register with bad information.
1337 */
1343 /* Clear consumer block for the same reason given above */
1347 /* Release all dynamically allocate skb in the receive ring. */
1351 /* Clear device structure flags */
1355 /* Deregister (free) IRQ */
1360 }
1362 \f
1363 /*
1364 * ======================
1365 * = dfx_int_pr_halt_id =
1366 * ======================
1367 *
1368 * Overview:
1369 * Displays halt id's in string form.
1370 *
1371 * Returns:
1372 * None
1373 *
1374 * Arguments:
1375 * bp - pointer to board information
1376 *
1377 * Functional Description:
1378 * Determine current halt id and display appropriate string.
1379 *
1380 * Return Codes:
1381 * None
1382 *
1383 * Assumptions:
1384 * None
1385 *
1386 * Side Effects:
1387 * None
1388 */
1391 {
1395 /* Read the latest port status */
1399 /* Display halt state transition information */
1403 {
1443 }
1444 }
1446 \f
1447 /*
1448 * ==========================
1449 * = dfx_int_type_0_process =
1450 * ==========================
1451 *
1452 * Overview:
1453 * Processes Type 0 interrupts.
1454 *
1455 * Returns:
1456 * None
1457 *
1458 * Arguments:
1459 * bp - pointer to board information
1460 *
1461 * Functional Description:
1462 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1463 * is a serious fault on the adapter, then an error message is displayed
1464 * and the adapter is reset.
1465 *
1466 * One tricky potential timing window is the rapid succession of "link avail"
1467 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1468 * interrupt must be done before reading the state from the Port Status
1469 * register. This is true because a state change could occur after reading
1470 * the data, but before acknowledging the interrupt. If this state change
1471 * does happen, it would be lost because the driver is using the old state,
1472 * and it will never know about the new state because it subsequently
1473 * acknowledges the state change interrupt.
1474 *
1475 * INCORRECT CORRECT
1476 * read type 0 int reasons read type 0 int reasons
1477 * read adapter state ack type 0 interrupts
1478 * ack type 0 interrupts read adapter state
1479 * ... process interrupt ... ... process interrupt ...
1480 *
1481 * Return Codes:
1482 * None
1483 *
1484 * Assumptions:
1485 * None
1486 *
1487 * Side Effects:
1488 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1489 * or if the port status indicates that the adapter is halted. The driver
1490 * is responsible for reinitializing the adapter with the current CAM
1491 * contents and adapter filter settings.
1492 */
1496 {
1500 /*
1501 * Read host interrupt Type 0 register to determine which Type 0
1502 * interrupts are pending. Immediately write it back out to clear
1503 * those interrupts.
1504 */
1509 /* Check for Type 0 error interrupts */
1512 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1513 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1514 {
1515 /* Check for Non-Existent Memory error */
1520 /* Check for Packet Memory Parity error */
1525 /* Check for Host Bus Parity error */
1530 /* Reset adapter and bring it back on-line */
1536 {
1540 }
1543 }
1545 /* Check for transmit flush interrupt */
1548 {
1549 /* Flush any pending xmt's and acknowledge the flush interrupt */
1554 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1557 NULL);
1558 }
1560 /* Check for adapter state change */
1563 {
1564 /* Get latest adapter state */
1568 {
1569 /*
1570 * Adapter has transitioned to HALTED state, try to reset
1571 * adapter to bring it back on-line. If reset fails,
1572 * leave the adapter in the broken state.
1573 */
1578 /* Reset adapter and bring it back on-line */
1584 {
1588 }
1590 }
1592 {
1594 }
1595 }
1596 }
1598 \f
1599 /*
1600 * ==================
1601 * = dfx_int_common =
1602 * ==================
1603 *
1604 * Overview:
1605 * Interrupt service routine (ISR)
1606 *
1607 * Returns:
1608 * None
1609 *
1610 * Arguments:
1611 * bp - pointer to board information
1612 *
1613 * Functional Description:
1614 * This is the ISR which processes incoming adapter interrupts.
1615 *
1616 * Return Codes:
1617 * None
1618 *
1619 * Assumptions:
1620 * This routine assumes PDQ interrupts have not been disabled.
1621 * When interrupts are disabled at the PDQ, the Port Status register
1622 * is automatically cleared. This routine uses the Port Status
1623 * register value to determine whether a Type 0 interrupt occurred,
1624 * so it's important that adapter interrupts are not normally
1625 * enabled/disabled at the PDQ.
1626 *
1627 * It's vital that this routine is NOT reentered for the
1628 * same board and that the OS is not in another section of
1629 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1630 * different thread.
1631 *
1632 * Side Effects:
1633 * Pending interrupts are serviced. Depending on the type of
1634 * interrupt, acknowledging and clearing the interrupt at the
1635 * PDQ involves writing a register to clear the interrupt bit
1636 * or updating completion indices.
1637 */
1640 {
1644 /* Process xmt interrupts - frequent case, so always call this routine */
1649 /* Process rcv interrupts - frequent case, so always call this routine */
1653 /*
1654 * Transmit and receive producer and completion indices are updated on the
1655 * adapter by writing to the Type 2 Producer register. Since the frequent
1656 * case is that we'll be processing either LLC transmit or receive buffers,
1657 * we'll optimize I/O writes by doing a single register write here.
1658 */
1662 /* Read PDQ Port Status register to find out which interrupts need processing */
1666 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1670 }
1672 \f
1673 /*
1674 * =================
1675 * = dfx_interrupt =
1676 * =================
1677 *
1678 * Overview:
1679 * Interrupt processing routine
1680 *
1681 * Returns:
1682 * None
1683 *
1684 * Arguments:
1685 * irq - interrupt vector
1686 * dev_id - pointer to device information
1687 * regs - pointer to registers structure
1688 *
1689 * Functional Description:
1690 * This routine calls the interrupt processing routine for this adapter. It
1691 * disables and reenables adapter interrupts, as appropriate. We can support
1692 * shared interrupts since the incoming dev_id pointer provides our device
1693 * structure context.
1694 *
1695 * Return Codes:
1696 * None
1697 *
1698 * Assumptions:
1699 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1700 * on Intel-based systems) is done by the operating system outside this
1701 * routine.
1702 *
1703 * System interrupts are enabled through this call.
1704 *
1705 * Side Effects:
1706 * Interrupts are disabled, then reenabled at the adapter.
1707 */
1710 {
1715 /* Get board pointer only if device structure is valid */
1721 /* See if we're already servicing an interrupt */
1723 /* Service adapter interrupts */
1726 {
1727 /* Disable PDQ-PFI interrupts at PFI */
1731 /* Call interrupt service routine for this adapter */
1735 /* Clear PDQ interrupt status bit and reenable interrupts */
1740 }
1741 else
1742 {
1743 /* Disable interrupts at the ESIC */
1749 /* Call interrupt service routine for this adapter */
1753 /* Reenable interrupts at the ESIC */
1758 }
1761 }
1763 \f
1764 /*
1765 * =====================
1766 * = dfx_ctl_get_stats =
1767 * =====================
1768 *
1769 * Overview:
1770 * Get statistics for FDDI adapter
1771 *
1772 * Returns:
1773 * Pointer to FDDI statistics structure
1774 *
1775 * Arguments:
1776 * dev - pointer to device information
1777 *
1778 * Functional Description:
1779 * Gets current MIB objects from adapter, then
1780 * returns FDDI statistics structure as defined
1781 * in if_fddi.h.
1782 *
1783 * Note: Since the FDDI statistics structure is
1784 * still new and the device structure doesn't
1785 * have an FDDI-specific get statistics handler,
1786 * we'll return the FDDI statistics structure as
1787 * a pointer to an Ethernet statistics structure.
1788 * That way, at least the first part of the statistics
1789 * structure can be decoded properly, and it allows
1790 * "smart" applications to perform a second cast to
1791 * decode the FDDI-specific statistics.
1792 *
1793 * We'll have to pay attention to this routine as the
1794 * device structure becomes more mature and LAN media
1795 * independent.
1796 *
1797 * Return Codes:
1798 * None
1799 *
1800 * Assumptions:
1801 * None
1802 *
1803 * Side Effects:
1804 * None
1805 */
1808 {
1811 /* Fill the bp->stats structure with driver-maintained counters */
1817 bp->stats.rx_errors = (u32)(bp->rcv_crc_errors + bp->rcv_frame_status_errors + bp->rcv_length_errors);
1824 /* Get FDDI SMT MIB objects */
1830 /* Fill the bp->stats structure with the SMT MIB object values */
1832 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1836 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1851 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1855 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1856 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1861 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1862 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1863 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1864 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1868 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1885 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1890 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1891 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1896 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1897 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1904 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1905 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1925 /* Get FDDI counters */
1931 /* Fill the bp->stats structure with the FDDI counter values */
1946 }
1948 \f
1949 /*
1950 * ==============================
1951 * = dfx_ctl_set_multicast_list =
1952 * ==============================
1953 *
1954 * Overview:
1955 * Enable/Disable LLC frame promiscuous mode reception
1956 * on the adapter and/or update multicast address table.
1957 *
1958 * Returns:
1959 * None
1960 *
1961 * Arguments:
1962 * dev - pointer to device information
1963 *
1964 * Functional Description:
1965 * This routine follows a fairly simple algorithm for setting the
1966 * adapter filters and CAM:
1967 *
1968 * if IFF_PROMISC flag is set
1969 * enable LLC individual/group promiscuous mode
1970 * else
1971 * disable LLC individual/group promiscuous mode
1972 * if number of incoming multicast addresses >
1973 * (CAM max size - number of unicast addresses in CAM)
1974 * enable LLC group promiscuous mode
1975 * set driver-maintained multicast address count to zero
1976 * else
1977 * disable LLC group promiscuous mode
1978 * set driver-maintained multicast address count to incoming count
1979 * update adapter CAM
1980 * update adapter filters
1981 *
1982 * Return Codes:
1983 * None
1984 *
1985 * Assumptions:
1986 * Multicast addresses are presented in canonical (LSB) format.
1987 *
1988 * Side Effects:
1989 * On-board adapter CAM and filters are updated.
1990 */
1993 {
1998 /* Enable LLC frame promiscuous mode, if necessary */
2003 /* Else, update multicast address table */
2005 else
2006 {
2008 /*
2009 * Check whether incoming multicast address count exceeds table size
2010 *
2011 * Note: The adapters utilize an on-board 64 entry CAM for
2012 * supporting perfect filtering of multicast packets
2013 * and bridge functions when adding unicast addresses.
2014 * There is no hash function available. To support
2015 * additional multicast addresses, the all multicast
2016 * filter (LLC group promiscuous mode) must be enabled.
2017 *
2018 * The firmware reserves two CAM entries for SMT-related
2019 * multicast addresses, which leaves 62 entries available.
2020 * The following code ensures that we're not being asked
2021 * to add more than 62 addresses to the CAM. If we are,
2022 * the driver will enable the all multicast filter.
2023 * Should the number of multicast addresses drop below
2024 * the high water mark, the filter will be disabled and
2025 * perfect filtering will be used.
2026 */
2029 {
2032 }
2033 else
2034 {
2037 }
2039 /* Copy addresses to multicast address table, then update adapter CAM */
2043 {
2046 }
2048 {
2050 }
2051 else
2052 {
2053 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2054 }
2055 }
2057 /* Update adapter filters */
2060 {
2062 }
2063 else
2064 {
2066 }
2067 }
2069 \f
2070 /*
2071 * ===========================
2072 * = dfx_ctl_set_mac_address =
2073 * ===========================
2074 *
2075 * Overview:
2076 * Add node address override (unicast address) to adapter
2077 * CAM and update dev_addr field in device table.
2078 *
2079 * Returns:
2080 * None
2081 *
2082 * Arguments:
2083 * dev - pointer to device information
2084 * addr - pointer to sockaddr structure containing unicast address to add
2085 *
2086 * Functional Description:
2087 * The adapter supports node address overrides by adding one or more
2088 * unicast addresses to the adapter CAM. This is similar to adding
2089 * multicast addresses. In this routine we'll update the driver and
2090 * device structures with the new address, then update the adapter CAM
2091 * to ensure that the adapter will copy and strip frames destined and
2092 * sourced by that address.
2093 *
2094 * Return Codes:
2095 * Always returns zero.
2096 *
2097 * Assumptions:
2098 * The address pointed to by addr->sa_data is a valid unicast
2099 * address and is presented in canonical (LSB) format.
2100 *
2101 * Side Effects:
2102 * On-board adapter CAM is updated. On-board adapter filters
2103 * may be updated.
2104 */
2107 {
2111 /* Copy unicast address to driver-maintained structs and update count */
2117 /*
2118 * Verify we're not exceeding the CAM size by adding unicast address
2119 *
2120 * Note: It's possible that before entering this routine we've
2121 * already filled the CAM with 62 multicast addresses.
2122 * Since we need to place the node address override into
2123 * the CAM, we have to check to see that we're not
2124 * exceeding the CAM size. If we are, we have to enable
2125 * the LLC group (multicast) promiscuous mode filter as
2126 * in dfx_ctl_set_multicast_list.
2127 */
2130 {
2134 /* Update adapter filters */
2137 {
2139 }
2140 else
2141 {
2143 }
2144 }
2146 /* Update adapter CAM with new unicast address */
2149 {
2151 }
2152 else
2153 {
2155 }
2157 }
2159 \f
2160 /*
2161 * ======================
2162 * = dfx_ctl_update_cam =
2163 * ======================
2164 *
2165 * Overview:
2166 * Procedure to update adapter CAM (Content Addressable Memory)
2167 * with desired unicast and multicast address entries.
2168 *
2169 * Returns:
2170 * Condition code
2171 *
2172 * Arguments:
2173 * bp - pointer to board information
2174 *
2175 * Functional Description:
2176 * Updates adapter CAM with current contents of board structure
2177 * unicast and multicast address tables. Since there are only 62
2178 * free entries in CAM, this routine ensures that the command
2179 * request buffer is not overrun.
2180 *
2181 * Return Codes:
2182 * DFX_K_SUCCESS - Request succeeded
2183 * DFX_K_FAILURE - Request failed
2184 *
2185 * Assumptions:
2186 * All addresses being added (unicast and multicast) are in canonical
2187 * order.
2188 *
2189 * Side Effects:
2190 * On-board adapter CAM is updated.
2191 */
2194 {
2198 /*
2199 * Fill in command request information
2200 *
2201 * Note: Even though both the unicast and multicast address
2202 * table entries are stored as contiguous 6 byte entries,
2203 * the firmware address filter set command expects each
2204 * entry to be two longwords (8 bytes total). We must be
2205 * careful to only copy the six bytes of each unicast and
2206 * multicast table entry into each command entry. This
2207 * is also why we must first clear the entire command
2208 * request buffer.
2209 */
2215 /* Now add unicast addresses to command request buffer, if any */
2218 {
2220 {
2223 }
2224 }
2226 /* Now add multicast addresses to command request buffer, if any */
2229 {
2231 {
2234 }
2235 }
2237 /* Issue command to update adapter CAM, then return */
2242 }
2244 \f
2245 /*
2246 * ==========================
2247 * = dfx_ctl_update_filters =
2248 * ==========================
2249 *
2250 * Overview:
2251 * Procedure to update adapter filters with desired
2252 * filter settings.
2253 *
2254 * Returns:
2255 * Condition code
2256 *
2257 * Arguments:
2258 * bp - pointer to board information
2259 *
2260 * Functional Description:
2261 * Enables or disables filter using current filter settings.
2262 *
2263 * Return Codes:
2264 * DFX_K_SUCCESS - Request succeeded.
2265 * DFX_K_FAILURE - Request failed.
2266 *
2267 * Assumptions:
2268 * We must always pass up packets destined to the broadcast
2269 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2270 * broadcast filter enabled.
2271 *
2272 * Side Effects:
2273 * On-board adapter filters are updated.
2274 */
2277 {
2280 /* Fill in command request information */
2284 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2289 /* Initialize LLC Individual/Group Promiscuous filter */
2294 /* Initialize LLC Group Promiscuous filter */
2299 /* Terminate the item code list */
2303 /* Issue command to update adapter filters, then return */
2308 }
2310 \f
2311 /*
2312 * ======================
2313 * = dfx_hw_dma_cmd_req =
2314 * ======================
2315 *
2316 * Overview:
2317 * Sends PDQ DMA command to adapter firmware
2318 *
2319 * Returns:
2320 * Condition code
2321 *
2322 * Arguments:
2323 * bp - pointer to board information
2324 *
2325 * Functional Description:
2326 * The command request and response buffers are posted to the adapter in the manner
2327 * described in the PDQ Port Specification:
2328 *
2329 * 1. Command Response Buffer is posted to adapter.
2330 * 2. Command Request Buffer is posted to adapter.
2331 * 3. Command Request consumer index is polled until it indicates that request
2332 * buffer has been DMA'd to adapter.
2333 * 4. Command Response consumer index is polled until it indicates that response
2334 * buffer has been DMA'd from adapter.
2335 *
2336 * This ordering ensures that a response buffer is already available for the firmware
2337 * to use once it's done processing the request buffer.
2338 *
2339 * Return Codes:
2340 * DFX_K_SUCCESS - DMA command succeeded
2341 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2342 * DFX_K_HW_TIMEOUT - DMA command timed out
2343 *
2344 * Assumptions:
2345 * Command request buffer has already been filled with desired DMA command.
2346 *
2347 * Side Effects:
2348 * None
2349 */
2352 {
2356 /* Make sure the adapter is in a state that we can issue the DMA command in */
2365 /* Put response buffer on the command response queue */
2371 /* Bump (and wrap) the producer index and write out to register */
2377 /* Put request buffer on the command request queue */
2383 /* Bump (and wrap) the producer index and write out to register */
2389 /*
2390 * Here we wait for the command request consumer index to be equal
2391 * to the producer, indicating that the adapter has DMAed the request.
2392 */
2395 {
2399 }
2403 /* Bump (and wrap) the completion index and write out to register */
2409 /*
2410 * Here we wait for the command response consumer index to be equal
2411 * to the producer, indicating that the adapter has DMAed the response.
2412 */
2415 {
2419 }
2423 /* Bump (and wrap) the completion index and write out to register */
2429 }
2431 \f
2432 /*
2433 * ========================
2434 * = dfx_hw_port_ctrl_req =
2435 * ========================
2436 *
2437 * Overview:
2438 * Sends PDQ port control command to adapter firmware
2439 *
2440 * Returns:
2441 * Host data register value in host_data if ptr is not NULL
2442 *
2443 * Arguments:
2444 * bp - pointer to board information
2445 * command - port control command
2446 * data_a - port data A register value
2447 * data_b - port data B register value
2448 * host_data - ptr to host data register value
2449 *
2450 * Functional Description:
2451 * Send generic port control command to adapter by writing
2452 * to various PDQ port registers, then polling for completion.
2453 *
2454 * Return Codes:
2455 * DFX_K_SUCCESS - port control command succeeded
2456 * DFX_K_HW_TIMEOUT - port control command timed out
2457 *
2458 * Assumptions:
2459 * None
2460 *
2461 * Side Effects:
2462 * None
2463 */
2467 PI_UINT32 command,
2468 PI_UINT32 data_a,
2469 PI_UINT32 data_b,
2470 PI_UINT32 *host_data
2471 )
2473 {
2477 /* Set Command Error bit in command longword */
2481 /* Issue port command to the adapter */
2487 /* Now wait for command to complete */
2491 else
2495 {
2500 }
2504 /*
2505 * If the address of host_data is non-zero, assume caller has supplied a
2506 * non NULL pointer, and return the contents of the HOST_DATA register in
2507 * it.
2508 */
2513 }
2515 \f
2516 /*
2517 * =====================
2518 * = dfx_hw_adap_reset =
2519 * =====================
2520 *
2521 * Overview:
2522 * Resets adapter
2523 *
2524 * Returns:
2525 * None
2526 *
2527 * Arguments:
2528 * bp - pointer to board information
2529 * type - type of reset to perform
2530 *
2531 * Functional Description:
2532 * Issue soft reset to adapter by writing to PDQ Port Reset
2533 * register. Use incoming reset type to tell adapter what
2534 * kind of reset operation to perform.
2535 *
2536 * Return Codes:
2537 * None
2538 *
2539 * Assumptions:
2540 * This routine merely issues a soft reset to the adapter.
2541 * It is expected that after this routine returns, the caller
2542 * will appropriately poll the Port Status register for the
2543 * adapter to enter the proper state.
2544 *
2545 * Side Effects:
2546 * Internal adapter registers are cleared.
2547 */
2551 PI_UINT32 type
2552 )
2554 {
2555 /* Set Reset type and assert reset */
2560 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2564 /* Deassert reset */
2567 }
2569 \f
2570 /*
2571 * ========================
2572 * = dfx_hw_adap_state_rd =
2573 * ========================
2574 *
2575 * Overview:
2576 * Returns current adapter state
2577 *
2578 * Returns:
2579 * Adapter state per PDQ Port Specification
2580 *
2581 * Arguments:
2582 * bp - pointer to board information
2583 *
2584 * Functional Description:
2585 * Reads PDQ Port Status register and returns adapter state.
2586 *
2587 * Return Codes:
2588 * None
2589 *
2590 * Assumptions:
2591 * None
2592 *
2593 * Side Effects:
2594 * None
2595 */
2598 {
2603 }
2605 \f
2606 /*
2607 * =====================
2608 * = dfx_hw_dma_uninit =
2609 * =====================
2610 *
2611 * Overview:
2612 * Brings adapter to DMA_UNAVAILABLE state
2613 *
2614 * Returns:
2615 * Condition code
2616 *
2617 * Arguments:
2618 * bp - pointer to board information
2619 * type - type of reset to perform
2620 *
2621 * Functional Description:
2622 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2623 * 1. Set reset type bit in Port Data A Register then reset adapter.
2624 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2625 *
2626 * Return Codes:
2627 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2628 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2629 *
2630 * Assumptions:
2631 * None
2632 *
2633 * Side Effects:
2634 * Internal adapter registers are cleared.
2635 */
2638 {
2641 /* Set reset type bit and reset adapter */
2645 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2648 {
2652 }
2656 }
2657 \f
2658 /*
2659 * Align an sk_buff to a boundary power of 2
2660 *
2661 */
2664 {
2666 u32 v;
2671 }
2673 \f
2674 /*
2675 * ================
2676 * = dfx_rcv_init =
2677 * ================
2678 *
2679 * Overview:
2680 * Produces buffers to adapter LLC Host receive descriptor block
2681 *
2682 * Returns:
2683 * None
2684 *
2685 * Arguments:
2686 * bp - pointer to board information
2687 * get_buffers - non-zero if buffers to be allocated
2688 *
2689 * Functional Description:
2690 * This routine can be called during dfx_adap_init() or during an adapter
2691 * reset. It initializes the descriptor block and produces all allocated
2692 * LLC Host queue receive buffers.
2693 *
2694 * Return Codes:
2695 * Return 0 on success or -ENOMEM if buffer allocation failed (when using
2696 * dynamic buffer allocation). If the buffer allocation failed, the
2697 * already allocated buffers will not be released and the caller should do
2698 * this.
2699 *
2700 * Assumptions:
2701 * The PDQ has been reset and the adapter and driver maintained Type 2
2702 * register indices are cleared.
2703 *
2704 * Side Effects:
2705 * Receive buffers are posted to the adapter LLC queue and the adapter
2706 * is notified.
2707 */
2710 {
2713 /*
2714 * Since each receive buffer is a single fragment of same length, initialize
2715 * first longword in each receive descriptor for entire LLC Host descriptor
2716 * block. Also initialize second longword in each receive descriptor with
2717 * physical address of receive buffer. We'll always allocate receive
2718 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2719 * block and produce new receive buffers by simply updating the receive
2720 * producer index.
2721 *
2722 * Assumptions:
2723 * To support all shipping versions of PDQ, the receive buffer size
2724 * must be mod 128 in length and the physical address must be 128 byte
2725 * aligned. In other words, bits 0-6 of the length and address must
2726 * be zero for the following descriptor field entries to be correct on
2727 * all PDQ-based boards. We guaranteed both requirements during
2728 * driver initialization when we allocated memory for the receive buffers.
2729 */
2732 #ifdef DYNAMIC_BUFFERS
2735 {
2741 /*
2742 * align to 128 bytes for compatibility with
2743 * the old EISA boards.
2744 */
2748 /*
2749 * p_rcv_buff_va is only used inside the
2750 * kernel so we put the skb pointer here.
2751 */
2753 }
2754 #else
2757 {
2760 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2762 }
2763 #endif
2764 }
2766 /* Update receive producer and Type 2 register */
2771 }
2773 \f
2774 /*
2775 * =========================
2776 * = dfx_rcv_queue_process =
2777 * =========================
2778 *
2779 * Overview:
2780 * Process received LLC frames.
2781 *
2782 * Returns:
2783 * None
2784 *
2785 * Arguments:
2786 * bp - pointer to board information
2787 *
2788 * Functional Description:
2789 * Received LLC frames are processed until there are no more consumed frames.
2790 * Once all frames are processed, the receive buffers are returned to the
2791 * adapter. Note that this algorithm fixes the length of time that can be spent
2792 * in this routine, because there are a fixed number of receive buffers to
2793 * process and buffers are not produced until this routine exits and returns
2794 * to the ISR.
2795 *
2796 * Return Codes:
2797 * None
2798 *
2799 * Assumptions:
2800 * None
2801 *
2802 * Side Effects:
2803 * None
2804 */
2807 DFX_board_t *bp
2808 )
2810 {
2816 /* Service all consumed LLC receive frames */
2820 {
2821 /* Process any errors */
2826 #ifdef DYNAMIC_BUFFERS
2828 #else
2830 #endif
2834 {
2837 else
2839 }
2840 else
2841 {
2844 /* The frame was received without errors - verify packet length */
2851 #ifdef DYNAMIC_BUFFERS
2867 #endif
2870 {
2874 }
2876 #ifndef DYNAMIC_BUFFERS
2878 #endif
2879 {
2880 /* Receive buffer allocated, pass receive packet up */
2883 }
2893 /* Update the rcv counters */
2898 }
2899 }
2900 }
2902 /*
2903 * Advance the producer (for recycling) and advance the completion
2904 * (for servicing received frames). Note that it is okay to
2905 * advance the producer without checking that it passes the
2906 * completion index because they are both advanced at the same
2907 * rate.
2908 */
2912 }
2913 }
2915 \f
2916 /*
2917 * =====================
2918 * = dfx_xmt_queue_pkt =
2919 * =====================
2920 *
2921 * Overview:
2922 * Queues packets for transmission
2923 *
2924 * Returns:
2925 * Condition code
2926 *
2927 * Arguments:
2928 * skb - pointer to sk_buff to queue for transmission
2929 * dev - pointer to device information
2930 *
2931 * Functional Description:
2932 * Here we assume that an incoming skb transmit request
2933 * is contained in a single physically contiguous buffer
2934 * in which the virtual address of the start of packet
2935 * (skb->data) can be converted to a physical address
2936 * by using virt_to_bus().
2937 *
2938 * Since the adapter architecture requires a three byte
2939 * packet request header to prepend the start of packet,
2940 * we'll write the three byte field immediately prior to
2941 * the FC byte. This assumption is valid because we've
2942 * ensured that dev->hard_header_len includes three pad
2943 * bytes. By posting a single fragment to the adapter,
2944 * we'll reduce the number of descriptor fetches and
2945 * bus traffic needed to send the request.
2946 *
2947 * Also, we can't free the skb until after it's been DMA'd
2948 * out by the adapter, so we'll queue it in the driver and
2949 * return it in dfx_xmt_done.
2950 *
2951 * Return Codes:
2952 * 0 - driver queued packet, link is unavailable, or skbuff was bad
2953 * 1 - caller should requeue the sk_buff for later transmission
2954 *
2955 * Assumptions:
2956 * First and foremost, we assume the incoming skb pointer
2957 * is NOT NULL and is pointing to a valid sk_buff structure.
2958 *
2959 * The outgoing packet is complete, starting with the
2960 * frame control byte including the last byte of data,
2961 * but NOT including the 4 byte CRC. We'll let the
2962 * adapter hardware generate and append the CRC.
2963 *
2964 * The entire packet is stored in one physically
2965 * contiguous buffer which is not cached and whose
2966 * 32-bit physical address can be determined.
2967 *
2968 * It's vital that this routine is NOT reentered for the
2969 * same board and that the OS is not in another section of
2970 * code (eg. dfx_int_common) for the same board on a
2971 * different thread.
2972 *
2973 * Side Effects:
2974 * None
2975 */
2980 )
2982 {
2991 /*
2992 * Verify that incoming transmit request is OK
2993 *
2994 * Note: The packet size check is consistent with other
2995 * Linux device drivers, although the correct packet
2996 * size should be verified before calling the
2997 * transmit routine.
2998 */
3001 {
3008 }
3009 /*
3010 * See if adapter link is available, if not, free buffer
3011 *
3012 * Note: If the link isn't available, free buffer and return 0
3013 * rather than tell the upper layer to requeue the packet.
3014 * The methodology here is that by the time the link
3015 * becomes available, the packet to be sent will be
3016 * fairly stale. By simply dropping the packet, the
3017 * higher layer protocols will eventually time out
3018 * waiting for response packets which it won't receive.
3019 */
3022 {
3025 else
3026 {
3031 }
3032 }
3036 /* Get the current producer and the next free xmt data descriptor */
3041 /*
3042 * Get pointer to auxiliary queue entry to contain information
3043 * for this packet.
3044 *
3045 * Note: The current xmt producer index will become the
3046 * current xmt completion index when we complete this
3047 * packet later on. So, we'll get the pointer to the
3048 * next auxiliary queue entry now before we bump the
3049 * producer index.
3050 */
3054 /* Write the three PRH bytes immediately before the FC byte */
3061 /*
3062 * Write the descriptor with buffer info and bump producer
3063 *
3064 * Note: Since we need to start DMA from the packet request
3065 * header, we'll add 3 bytes to the DMA buffer length,
3066 * and we'll determine the physical address of the
3067 * buffer from the PRH, not skb->data.
3068 *
3069 * Assumptions:
3070 * 1. Packet starts with the frame control (FC) byte
3071 * at skb->data.
3072 * 2. The 4-byte CRC is not appended to the buffer or
3073 * included in the length.
3074 * 3. Packet length (skb->len) is from FC to end of
3075 * data, inclusive.
3076 * 4. The packet length does not exceed the maximum
3077 * FDDI LLC frame length of 4491 bytes.
3078 * 5. The entire packet is contained in a physically
3079 * contiguous, non-cached, locked memory space
3080 * comprised of a single buffer pointed to by
3081 * skb->data.
3082 * 6. The physical address of the start of packet
3083 * can be determined from the virtual address
3084 * by using virt_to_bus() and is only 32-bits
3085 * wide.
3086 */
3088 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3091 /*
3092 * Verify that descriptor is actually available
3093 *
3094 * Note: If descriptor isn't available, return 1 which tells
3095 * the upper layer to requeue the packet for later
3096 * transmission.
3097 *
3098 * We need to ensure that the producer never reaches the
3099 * completion, except to indicate that the queue is empty.
3100 */
3103 {
3107 }
3109 /*
3110 * Save info for this packet for xmt done indication routine
3111 *
3112 * Normally, we'd save the producer index in the p_xmt_drv_descr
3113 * structure so that we'd have it handy when we complete this
3114 * packet later (in dfx_xmt_done). However, since the current
3115 * transmit architecture guarantees a single fragment for the
3116 * entire packet, we can simply bump the completion index by
3117 * one (1) for each completed packet.
3118 *
3119 * Note: If this assumption changes and we're presented with
3120 * an inconsistent number of transmit fragments for packet
3121 * data, we'll need to modify this code to save the current
3122 * transmit producer index.
3123 */
3127 /* Update Type 2 register */
3134 }
3136 \f
3137 /*
3138 * ================
3139 * = dfx_xmt_done =
3140 * ================
3141 *
3142 * Overview:
3143 * Processes all frames that have been transmitted.
3144 *
3145 * Returns:
3146 * None
3147 *
3148 * Arguments:
3149 * bp - pointer to board information
3150 *
3151 * Functional Description:
3152 * For all consumed transmit descriptors that have not
3153 * yet been completed, we'll free the skb we were holding
3154 * onto using dev_kfree_skb and bump the appropriate
3155 * counters.
3156 *
3157 * Return Codes:
3158 * None
3159 *
3160 * Assumptions:
3161 * The Type 2 register is not updated in this routine. It is
3162 * assumed that it will be updated in the ISR when dfx_xmt_done
3163 * returns.
3164 *
3165 * Side Effects:
3166 * None
3167 */
3170 {
3175 /* Service all consumed transmit frames */
3179 {
3180 /* Get pointer to the transmit driver descriptor block information */
3184 /* Increment transmit counters */
3189 /* Return skb to operating system */
3193 /*
3194 * Move to start of next packet by updating completion index
3195 *
3196 * Here we assume that a transmit packet request is always
3197 * serviced by posting one fragment. We can therefore
3198 * simplify the completion code by incrementing the
3199 * completion index by one. This code will need to be
3200 * modified if this assumption changes. See comments
3201 * in dfx_xmt_queue_pkt for more details.
3202 */
3205 freed++;
3206 }
3208 }
3210 \f
3211 /*
3212 * =================
3213 * = dfx_rcv_flush =
3214 * =================
3215 *
3216 * Overview:
3217 * Remove all skb's in the receive ring.
3218 *
3219 * Returns:
3220 * None
3221 *
3222 * Arguments:
3223 * bp - pointer to board information
3224 *
3225 * Functional Description:
3226 * Free's all the dynamically allocated skb's that are
3227 * currently attached to the device receive ring. This
3228 * function is typically only used when the device is
3229 * initialized or reinitialized.
3230 *
3231 * Return Codes:
3232 * None
3233 *
3234 * Side Effects:
3235 * None
3236 */
3237 #ifdef DYNAMIC_BUFFERS
3239 {
3244 {
3250 }
3252 }
3253 #else
3255 {
3256 }
3259 /*
3260 * =================
3261 * = dfx_xmt_flush =
3262 * =================
3263 *
3264 * Overview:
3265 * Processes all frames whether they've been transmitted
3266 * or not.
3267 *
3268 * Returns:
3269 * None
3270 *
3271 * Arguments:
3272 * bp - pointer to board information
3273 *
3274 * Functional Description:
3275 * For all produced transmit descriptors that have not
3276 * yet been completed, we'll free the skb we were holding
3277 * onto using dev_kfree_skb and bump the appropriate
3278 * counters. Of course, it's possible that some of
3279 * these transmit requests actually did go out, but we
3280 * won't make that distinction here. Finally, we'll
3281 * update the consumer index to match the producer.
3282 *
3283 * Return Codes:
3284 * None
3285 *
3286 * Assumptions:
3287 * This routine does NOT update the Type 2 register. It
3288 * is assumed that this routine is being called during a
3289 * transmit flush interrupt, or a shutdown or close routine.
3290 *
3291 * Side Effects:
3292 * None
3293 */
3296 {
3300 /* Flush all outstanding transmit frames */
3303 {
3304 /* Get pointer to the transmit driver descriptor block information */
3308 /* Return skb to operating system */
3312 /* Increment transmit error counter */
3316 /*
3317 * Move to start of next packet by updating completion index
3318 *
3319 * Here we assume that a transmit packet request is always
3320 * serviced by posting one fragment. We can therefore
3321 * simplify the completion code by incrementing the
3322 * completion index by one. This code will need to be
3323 * modified if this assumption changes. See comments
3324 * in dfx_xmt_queue_pkt for more details.
3325 */
3328 }
3330 /* Update the transmit consumer index in the consumer block */
3335 }
3338 {
3345 }
3348 {
3353 }
3358 };
3366 };
3373 {
3377 {
3385 }
3386 }
3389 {
3392 /* when a module, this is printed whether or not devices are found in probe */
3393 #ifdef MODULE
3395 #endif
3404 }
3407 {
3413 }
3419 \f
3420 /*
3421 * Local variables:
3422 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"
3423 * End:
3424 */