drivers/net/8390.h

   1 /* Generic NS8390 register definitions. */
   2 /* This file is part of Donald Becker's 8390 drivers, and is distributed
   3    under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
   4    Some of these names and comments originated from the Crynwr
   5    packet drivers, which are distributed under the GPL. */
   6
   7 #ifndef _8390_h
   8 #define _8390_h
   9
  10 #include <linux/config.h>
  11 #include <linux/if_ether.h>
  12 #include <linux/ioport.h>
  13 #include <linux/skbuff.h>
  14
  15 #define TX_2X_PAGES 12
  16 #define TX_1X_PAGES 6
  17
  18 /* Should always use two Tx slots to get back-to-back transmits. */
  19 #define EI_PINGPONG
  20
  21 #ifdef EI_PINGPONG
  22 #define TX_PAGES TX_2X_PAGES
  23 #else
  24 #define TX_PAGES TX_1X_PAGES
  25 #endif
  26
  27 #define ETHER_ADDR_LEN 6
  28
  29 /* The 8390 specific per-packet-header format. */
  30 struct e8390_pkt_hdr {
  31   unsigned char status; /* status */
  32   unsigned char next;   /* pointer to next packet. */
  33   unsigned short count; /* header + packet length in bytes */
  34 };
  35
  36 #ifdef notdef
  37 extern int ei_debug;
  38 #else
  39 #define ei_debug 1
  40 #endif
  41
  42 extern int ethdev_init(struct net_device *dev);
  43 extern void NS8390_init(struct net_device *dev, int startp);
  44 extern int ei_open(struct net_device *dev);
  45 extern int ei_close(struct net_device *dev);
  46 extern irqreturn_t ei_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  47
  48 /* You have one of these per-board */
  49 struct ei_device {
  50         const char *name;
  51         void (*reset_8390)(struct net_device *);
  52         void (*get_8390_hdr)(struct net_device *, struct e8390_pkt_hdr *, int);
  53         void (*block_output)(struct net_device *, int, const unsigned char *, int);
  54         void (*block_input)(struct net_device *, int, struct sk_buff *, int);
  55         unsigned long rmem_start;
  56         unsigned long rmem_end;
  57         unsigned char mcfilter[8];
  58         unsigned open:1;
  59         unsigned word16:1;              /* We have the 16-bit (vs 8-bit) version of the card. */
  60         unsigned bigendian:1;           /* 16-bit big endian mode. Do NOT */
  61                                         /* set this on random 8390 clones! */
  62         unsigned txing:1;               /* Transmit Active */
  63         unsigned irqlock:1;             /* 8390's intrs disabled when '1'. */
  64         unsigned dmaing:1;              /* Remote DMA Active */
  65         unsigned char tx_start_page, rx_start_page, stop_page;
  66         unsigned char current_page;     /* Read pointer in buffer  */
  67         unsigned char interface_num;    /* Net port (AUI, 10bT.) to use. */
  68         unsigned char txqueue;          /* Tx Packet buffer queue length. */
  69         short tx1, tx2;                 /* Packet lengths for ping-pong tx. */
  70         short lasttx;                   /* Alpha version consistency check. */
  71         unsigned char reg0;             /* Register '0' in a WD8013 */
  72         unsigned char reg5;             /* Register '5' in a WD8013 */
  73         unsigned char saved_irq;        /* Original dev->irq value. */
  74         struct net_device_stats stat;   /* The new statistics table. */
  75         u32 *reg_offset;                /* Register mapping table */
  76         spinlock_t page_lock;           /* Page register locks */
  77         unsigned long priv;             /* Private field to store bus IDs etc. */
  78 };
  79
  80 /* The maximum number of 8390 interrupt service routines called per IRQ. */
  81 #define MAX_SERVICE 12
  82
  83 /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
  84 #define TX_TIMEOUT (20*HZ/100)
  85
  86 #define ei_status (*(struct ei_device *)(dev->priv))
  87
  88 /* Some generic ethernet register configurations. */
  89 #define E8390_TX_IRQ_MASK       0xa     /* For register EN0_ISR */
  90 #define E8390_RX_IRQ_MASK       0x5
  91 #define E8390_RXCONFIG          0x4     /* EN0_RXCR: broadcasts, no multicast,errors */
  92 #define E8390_RXOFF             0x20    /* EN0_RXCR: Accept no packets */
  93 #define E8390_TXCONFIG          0x00    /* EN0_TXCR: Normal transmit mode */
  94 #define E8390_TXOFF             0x02    /* EN0_TXCR: Transmitter off */
  95
  96 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  97 #define E8390_STOP      0x01    /* Stop and reset the chip */
  98 #define E8390_START     0x02    /* Start the chip, clear reset */
  99 #define E8390_TRANS     0x04    /* Transmit a frame */
 100 #define E8390_RREAD     0x08    /* Remote read */
 101 #define E8390_RWRITE    0x10    /* Remote write  */
 102 #define E8390_NODMA     0x20    /* Remote DMA */
 103 #define E8390_PAGE0     0x00    /* Select page chip registers */
 104 #define E8390_PAGE1     0x40    /* using the two high-order bits */
 105 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
 106
 107 /*
 108  *      Only generate indirect loads given a machine that needs them.
 109  *      - removed AMIGA_PCMCIA from this list, handled as ISA io now
 110  */
 111
 112 #if defined(CONFIG_MAC) ||  \
 113     defined(CONFIG_ARIADNE2) || defined(CONFIG_ARIADNE2_MODULE) || \
 114     defined(CONFIG_HYDRA) || defined(CONFIG_HYDRA_MODULE)
 115 #define EI_SHIFT(x)     (ei_local->reg_offset[x])
 116 #undef inb
 117 #undef inb_p
 118 #undef outb
 119 #undef outb_p
 120
 121 #define inb(port)   in_8(port)
 122 #define outb(val,port)  out_8(port,val)
 123 #define inb_p(port)   in_8(port)
 124 #define outb_p(val,port)  out_8(port,val)
 125
 126 #elif defined(CONFIG_ARM_ETHERH) || defined(CONFIG_ARM_ETHERH_MODULE) || \
 127       defined(CONFIG_NET_CBUS)
 128 #define EI_SHIFT(x)     (ei_local->reg_offset[x])
 129 #else
 130 #define EI_SHIFT(x)     (x)
 131 #endif
 132
 133 #define E8390_CMD       EI_SHIFT(0x00)  /* The command register (for all pages) */
 134 /* Page 0 register offsets. */
 135 #define EN0_CLDALO      EI_SHIFT(0x01)  /* Low byte of current local dma addr  RD */
 136 #define EN0_STARTPG     EI_SHIFT(0x01)  /* Starting page of ring bfr WR */
 137 #define EN0_CLDAHI      EI_SHIFT(0x02)  /* High byte of current local dma addr  RD */
 138 #define EN0_STOPPG      EI_SHIFT(0x02)  /* Ending page +1 of ring bfr WR */
 139 #define EN0_BOUNDARY    EI_SHIFT(0x03)  /* Boundary page of ring bfr RD WR */
 140 #define EN0_TSR         EI_SHIFT(0x04)  /* Transmit status reg RD */
 141 #define EN0_TPSR        EI_SHIFT(0x04)  /* Transmit starting page WR */
 142 #define EN0_NCR         EI_SHIFT(0x05)  /* Number of collision reg RD */
 143 #define EN0_TCNTLO      EI_SHIFT(0x05)  /* Low  byte of tx byte count WR */
 144 #define EN0_FIFO        EI_SHIFT(0x06)  /* FIFO RD */
 145 #define EN0_TCNTHI      EI_SHIFT(0x06)  /* High byte of tx byte count WR */
 146 #define EN0_ISR         EI_SHIFT(0x07)  /* Interrupt status reg RD WR */
 147 #define EN0_CRDALO      EI_SHIFT(0x08)  /* low byte of current remote dma address RD */
 148 #define EN0_RSARLO      EI_SHIFT(0x08)  /* Remote start address reg 0 */
 149 #define EN0_CRDAHI      EI_SHIFT(0x09)  /* high byte, current remote dma address RD */
 150 #define EN0_RSARHI      EI_SHIFT(0x09)  /* Remote start address reg 1 */
 151 #define EN0_RCNTLO      EI_SHIFT(0x0a)  /* Remote byte count reg WR */
 152 #define EN0_RCNTHI      EI_SHIFT(0x0b)  /* Remote byte count reg WR */
 153 #define EN0_RSR         EI_SHIFT(0x0c)  /* rx status reg RD */
 154 #define EN0_RXCR        EI_SHIFT(0x0c)  /* RX configuration reg WR */
 155 #define EN0_TXCR        EI_SHIFT(0x0d)  /* TX configuration reg WR */
 156 #define EN0_COUNTER0    EI_SHIFT(0x0d)  /* Rcv alignment error counter RD */
 157 #define EN0_DCFG        EI_SHIFT(0x0e)  /* Data configuration reg WR */
 158 #define EN0_COUNTER1    EI_SHIFT(0x0e)  /* Rcv CRC error counter RD */
 159 #define EN0_IMR         EI_SHIFT(0x0f)  /* Interrupt mask reg WR */
 160 #define EN0_COUNTER2    EI_SHIFT(0x0f)  /* Rcv missed frame error counter RD */
 161
 162 /* Bits in EN0_ISR - Interrupt status register */
 163 #define ENISR_RX        0x01    /* Receiver, no error */
 164 #define ENISR_TX        0x02    /* Transmitter, no error */
 165 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
 166 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
 167 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
 168 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
 169 #define ENISR_RDC       0x40    /* remote dma complete */
 170 #define ENISR_RESET     0x80    /* Reset completed */
 171 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
 172
 173 /* Bits in EN0_DCFG - Data config register */
 174 #define ENDCFG_WTS      0x01    /* word transfer mode selection */
 175 #define ENDCFG_BOS      0x02    /* byte order selection */
 176
 177 /* Page 1 register offsets. */
 178 #define EN1_PHYS   EI_SHIFT(0x01)       /* This board's physical enet addr RD WR */
 179 #define EN1_PHYS_SHIFT(i)  EI_SHIFT(i+1) /* Get and set mac address */
 180 #define EN1_CURPAG EI_SHIFT(0x07)       /* Current memory page RD WR */
 181 #define EN1_MULT   EI_SHIFT(0x08)       /* Multicast filter mask array (8 bytes) RD WR */
 182 #define EN1_MULT_SHIFT(i)  EI_SHIFT(8+i) /* Get and set multicast filter */
 183
 184 /* Bits in received packet status byte and EN0_RSR*/
 185 #define ENRSR_RXOK      0x01    /* Received a good packet */
 186 #define ENRSR_CRC       0x02    /* CRC error */
 187 #define ENRSR_FAE       0x04    /* frame alignment error */
 188 #define ENRSR_FO        0x08    /* FIFO overrun */
 189 #define ENRSR_MPA       0x10    /* missed pkt */
 190 #define ENRSR_PHY       0x20    /* physical/multicast address */
 191 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 192 #define ENRSR_DEF       0x80    /* deferring */
 193
 194 /* Transmitted packet status, EN0_TSR. */
 195 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 196 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 197 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 198 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 199 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 200 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 201 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 202 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 203
 204 #endif /* _8390_h */