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[linux-2.6/linux-mips.git] / drivers / net / 8139too.c
blobaf7c1e4281ff00043f22ae3b4af086ffa4270b77
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 See 8139too.txt for more details.
91
92 */
93
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.26"
96
97
98 #include <linux/config.h>
99 #include <linux/module.h>
100 #include <linux/kernel.h>
101 #include <linux/compiler.h>
102 #include <linux/pci.h>
103 #include <linux/init.h>
104 #include <linux/ioport.h>
105 #include <linux/netdevice.h>
106 #include <linux/etherdevice.h>
107 #include <linux/rtnetlink.h>
108 #include <linux/delay.h>
109 #include <linux/ethtool.h>
110 #include <linux/mii.h>
111 #include <linux/completion.h>
112 #include <linux/crc32.h>
113 #include <asm/io.h>
114 #include <asm/uaccess.h>
115
116 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
117 #define PFX DRV_NAME ": "
118
119
120 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
121 #ifdef CONFIG_8139TOO_PIO
122 #define USE_IO_OPS 1
123 #endif
124
125 /* define to 1 to enable copious debugging info */
126 #undef RTL8139_DEBUG
127
128 /* define to 1 to disable lightweight runtime debugging checks */
129 #undef RTL8139_NDEBUG
130
131
132 #ifdef RTL8139_DEBUG
133 /* note: prints function name for you */
134 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
135 #else
136 # define DPRINTK(fmt, args...)
137 #endif
138
139 #ifdef RTL8139_NDEBUG
140 # define assert(expr) do {} while (0)
141 #else
142 # define assert(expr) \
143 if(!(expr)) { \
144 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
145 #expr,__FILE__,__FUNCTION__,__LINE__); \
146 }
147 #endif
148
149
150 /* A few user-configurable values. */
151 /* media options */
152 #define MAX_UNITS 8
153 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
154 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
155
156 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
157 static int max_interrupt_work = 20;
158
159 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
160 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
161 static int multicast_filter_limit = 32;
162
163 /* bitmapped message enable number */
164 static int debug = -1;
165
166 /* Size of the in-memory receive ring. */
167 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
168 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
169 #define RX_BUF_PAD 16
170 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
171 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
172
173 /* Number of Tx descriptor registers. */
174 #define NUM_TX_DESC 4
175
176 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
177 #define MAX_ETH_FRAME_SIZE 1536
178
179 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
180 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
181 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
182
183 /* PCI Tuning Parameters
184 Threshold is bytes transferred to chip before transmission starts. */
185 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
186
187 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
188 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
189 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
190 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
191 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
192
193 /* Operational parameters that usually are not changed. */
194 /* Time in jiffies before concluding the transmitter is hung. */
195 #define TX_TIMEOUT (6*HZ)
196
197
198 enum {
199 HAS_MII_XCVR = 0x010000,
200 HAS_CHIP_XCVR = 0x020000,
201 HAS_LNK_CHNG = 0x040000,
202 };
203
204 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
205 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
206 #define RTL_MIN_IO_SIZE 0x80
207 #define RTL8139B_IO_SIZE 256
208
209 #define RTL8129_CAPS HAS_MII_XCVR
210 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
211
212 typedef enum {
213 RTL8139 = 0,
214 RTL8139_CB,
215 SMC1211TX,
216 /*MPX5030,*/
217 DELTA8139,
218 ADDTRON8139,
219 DFE538TX,
220 DFE690TXD,
221 FE2000VX,
222 ALLIED8139,
223 RTL8129,
224 FNW3603TX,
225 FNW3800TX,
226 } board_t;
227
228
229 /* indexed by board_t, above */
230 static struct {
231 const char *name;
232 u32 hw_flags;
233 } board_info[] __devinitdata = {
234 { "RealTek RTL8139 Fast Ethernet", RTL8139_CAPS },
235 { "RealTek RTL8139B PCI/CardBus", RTL8139_CAPS },
236 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)", RTL8139_CAPS },
237 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)", RTL8139_CAPS },*/
238 { "Delta Electronics 8139 10/100BaseTX", RTL8139_CAPS },
239 { "Addtron Technolgy 8139 10/100BaseTX", RTL8139_CAPS },
240 { "D-Link DFE-538TX (RealTek RTL8139)", RTL8139_CAPS },
241 { "D-Link DFE-690TXD (RealTek RTL8139)", RTL8139_CAPS },
242 { "AboCom FE2000VX (RealTek RTL8139)", RTL8139_CAPS },
243 { "Allied Telesyn 8139 CardBus", RTL8139_CAPS },
244 { "RealTek RTL8129", RTL8129_CAPS },
245 { "Planex FNW-3603-TX 10/100 CardBus", RTL8139_CAPS },
246 { "Planex FNW-3800-TX 10/100 CardBus", RTL8139_CAPS },
247 };
248
249
250 static struct pci_device_id rtl8139_pci_tbl[] __devinitdata = {
251 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139_CB },
253 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
254 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
255 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
256 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
257 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE538TX },
258 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE690TXD },
259 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FE2000VX },
260 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ALLIED8139 },
261 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FNW3603TX },
262 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FNW3800TX },
263
264 #ifdef CONFIG_8139TOO_8129
265 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
266 #endif
267
268 /* some crazy cards report invalid vendor ids like
269 * 0x0001 here. The other ids are valid and constant,
270 * so we simply don't match on the main vendor id.
271 */
272 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
273 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, DFE538TX },
274 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, FE2000VX },
275
276 {0,}
277 };
278 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
279
280 static struct {
281 const char str[ETH_GSTRING_LEN];
282 } ethtool_stats_keys[] = {
283 { "early_rx" },
284 { "tx_buf_mapped" },
285 { "tx_timeouts" },
286 { "rx_lost_in_ring" },
287 };
288
289 /* The rest of these values should never change. */
290
291 /* Symbolic offsets to registers. */
292 enum RTL8139_registers {
293 MAC0 = 0, /* Ethernet hardware address. */
294 MAR0 = 8, /* Multicast filter. */
295 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
296 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
297 RxBuf = 0x30,
298 ChipCmd = 0x37,
299 RxBufPtr = 0x38,
300 RxBufAddr = 0x3A,
301 IntrMask = 0x3C,
302 IntrStatus = 0x3E,
303 TxConfig = 0x40,
304 ChipVersion = 0x43,
305 RxConfig = 0x44,
306 Timer = 0x48, /* A general-purpose counter. */
307 RxMissed = 0x4C, /* 24 bits valid, write clears. */
308 Cfg9346 = 0x50,
309 Config0 = 0x51,
310 Config1 = 0x52,
311 FlashReg = 0x54,
312 MediaStatus = 0x58,
313 Config3 = 0x59,
314 Config4 = 0x5A, /* absent on RTL-8139A */
315 HltClk = 0x5B,
316 MultiIntr = 0x5C,
317 TxSummary = 0x60,
318 BasicModeCtrl = 0x62,
319 BasicModeStatus = 0x64,
320 NWayAdvert = 0x66,
321 NWayLPAR = 0x68,
322 NWayExpansion = 0x6A,
323 /* Undocumented registers, but required for proper operation. */
324 FIFOTMS = 0x70, /* FIFO Control and test. */
325 CSCR = 0x74, /* Chip Status and Configuration Register. */
326 PARA78 = 0x78,
327 PARA7c = 0x7c, /* Magic transceiver parameter register. */
328 Config5 = 0xD8, /* absent on RTL-8139A */
329 };
330
331 enum ClearBitMasks {
332 MultiIntrClear = 0xF000,
333 ChipCmdClear = 0xE2,
334 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
335 };
336
337 enum ChipCmdBits {
338 CmdReset = 0x10,
339 CmdRxEnb = 0x08,
340 CmdTxEnb = 0x04,
341 RxBufEmpty = 0x01,
342 };
343
344 /* Interrupt register bits, using my own meaningful names. */
345 enum IntrStatusBits {
346 PCIErr = 0x8000,
347 PCSTimeout = 0x4000,
348 RxFIFOOver = 0x40,
349 RxUnderrun = 0x20,
350 RxOverflow = 0x10,
351 TxErr = 0x08,
352 TxOK = 0x04,
353 RxErr = 0x02,
354 RxOK = 0x01,
355
356 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
357 };
358
359 enum TxStatusBits {
360 TxHostOwns = 0x2000,
361 TxUnderrun = 0x4000,
362 TxStatOK = 0x8000,
363 TxOutOfWindow = 0x20000000,
364 TxAborted = 0x40000000,
365 TxCarrierLost = 0x80000000,
366 };
367 enum RxStatusBits {
368 RxMulticast = 0x8000,
369 RxPhysical = 0x4000,
370 RxBroadcast = 0x2000,
371 RxBadSymbol = 0x0020,
372 RxRunt = 0x0010,
373 RxTooLong = 0x0008,
374 RxCRCErr = 0x0004,
375 RxBadAlign = 0x0002,
376 RxStatusOK = 0x0001,
377 };
378
379 /* Bits in RxConfig. */
380 enum rx_mode_bits {
381 AcceptErr = 0x20,
382 AcceptRunt = 0x10,
383 AcceptBroadcast = 0x08,
384 AcceptMulticast = 0x04,
385 AcceptMyPhys = 0x02,
386 AcceptAllPhys = 0x01,
387 };
388
389 /* Bits in TxConfig. */
390 enum tx_config_bits {
391 TxIFG1 = (1 << 25), /* Interframe Gap Time */
392 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
393 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
394 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
395 TxClearAbt = (1 << 0), /* Clear abort (WO) */
396 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
397 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
398
399 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
400 };
401
402 /* Bits in Config1 */
403 enum Config1Bits {
404 Cfg1_PM_Enable = 0x01,
405 Cfg1_VPD_Enable = 0x02,
406 Cfg1_PIO = 0x04,
407 Cfg1_MMIO = 0x08,
408 LWAKE = 0x10, /* not on 8139, 8139A */
409 Cfg1_Driver_Load = 0x20,
410 Cfg1_LED0 = 0x40,
411 Cfg1_LED1 = 0x80,
412 SLEEP = (1 << 1), /* only on 8139, 8139A */
413 PWRDN = (1 << 0), /* only on 8139, 8139A */
414 };
415
416 /* Bits in Config3 */
417 enum Config3Bits {
418 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
419 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
420 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
421 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
422 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
423 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
424 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
425 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
426 };
427
428 /* Bits in Config4 */
429 enum Config4Bits {
430 LWPTN = (1 << 2), /* not on 8139, 8139A */
431 };
432
433 /* Bits in Config5 */
434 enum Config5Bits {
435 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
436 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
437 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
438 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
439 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
440 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
441 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
442 };
443
444 enum RxConfigBits {
445 /* rx fifo threshold */
446 RxCfgFIFOShift = 13,
447 RxCfgFIFONone = (7 << RxCfgFIFOShift),
448
449 /* Max DMA burst */
450 RxCfgDMAShift = 8,
451 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
452
453 /* rx ring buffer length */
454 RxCfgRcv8K = 0,
455 RxCfgRcv16K = (1 << 11),
456 RxCfgRcv32K = (1 << 12),
457 RxCfgRcv64K = (1 << 11) | (1 << 12),
458
459 /* Disable packet wrap at end of Rx buffer */
460 RxNoWrap = (1 << 7),
461 };
462
463
464 /* Twister tuning parameters from RealTek.
465 Completely undocumented, but required to tune bad links on some boards. */
466 enum CSCRBits {
467 CSCR_LinkOKBit = 0x0400,
468 CSCR_LinkChangeBit = 0x0800,
469 CSCR_LinkStatusBits = 0x0f000,
470 CSCR_LinkDownOffCmd = 0x003c0,
471 CSCR_LinkDownCmd = 0x0f3c0,
472 };
473
474
475 enum Cfg9346Bits {
476 Cfg9346_Lock = 0x00,
477 Cfg9346_Unlock = 0xC0,
478 };
479
480 #ifdef CONFIG_8139TOO_TUNE_TWISTER
481
482 enum TwisterParamVals {
483 PARA78_default = 0x78fa8388,
484 PARA7c_default = 0xcb38de43, /* param[0][3] */
485 PARA7c_xxx = 0xcb38de43,
486 };
487
488 static const unsigned long param[4][4] = {
489 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
490 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
491 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
492 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
493 };
494
495 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
496
497 typedef enum {
498 CH_8139 = 0,
499 CH_8139_K,
500 CH_8139A,
501 CH_8139B,
502 CH_8130,
503 CH_8139C,
504 } chip_t;
505
506 enum chip_flags {
507 HasHltClk = (1 << 0),
508 HasLWake = (1 << 1),
509 };
510
511
512 /* directly indexed by chip_t, above */
513 const static struct {
514 const char *name;
515 u8 version; /* from RTL8139C docs */
516 u32 RxConfigMask; /* should clear the bits supported by this chip */
517 u32 flags;
518 } rtl_chip_info[] = {
519 { "RTL-8139",
520 0x40,
521 0xf0fe0040, /* XXX copied from RTL8139A, verify */
522 HasHltClk,
523 },
524
525 { "RTL-8139 rev K",
526 0x60,
527 0xf0fe0040,
528 HasHltClk,
529 },
530
531 { "RTL-8139A",
532 0x70,
533 0xf0fe0040,
534 HasHltClk, /* XXX undocumented? */
535 },
536
537 { "RTL-8139B",
538 0x78,
539 0xf0fc0040,
540 HasLWake,
541 },
542
543 { "RTL-8130",
544 0x7C,
545 0xf0fe0040, /* XXX copied from RTL8139A, verify */
546 HasLWake,
547 },
548
549 { "RTL-8139C",
550 0x74,
551 0xf0fc0040, /* XXX copied from RTL8139B, verify */
552 HasLWake,
553 },
554
555 };
556
557 struct rtl_extra_stats {
558 unsigned long early_rx;
559 unsigned long tx_buf_mapped;
560 unsigned long tx_timeouts;
561 unsigned long rx_lost_in_ring;
562 };
563
564 struct rtl8139_private {
565 void *mmio_addr;
566 int drv_flags;
567 struct pci_dev *pci_dev;
568 struct net_device_stats stats;
569 unsigned char *rx_ring;
570 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
571 unsigned int tx_flag;
572 unsigned long cur_tx;
573 unsigned long dirty_tx;
574 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
575 unsigned char *tx_bufs; /* Tx bounce buffer region. */
576 dma_addr_t rx_ring_dma;
577 dma_addr_t tx_bufs_dma;
578 signed char phys[4]; /* MII device addresses. */
579 char twistie, twist_row, twist_col; /* Twister tune state. */
580 unsigned int default_port:4; /* Last dev->if_port value. */
581 spinlock_t lock;
582 chip_t chipset;
583 pid_t thr_pid;
584 wait_queue_head_t thr_wait;
585 struct completion thr_exited;
586 u32 rx_config;
587 struct rtl_extra_stats xstats;
588 int time_to_die;
589 struct mii_if_info mii;
590 unsigned int regs_len;
591 };
592
593 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
594 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
595 MODULE_LICENSE("GPL");
596
597 MODULE_PARM (multicast_filter_limit, "i");
598 MODULE_PARM (max_interrupt_work, "i");
599 MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");
600 MODULE_PARM (full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
601 MODULE_PARM (debug, "i");
602 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
603 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
604 MODULE_PARM_DESC (max_interrupt_work, "8139too maximum events handled per interrupt");
605 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
606 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
607
608 static int read_eeprom (void *ioaddr, int location, int addr_len);
609 static int rtl8139_open (struct net_device *dev);
610 static int mdio_read (struct net_device *dev, int phy_id, int location);
611 static void mdio_write (struct net_device *dev, int phy_id, int location,
612 int val);
613 static int rtl8139_thread (void *data);
614 static void rtl8139_tx_timeout (struct net_device *dev);
615 static void rtl8139_init_ring (struct net_device *dev);
616 static int rtl8139_start_xmit (struct sk_buff *skb,
617 struct net_device *dev);
618 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
619 struct pt_regs *regs);
620 static int rtl8139_close (struct net_device *dev);
621 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
622 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
623 static void rtl8139_set_rx_mode (struct net_device *dev);
624 static void __set_rx_mode (struct net_device *dev);
625 static void rtl8139_hw_start (struct net_device *dev);
626
627 #ifdef USE_IO_OPS
628
629 #define RTL_R8(reg) inb (((unsigned long)ioaddr) + (reg))
630 #define RTL_R16(reg) inw (((unsigned long)ioaddr) + (reg))
631 #define RTL_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
632 #define RTL_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
633 #define RTL_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
634 #define RTL_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
635 #define RTL_W8_F RTL_W8
636 #define RTL_W16_F RTL_W16
637 #define RTL_W32_F RTL_W32
638 #undef readb
639 #undef readw
640 #undef readl
641 #undef writeb
642 #undef writew
643 #undef writel
644 #define readb(addr) inb((unsigned long)(addr))
645 #define readw(addr) inw((unsigned long)(addr))
646 #define readl(addr) inl((unsigned long)(addr))
647 #define writeb(val,addr) outb((val),(unsigned long)(addr))
648 #define writew(val,addr) outw((val),(unsigned long)(addr))
649 #define writel(val,addr) outl((val),(unsigned long)(addr))
650
651 #else
652
653 /* write MMIO register, with flush */
654 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
655 #define RTL_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
656 #define RTL_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
657 #define RTL_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
658
659
660 #define MMIO_FLUSH_AUDIT_COMPLETE 1
661 #if MMIO_FLUSH_AUDIT_COMPLETE
662
663 /* write MMIO register */
664 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
665 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
666 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
667
668 #else
669
670 /* write MMIO register, then flush */
671 #define RTL_W8 RTL_W8_F
672 #define RTL_W16 RTL_W16_F
673 #define RTL_W32 RTL_W32_F
674
675 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
676
677 /* read MMIO register */
678 #define RTL_R8(reg) readb (ioaddr + (reg))
679 #define RTL_R16(reg) readw (ioaddr + (reg))
680 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
681
682 #endif /* USE_IO_OPS */
683
684
685 static const u16 rtl8139_intr_mask =
686 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
687 TxErr | TxOK | RxErr | RxOK;
688
689 static const unsigned int rtl8139_rx_config =
690 RxCfgRcv32K | RxNoWrap |
691 (RX_FIFO_THRESH << RxCfgFIFOShift) |
692 (RX_DMA_BURST << RxCfgDMAShift);
693
694 static const unsigned int rtl8139_tx_config =
695 (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
696
697 static void __rtl8139_cleanup_dev (struct net_device *dev)
698 {
699 struct rtl8139_private *tp;
700 struct pci_dev *pdev;
701
702 assert (dev != NULL);
703 assert (dev->priv != NULL);
704
705 tp = dev->priv;
706 assert (tp->pci_dev != NULL);
707 pdev = tp->pci_dev;
708
709 #ifndef USE_IO_OPS
710 if (tp->mmio_addr)
711 iounmap (tp->mmio_addr);
712 #endif /* !USE_IO_OPS */
713
714 /* it's ok to call this even if we have no regions to free */
715 pci_release_regions (pdev);
716
717 #ifndef RTL8139_NDEBUG
718 /* poison memory before freeing */
719 memset (dev, 0xBC,
720 sizeof (struct net_device) +
721 sizeof (struct rtl8139_private));
722 #endif /* RTL8139_NDEBUG */
723
724 kfree (dev);
725
726 pci_set_drvdata (pdev, NULL);
727 }
728
729
730 static void rtl8139_chip_reset (void *ioaddr)
731 {
732 int i;
733
734 /* Soft reset the chip. */
735 RTL_W8 (ChipCmd, CmdReset);
736
737 /* Check that the chip has finished the reset. */
738 for (i = 1000; i > 0; i--) {
739 barrier();
740 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
741 break;
742 udelay (10);
743 }
744 }
745
746
747 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
748 struct net_device **dev_out)
749 {
750 void *ioaddr;
751 struct net_device *dev;
752 struct rtl8139_private *tp;
753 u8 tmp8;
754 int rc;
755 unsigned int i;
756 u32 pio_start, pio_end, pio_flags, pio_len;
757 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
758 u32 tmp;
759
760 assert (pdev != NULL);
761
762 *dev_out = NULL;
763
764 /* dev and dev->priv zeroed in alloc_etherdev */
765 dev = alloc_etherdev (sizeof (*tp));
766 if (dev == NULL) {
767 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pdev->slot_name);
768 return -ENOMEM;
769 }
770 SET_MODULE_OWNER(dev);
771 SET_NETDEV_DEV(dev, &pdev->dev);
772
773 tp = dev->priv;
774 tp->pci_dev = pdev;
775
776 /* enable device (incl. PCI PM wakeup and hotplug setup) */
777 rc = pci_enable_device (pdev);
778 if (rc)
779 goto err_out;
780
781 pio_start = pci_resource_start (pdev, 0);
782 pio_end = pci_resource_end (pdev, 0);
783 pio_flags = pci_resource_flags (pdev, 0);
784 pio_len = pci_resource_len (pdev, 0);
785
786 mmio_start = pci_resource_start (pdev, 1);
787 mmio_end = pci_resource_end (pdev, 1);
788 mmio_flags = pci_resource_flags (pdev, 1);
789 mmio_len = pci_resource_len (pdev, 1);
790
791 /* set this immediately, we need to know before
792 * we talk to the chip directly */
793 DPRINTK("PIO region size == 0x%02X\n", pio_len);
794 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
795
796 #ifdef USE_IO_OPS
797 /* make sure PCI base addr 0 is PIO */
798 if (!(pio_flags & IORESOURCE_IO)) {
799 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pdev->slot_name);
800 rc = -ENODEV;
801 goto err_out;
802 }
803 /* check for weird/broken PCI region reporting */
804 if (pio_len < RTL_MIN_IO_SIZE) {
805 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pdev->slot_name);
806 rc = -ENODEV;
807 goto err_out;
808 }
809 #else
810 /* make sure PCI base addr 1 is MMIO */
811 if (!(mmio_flags & IORESOURCE_MEM)) {
812 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pdev->slot_name);
813 rc = -ENODEV;
814 goto err_out;
815 }
816 if (mmio_len < RTL_MIN_IO_SIZE) {
817 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pdev->slot_name);
818 rc = -ENODEV;
819 goto err_out;
820 }
821 #endif
822
823 rc = pci_request_regions (pdev, "8139too");
824 if (rc)
825 goto err_out;
826
827 /* enable PCI bus-mastering */
828 pci_set_master (pdev);
829
830 #ifdef USE_IO_OPS
831 ioaddr = (void *) pio_start;
832 dev->base_addr = pio_start;
833 tp->mmio_addr = ioaddr;
834 tp->regs_len = pio_len;
835 #else
836 /* ioremap MMIO region */
837 ioaddr = ioremap (mmio_start, mmio_len);
838 if (ioaddr == NULL) {
839 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pdev->slot_name);
840 rc = -EIO;
841 goto err_out;
842 }
843 dev->base_addr = (long) ioaddr;
844 tp->mmio_addr = ioaddr;
845 tp->regs_len = mmio_len;
846 #endif /* USE_IO_OPS */
847
848 /* Bring old chips out of low-power mode. */
849 RTL_W8 (HltClk, 'R');
850
851 /* check for missing/broken hardware */
852 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
853 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
854 pdev->slot_name);
855 rc = -EIO;
856 goto err_out;
857 }
858
859 /* identify chip attached to board */
860 tmp = RTL_R8 (ChipVersion);
861 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
862 if (tmp == rtl_chip_info[i].version) {
863 tp->chipset = i;
864 goto match;
865 }
866
867 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
868 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
869 pdev->slot_name);
870 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pdev->slot_name, RTL_R32 (TxConfig));
871 tp->chipset = 0;
872
873 match:
874 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
875 tmp,
876 tp->chipset,
877 rtl_chip_info[tp->chipset].name);
878
879 if (tp->chipset >= CH_8139B) {
880 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
881 DPRINTK("PCI PM wakeup\n");
882 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
883 (tmp8 & LWAKE))
884 new_tmp8 &= ~LWAKE;
885 new_tmp8 |= Cfg1_PM_Enable;
886 if (new_tmp8 != tmp8) {
887 RTL_W8 (Cfg9346, Cfg9346_Unlock);
888 RTL_W8 (Config1, tmp8);
889 RTL_W8 (Cfg9346, Cfg9346_Lock);
890 }
891 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
892 tmp8 = RTL_R8 (Config4);
893 if (tmp8 & LWPTN)
894 RTL_W8 (Config4, tmp8 & ~LWPTN);
895 }
896 } else {
897 DPRINTK("Old chip wakeup\n");
898 tmp8 = RTL_R8 (Config1);
899 tmp8 &= ~(SLEEP | PWRDN);
900 RTL_W8 (Config1, tmp8);
901 }
902
903 rtl8139_chip_reset (ioaddr);
904
905 *dev_out = dev;
906 return 0;
907
908 err_out:
909 __rtl8139_cleanup_dev (dev);
910 return rc;
911 }
912
913
914 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
915 const struct pci_device_id *ent)
916 {
917 struct net_device *dev = NULL;
918 struct rtl8139_private *tp;
919 int i, addr_len, option;
920 void *ioaddr;
921 static int board_idx = -1;
922 u8 pci_rev;
923
924 assert (pdev != NULL);
925 assert (ent != NULL);
926
927 board_idx++;
928
929 /* when we're built into the kernel, the driver version message
930 * is only printed if at least one 8139 board has been found
931 */
932 #ifndef MODULE
933 {
934 static int printed_version;
935 if (!printed_version++)
936 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
937 }
938 #endif
939
940 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
941
942 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
943 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
944 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
945 pdev->slot_name, pdev->vendor, pdev->device, pci_rev);
946 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
947 }
948
949 i = rtl8139_init_board (pdev, &dev);
950 if (i < 0)
951 return i;
952
953 tp = dev->priv;
954 ioaddr = tp->mmio_addr;
955
956 assert (ioaddr != NULL);
957 assert (dev != NULL);
958 assert (tp != NULL);
959
960 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
961 for (i = 0; i < 3; i++)
962 ((u16 *) (dev->dev_addr))[i] =
963 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
964
965 /* The Rtl8139-specific entries in the device structure. */
966 dev->open = rtl8139_open;
967 dev->hard_start_xmit = rtl8139_start_xmit;
968 dev->stop = rtl8139_close;
969 dev->get_stats = rtl8139_get_stats;
970 dev->set_multicast_list = rtl8139_set_rx_mode;
971 dev->do_ioctl = netdev_ioctl;
972 dev->tx_timeout = rtl8139_tx_timeout;
973 dev->watchdog_timeo = TX_TIMEOUT;
974
975 /* note: the hardware is not capable of sg/csum/highdma, however
976 * through the use of skb_copy_and_csum_dev we enable these
977 * features
978 */
979 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
980
981 dev->irq = pdev->irq;
982
983 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
984 tp = dev->priv;
985
986 /* note: tp->chipset set in rtl8139_init_board */
987 tp->drv_flags = board_info[ent->driver_data].hw_flags;
988 tp->mmio_addr = ioaddr;
989 spin_lock_init (&tp->lock);
990 init_waitqueue_head (&tp->thr_wait);
991 init_completion (&tp->thr_exited);
992 tp->mii.dev = dev;
993 tp->mii.mdio_read = mdio_read;
994 tp->mii.mdio_write = mdio_write;
995 tp->mii.phy_id_mask = 0x3f;
996 tp->mii.reg_num_mask = 0x1f;
997
998 /* dev is fully set up and ready to use now */
999 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1000 i = register_netdev (dev);
1001 if (i) goto err_out;
1002
1003 pci_set_drvdata (pdev, dev);
1004
1005 printk (KERN_INFO "%s: %s at 0x%lx, "
1006 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1007 "IRQ %d\n",
1008 dev->name,
1009 board_info[ent->driver_data].name,
1010 dev->base_addr,
1011 dev->dev_addr[0], dev->dev_addr[1],
1012 dev->dev_addr[2], dev->dev_addr[3],
1013 dev->dev_addr[4], dev->dev_addr[5],
1014 dev->irq);
1015
1016 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1017 dev->name, rtl_chip_info[tp->chipset].name);
1018
1019 /* Find the connected MII xcvrs.
1020 Doing this in open() would allow detecting external xcvrs later, but
1021 takes too much time. */
1022 #ifdef CONFIG_8139TOO_8129
1023 if (tp->drv_flags & HAS_MII_XCVR) {
1024 int phy, phy_idx = 0;
1025 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1026 int mii_status = mdio_read(dev, phy, 1);
1027 if (mii_status != 0xffff && mii_status != 0x0000) {
1028 u16 advertising = mdio_read(dev, phy, 4);
1029 tp->phys[phy_idx++] = phy;
1030 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1031 "advertising %4.4x.\n",
1032 dev->name, phy, mii_status, advertising);
1033 }
1034 }
1035 if (phy_idx == 0) {
1036 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1037 "transceiver.\n",
1038 dev->name);
1039 tp->phys[0] = 32;
1040 }
1041 } else
1042 #endif
1043 tp->phys[0] = 32;
1044 tp->mii.phy_id = tp->phys[0];
1045
1046 /* The lower four bits are the media type. */
1047 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1048 if (option > 0) {
1049 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1050 tp->default_port = option & 0xFF;
1051 if (tp->default_port)
1052 tp->mii.force_media = 1;
1053 }
1054 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1055 tp->mii.full_duplex = full_duplex[board_idx];
1056 if (tp->mii.full_duplex) {
1057 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1058 /* Changing the MII-advertised media because might prevent
1059 re-connection. */
1060 tp->mii.force_media = 1;
1061 }
1062 if (tp->default_port) {
1063 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1064 (option & 0x20 ? 100 : 10),
1065 (option & 0x10 ? "full" : "half"));
1066 mdio_write(dev, tp->phys[0], 0,
1067 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1068 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1069 }
1070
1071 /* Put the chip into low-power mode. */
1072 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1073 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1074
1075 return 0;
1076
1077 err_out:
1078 __rtl8139_cleanup_dev (dev);
1079 return i;
1080 }
1081
1082
1083 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1084 {
1085 struct net_device *dev = pci_get_drvdata (pdev);
1086 struct rtl8139_private *np;
1087
1088 assert (dev != NULL);
1089 np = dev->priv;
1090 assert (np != NULL);
1091
1092 unregister_netdev (dev);
1093
1094 __rtl8139_cleanup_dev (dev);
1095 }
1096
1097
1098 /* Serial EEPROM section. */
1099
1100 /* EEPROM_Ctrl bits. */
1101 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1102 #define EE_CS 0x08 /* EEPROM chip select. */
1103 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1104 #define EE_WRITE_0 0x00
1105 #define EE_WRITE_1 0x02
1106 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1107 #define EE_ENB (0x80 | EE_CS)
1108
1109 /* Delay between EEPROM clock transitions.
1110 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1111 */
1112
1113 #define eeprom_delay() readl(ee_addr)
1114
1115 /* The EEPROM commands include the alway-set leading bit. */
1116 #define EE_WRITE_CMD (5)
1117 #define EE_READ_CMD (6)
1118 #define EE_ERASE_CMD (7)
1119
1120 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
1121 {
1122 int i;
1123 unsigned retval = 0;
1124 void *ee_addr = ioaddr + Cfg9346;
1125 int read_cmd = location | (EE_READ_CMD << addr_len);
1126
1127 writeb (EE_ENB & ~EE_CS, ee_addr);
1128 writeb (EE_ENB, ee_addr);
1129 eeprom_delay ();
1130
1131 /* Shift the read command bits out. */
1132 for (i = 4 + addr_len; i >= 0; i--) {
1133 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1134 writeb (EE_ENB | dataval, ee_addr);
1135 eeprom_delay ();
1136 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1137 eeprom_delay ();
1138 }
1139 writeb (EE_ENB, ee_addr);
1140 eeprom_delay ();
1141
1142 for (i = 16; i > 0; i--) {
1143 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1144 eeprom_delay ();
1145 retval =
1146 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1147 0);
1148 writeb (EE_ENB, ee_addr);
1149 eeprom_delay ();
1150 }
1151
1152 /* Terminate the EEPROM access. */
1153 writeb (~EE_CS, ee_addr);
1154 eeprom_delay ();
1155
1156 return retval;
1157 }
1158
1159 /* MII serial management: mostly bogus for now. */
1160 /* Read and write the MII management registers using software-generated
1161 serial MDIO protocol.
1162 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1163 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1164 "overclocking" issues. */
1165 #define MDIO_DIR 0x80
1166 #define MDIO_DATA_OUT 0x04
1167 #define MDIO_DATA_IN 0x02
1168 #define MDIO_CLK 0x01
1169 #define MDIO_WRITE0 (MDIO_DIR)
1170 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1171
1172 #define mdio_delay(mdio_addr) readb(mdio_addr)
1173
1174
1175 static char mii_2_8139_map[8] = {
1176 BasicModeCtrl,
1177 BasicModeStatus,
1178 0,
1179 0,
1180 NWayAdvert,
1181 NWayLPAR,
1182 NWayExpansion,
1183 0
1184 };
1185
1186
1187 #ifdef CONFIG_8139TOO_8129
1188 /* Syncronize the MII management interface by shifting 32 one bits out. */
1189 static void mdio_sync (void *mdio_addr)
1190 {
1191 int i;
1192
1193 for (i = 32; i >= 0; i--) {
1194 writeb (MDIO_WRITE1, mdio_addr);
1195 mdio_delay (mdio_addr);
1196 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
1197 mdio_delay (mdio_addr);
1198 }
1199 }
1200 #endif
1201
1202 static int mdio_read (struct net_device *dev, int phy_id, int location)
1203 {
1204 struct rtl8139_private *tp = dev->priv;
1205 int retval = 0;
1206 #ifdef CONFIG_8139TOO_8129
1207 void *mdio_addr = tp->mmio_addr + Config4;
1208 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1209 int i;
1210 #endif
1211
1212 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1213 return location < 8 && mii_2_8139_map[location] ?
1214 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1215 }
1216
1217 #ifdef CONFIG_8139TOO_8129
1218 mdio_sync (mdio_addr);
1219 /* Shift the read command bits out. */
1220 for (i = 15; i >= 0; i--) {
1221 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1222
1223 writeb (MDIO_DIR | dataval, mdio_addr);
1224 mdio_delay (mdio_addr);
1225 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1226 mdio_delay (mdio_addr);
1227 }
1228
1229 /* Read the two transition, 16 data, and wire-idle bits. */
1230 for (i = 19; i > 0; i--) {
1231 writeb (0, mdio_addr);
1232 mdio_delay (mdio_addr);
1233 retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
1234 writeb (MDIO_CLK, mdio_addr);
1235 mdio_delay (mdio_addr);
1236 }
1237 #endif
1238
1239 return (retval >> 1) & 0xffff;
1240 }
1241
1242
1243 static void mdio_write (struct net_device *dev, int phy_id, int location,
1244 int value)
1245 {
1246 struct rtl8139_private *tp = dev->priv;
1247 #ifdef CONFIG_8139TOO_8129
1248 void *mdio_addr = tp->mmio_addr + Config4;
1249 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1250 int i;
1251 #endif
1252
1253 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1254 void *ioaddr = tp->mmio_addr;
1255 if (location == 0) {
1256 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1257 RTL_W16 (BasicModeCtrl, value);
1258 RTL_W8 (Cfg9346, Cfg9346_Lock);
1259 } else if (location < 8 && mii_2_8139_map[location])
1260 RTL_W16 (mii_2_8139_map[location], value);
1261 return;
1262 }
1263
1264 #ifdef CONFIG_8139TOO_8129
1265 mdio_sync (mdio_addr);
1266
1267 /* Shift the command bits out. */
1268 for (i = 31; i >= 0; i--) {
1269 int dataval =
1270 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1271 writeb (dataval, mdio_addr);
1272 mdio_delay (mdio_addr);
1273 writeb (dataval | MDIO_CLK, mdio_addr);
1274 mdio_delay (mdio_addr);
1275 }
1276 /* Clear out extra bits. */
1277 for (i = 2; i > 0; i--) {
1278 writeb (0, mdio_addr);
1279 mdio_delay (mdio_addr);
1280 writeb (MDIO_CLK, mdio_addr);
1281 mdio_delay (mdio_addr);
1282 }
1283 #endif
1284 }
1285
1286
1287 static int rtl8139_open (struct net_device *dev)
1288 {
1289 struct rtl8139_private *tp = dev->priv;
1290 int retval;
1291 #ifdef RTL8139_DEBUG
1292 void *ioaddr = tp->mmio_addr;
1293 #endif
1294
1295 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1296 if (retval)
1297 return retval;
1298
1299 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1300 &tp->tx_bufs_dma);
1301 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1302 &tp->rx_ring_dma);
1303 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1304 free_irq(dev->irq, dev);
1305
1306 if (tp->tx_bufs)
1307 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1308 tp->tx_bufs, tp->tx_bufs_dma);
1309 if (tp->rx_ring)
1310 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1311 tp->rx_ring, tp->rx_ring_dma);
1312
1313 return -ENOMEM;
1314
1315 }
1316
1317 tp->mii.full_duplex = tp->mii.force_media;
1318 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1319 tp->twistie = (tp->chipset == CH_8139_K) ? 1 : 0;
1320 tp->time_to_die = 0;
1321
1322 rtl8139_init_ring (dev);
1323 rtl8139_hw_start (dev);
1324
1325 DPRINTK ("%s: rtl8139_open() ioaddr %#lx IRQ %d"
1326 " GP Pins %2.2x %s-duplex.\n",
1327 dev->name, pci_resource_start (tp->pci_dev, 1),
1328 dev->irq, RTL_R8 (MediaStatus),
1329 tp->mii.full_duplex ? "full" : "half");
1330
1331 tp->thr_pid = kernel_thread (rtl8139_thread, dev, CLONE_FS | CLONE_FILES);
1332 if (tp->thr_pid < 0)
1333 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1334 dev->name);
1335
1336 return 0;
1337 }
1338
1339
1340 static void rtl_check_media (struct net_device *dev)
1341 {
1342 struct rtl8139_private *tp = dev->priv;
1343
1344 if (tp->phys[0] >= 0) {
1345 u16 mii_lpa = mdio_read(dev, tp->phys[0], MII_LPA);
1346 if (mii_lpa == 0xffff)
1347 ; /* Not there */
1348 else if ((mii_lpa & LPA_100FULL) == LPA_100FULL
1349 || (mii_lpa & 0x00C0) == LPA_10FULL)
1350 tp->mii.full_duplex = 1;
1351
1352 printk (KERN_INFO"%s: Setting %s%s-duplex based on"
1353 " auto-negotiated partner ability %4.4x.\n",
1354 dev->name, mii_lpa == 0 ? "" :
1355 (mii_lpa & 0x0180) ? "100mbps " : "10mbps ",
1356 tp->mii.full_duplex ? "full" : "half", mii_lpa);
1357 }
1358 }
1359
1360 /* Start the hardware at open or resume. */
1361 static void rtl8139_hw_start (struct net_device *dev)
1362 {
1363 struct rtl8139_private *tp = dev->priv;
1364 void *ioaddr = tp->mmio_addr;
1365 u32 i;
1366 u8 tmp;
1367
1368 /* Bring old chips out of low-power mode. */
1369 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1370 RTL_W8 (HltClk, 'R');
1371
1372 rtl8139_chip_reset (ioaddr);
1373
1374 /* unlock Config[01234] and BMCR register writes */
1375 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1376 /* Restore our idea of the MAC address. */
1377 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1378 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1379
1380 /* Must enable Tx/Rx before setting transfer thresholds! */
1381 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1382
1383 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1384 RTL_W32 (RxConfig, tp->rx_config);
1385
1386 /* Check this value: the documentation for IFG contradicts ifself. */
1387 RTL_W32 (TxConfig, rtl8139_tx_config);
1388
1389 tp->cur_rx = 0;
1390
1391 rtl_check_media (dev);
1392
1393 if (tp->chipset >= CH_8139B) {
1394 /* Disable magic packet scanning, which is enabled
1395 * when PM is enabled in Config1. It can be reenabled
1396 * via ETHTOOL_SWOL if desired. */
1397 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1398 }
1399
1400 DPRINTK("init buffer addresses\n");
1401
1402 /* Lock Config[01234] and BMCR register writes */
1403 RTL_W8 (Cfg9346, Cfg9346_Lock);
1404
1405 /* init Rx ring buffer DMA address */
1406 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1407
1408 /* init Tx buffer DMA addresses */
1409 for (i = 0; i < NUM_TX_DESC; i++)
1410 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1411
1412 RTL_W32 (RxMissed, 0);
1413
1414 rtl8139_set_rx_mode (dev);
1415
1416 /* no early-rx interrupts */
1417 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1418
1419 /* make sure RxTx has started */
1420 tmp = RTL_R8 (ChipCmd);
1421 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1422 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1423
1424 /* Enable all known interrupts by setting the interrupt mask. */
1425 RTL_W16 (IntrMask, rtl8139_intr_mask);
1426
1427 netif_start_queue (dev);
1428 }
1429
1430
1431 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1432 static void rtl8139_init_ring (struct net_device *dev)
1433 {
1434 struct rtl8139_private *tp = dev->priv;
1435 int i;
1436
1437 tp->cur_rx = 0;
1438 tp->cur_tx = 0;
1439 tp->dirty_tx = 0;
1440
1441 for (i = 0; i < NUM_TX_DESC; i++)
1442 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1443 }
1444
1445
1446 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1447 static int next_tick = 3 * HZ;
1448
1449 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1450 static inline void rtl8139_tune_twister (struct net_device *dev,
1451 struct rtl8139_private *tp) {}
1452 #else
1453 static void rtl8139_tune_twister (struct net_device *dev,
1454 struct rtl8139_private *tp)
1455 {
1456 int linkcase;
1457 void *ioaddr = tp->mmio_addr;
1458
1459 /* This is a complicated state machine to configure the "twister" for
1460 impedance/echos based on the cable length.
1461 All of this is magic and undocumented.
1462 */
1463 switch (tp->twistie) {
1464 case 1:
1465 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1466 /* We have link beat, let us tune the twister. */
1467 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1468 tp->twistie = 2; /* Change to state 2. */
1469 next_tick = HZ / 10;
1470 } else {
1471 /* Just put in some reasonable defaults for when beat returns. */
1472 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1473 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1474 RTL_W32 (PARA78, PARA78_default);
1475 RTL_W32 (PARA7c, PARA7c_default);
1476 tp->twistie = 0; /* Bail from future actions. */
1477 }
1478 break;
1479 case 2:
1480 /* Read how long it took to hear the echo. */
1481 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1482 if (linkcase == 0x7000)
1483 tp->twist_row = 3;
1484 else if (linkcase == 0x3000)
1485 tp->twist_row = 2;
1486 else if (linkcase == 0x1000)
1487 tp->twist_row = 1;
1488 else
1489 tp->twist_row = 0;
1490 tp->twist_col = 0;
1491 tp->twistie = 3; /* Change to state 2. */
1492 next_tick = HZ / 10;
1493 break;
1494 case 3:
1495 /* Put out four tuning parameters, one per 100msec. */
1496 if (tp->twist_col == 0)
1497 RTL_W16 (FIFOTMS, 0);
1498 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1499 [(int) tp->twist_col]);
1500 next_tick = HZ / 10;
1501 if (++tp->twist_col >= 4) {
1502 /* For short cables we are done.
1503 For long cables (row == 3) check for mistune. */
1504 tp->twistie =
1505 (tp->twist_row == 3) ? 4 : 0;
1506 }
1507 break;
1508 case 4:
1509 /* Special case for long cables: check for mistune. */
1510 if ((RTL_R16 (CSCR) &
1511 CSCR_LinkStatusBits) == 0x7000) {
1512 tp->twistie = 0;
1513 break;
1514 } else {
1515 RTL_W32 (PARA7c, 0xfb38de03);
1516 tp->twistie = 5;
1517 next_tick = HZ / 10;
1518 }
1519 break;
1520 case 5:
1521 /* Retune for shorter cable (column 2). */
1522 RTL_W32 (FIFOTMS, 0x20);
1523 RTL_W32 (PARA78, PARA78_default);
1524 RTL_W32 (PARA7c, PARA7c_default);
1525 RTL_W32 (FIFOTMS, 0x00);
1526 tp->twist_row = 2;
1527 tp->twist_col = 0;
1528 tp->twistie = 3;
1529 next_tick = HZ / 10;
1530 break;
1531
1532 default:
1533 /* do nothing */
1534 break;
1535 }
1536 }
1537 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1538
1539
1540 static inline void rtl8139_thread_iter (struct net_device *dev,
1541 struct rtl8139_private *tp,
1542 void *ioaddr)
1543 {
1544 int mii_lpa;
1545
1546 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1547
1548 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1549 int duplex = (mii_lpa & LPA_100FULL)
1550 || (mii_lpa & 0x01C0) == 0x0040;
1551 if (tp->mii.full_duplex != duplex) {
1552 tp->mii.full_duplex = duplex;
1553
1554 if (mii_lpa) {
1555 printk (KERN_INFO
1556 "%s: Setting %s-duplex based on MII #%d link"
1557 " partner ability of %4.4x.\n",
1558 dev->name,
1559 tp->mii.full_duplex ? "full" : "half",
1560 tp->phys[0], mii_lpa);
1561 } else {
1562 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1563 dev->name);
1564 }
1565 #if 0
1566 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1567 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1568 RTL_W8 (Cfg9346, Cfg9346_Lock);
1569 #endif
1570 }
1571 }
1572
1573 next_tick = HZ * 60;
1574
1575 rtl8139_tune_twister (dev, tp);
1576
1577 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1578 dev->name, RTL_R16 (NWayLPAR));
1579 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1580 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1581 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1582 dev->name, RTL_R8 (Config0),
1583 RTL_R8 (Config1));
1584 }
1585
1586
1587 static int rtl8139_thread (void *data)
1588 {
1589 struct net_device *dev = data;
1590 struct rtl8139_private *tp = dev->priv;
1591 unsigned long timeout;
1592
1593 daemonize("%s", dev->name);
1594 allow_signal(SIGTERM);
1595
1596 while (1) {
1597 timeout = next_tick;
1598 do {
1599 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1600 } while (!signal_pending (current) && (timeout > 0));
1601
1602 if (signal_pending (current)) {
1603 flush_signals(current);
1604 }
1605
1606 if (tp->time_to_die)
1607 break;
1608
1609 rtnl_lock ();
1610 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1611 rtnl_unlock ();
1612 }
1613
1614 complete_and_exit (&tp->thr_exited, 0);
1615 }
1616
1617
1618 static void rtl8139_tx_clear (struct rtl8139_private *tp)
1619 {
1620 tp->cur_tx = 0;
1621 tp->dirty_tx = 0;
1622
1623 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1624 }
1625
1626
1627 static void rtl8139_tx_timeout (struct net_device *dev)
1628 {
1629 struct rtl8139_private *tp = dev->priv;
1630 void *ioaddr = tp->mmio_addr;
1631 int i;
1632 u8 tmp8;
1633 unsigned long flags;
1634
1635 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1636 "media %2.2x.\n", dev->name,
1637 RTL_R8 (ChipCmd),
1638 RTL_R16 (IntrStatus),
1639 RTL_R8 (MediaStatus));
1640
1641 tp->xstats.tx_timeouts++;
1642
1643 /* disable Tx ASAP, if not already */
1644 tmp8 = RTL_R8 (ChipCmd);
1645 if (tmp8 & CmdTxEnb)
1646 RTL_W8 (ChipCmd, CmdRxEnb);
1647
1648 /* Disable interrupts by clearing the interrupt mask. */
1649 RTL_W16 (IntrMask, 0x0000);
1650
1651 /* Emit info to figure out what went wrong. */
1652 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1653 dev->name, tp->cur_tx, tp->dirty_tx);
1654 for (i = 0; i < NUM_TX_DESC; i++)
1655 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1656 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1657 i == tp->dirty_tx % NUM_TX_DESC ?
1658 " (queue head)" : "");
1659
1660 /* Stop a shared interrupt from scavenging while we are. */
1661 spin_lock_irqsave (&tp->lock, flags);
1662 rtl8139_tx_clear (tp);
1663 spin_unlock_irqrestore (&tp->lock, flags);
1664
1665 /* ...and finally, reset everything */
1666 rtl8139_hw_start (dev);
1667
1668 netif_wake_queue (dev);
1669 }
1670
1671
1672 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1673 {
1674 struct rtl8139_private *tp = dev->priv;
1675 void *ioaddr = tp->mmio_addr;
1676 unsigned int entry;
1677 unsigned int len = skb->len;
1678
1679 /* Calculate the next Tx descriptor entry. */
1680 entry = tp->cur_tx % NUM_TX_DESC;
1681
1682 if (likely(len < TX_BUF_SIZE)) {
1683 if (len < ETH_ZLEN)
1684 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1685 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1686 dev_kfree_skb(skb);
1687 } else {
1688 dev_kfree_skb(skb);
1689 tp->stats.tx_dropped++;
1690 return 0;
1691 }
1692
1693 /* Note: the chip doesn't have auto-pad! */
1694 spin_lock_irq(&tp->lock);
1695 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1696 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1697
1698 dev->trans_start = jiffies;
1699
1700 tp->cur_tx++;
1701 wmb();
1702
1703 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1704 netif_stop_queue (dev);
1705 spin_unlock_irq(&tp->lock);
1706
1707 DPRINTK ("%s: Queued Tx packet size %u to slot %d.\n",
1708 dev->name, len, entry);
1709
1710 return 0;
1711 }
1712
1713
1714 static void rtl8139_tx_interrupt (struct net_device *dev,
1715 struct rtl8139_private *tp,
1716 void *ioaddr)
1717 {
1718 unsigned long dirty_tx, tx_left;
1719
1720 assert (dev != NULL);
1721 assert (tp != NULL);
1722 assert (ioaddr != NULL);
1723
1724 dirty_tx = tp->dirty_tx;
1725 tx_left = tp->cur_tx - dirty_tx;
1726 while (tx_left > 0) {
1727 int entry = dirty_tx % NUM_TX_DESC;
1728 int txstatus;
1729
1730 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1731
1732 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1733 break; /* It still hasn't been Txed */
1734
1735 /* Note: TxCarrierLost is always asserted at 100mbps. */
1736 if (txstatus & (TxOutOfWindow | TxAborted)) {
1737 /* There was an major error, log it. */
1738 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1739 dev->name, txstatus);
1740 tp->stats.tx_errors++;
1741 if (txstatus & TxAborted) {
1742 tp->stats.tx_aborted_errors++;
1743 RTL_W32 (TxConfig, TxClearAbt);
1744 RTL_W16 (IntrStatus, TxErr);
1745 wmb();
1746 }
1747 if (txstatus & TxCarrierLost)
1748 tp->stats.tx_carrier_errors++;
1749 if (txstatus & TxOutOfWindow)
1750 tp->stats.tx_window_errors++;
1751 } else {
1752 if (txstatus & TxUnderrun) {
1753 /* Add 64 to the Tx FIFO threshold. */
1754 if (tp->tx_flag < 0x00300000)
1755 tp->tx_flag += 0x00020000;
1756 tp->stats.tx_fifo_errors++;
1757 }
1758 tp->stats.collisions += (txstatus >> 24) & 15;
1759 tp->stats.tx_bytes += txstatus & 0x7ff;
1760 tp->stats.tx_packets++;
1761 }
1762
1763 dirty_tx++;
1764 tx_left--;
1765 }
1766
1767 #ifndef RTL8139_NDEBUG
1768 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1769 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1770 dev->name, dirty_tx, tp->cur_tx);
1771 dirty_tx += NUM_TX_DESC;
1772 }
1773 #endif /* RTL8139_NDEBUG */
1774
1775 /* only wake the queue if we did work, and the queue is stopped */
1776 if (tp->dirty_tx != dirty_tx) {
1777 tp->dirty_tx = dirty_tx;
1778 mb();
1779 if (netif_queue_stopped (dev))
1780 netif_wake_queue (dev);
1781 }
1782 }
1783
1784
1785 /* TODO: clean this up! Rx reset need not be this intensive */
1786 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1787 struct rtl8139_private *tp, void *ioaddr)
1788 {
1789 u8 tmp8;
1790 #ifdef CONFIG_8139_OLD_RX_RESET
1791 int tmp_work;
1792 #endif
1793
1794 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1795 dev->name, rx_status);
1796 tp->stats.rx_errors++;
1797 if (!(rx_status & RxStatusOK)) {
1798 if (rx_status & RxTooLong) {
1799 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1800 dev->name, rx_status);
1801 /* A.C.: The chip hangs here. */
1802 }
1803 if (rx_status & (RxBadSymbol | RxBadAlign))
1804 tp->stats.rx_frame_errors++;
1805 if (rx_status & (RxRunt | RxTooLong))
1806 tp->stats.rx_length_errors++;
1807 if (rx_status & RxCRCErr)
1808 tp->stats.rx_crc_errors++;
1809 } else {
1810 tp->xstats.rx_lost_in_ring++;
1811 }
1812
1813 #ifndef CONFIG_8139_OLD_RX_RESET
1814 tmp8 = RTL_R8 (ChipCmd);
1815 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1816 RTL_W8 (ChipCmd, tmp8);
1817 RTL_W32 (RxConfig, tp->rx_config);
1818 tp->cur_rx = 0;
1819 #else
1820 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1821
1822 /* disable receive */
1823 RTL_W8_F (ChipCmd, CmdTxEnb);
1824 tmp_work = 200;
1825 while (--tmp_work > 0) {
1826 udelay(1);
1827 tmp8 = RTL_R8 (ChipCmd);
1828 if (!(tmp8 & CmdRxEnb))
1829 break;
1830 }
1831 if (tmp_work <= 0)
1832 printk (KERN_WARNING PFX "rx stop wait too long\n");
1833 /* restart receive */
1834 tmp_work = 200;
1835 while (--tmp_work > 0) {
1836 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1837 udelay(1);
1838 tmp8 = RTL_R8 (ChipCmd);
1839 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1840 break;
1841 }
1842 if (tmp_work <= 0)
1843 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1844
1845 /* and reinitialize all rx related registers */
1846 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1847 /* Must enable Tx/Rx before setting transfer thresholds! */
1848 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1849
1850 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1851 RTL_W32 (RxConfig, tp->rx_config);
1852 tp->cur_rx = 0;
1853
1854 DPRINTK("init buffer addresses\n");
1855
1856 /* Lock Config[01234] and BMCR register writes */
1857 RTL_W8 (Cfg9346, Cfg9346_Lock);
1858
1859 /* init Rx ring buffer DMA address */
1860 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1861
1862 /* A.C.: Reset the multicast list. */
1863 __set_rx_mode (dev);
1864 #endif
1865 }
1866
1867 static void rtl8139_rx_interrupt (struct net_device *dev,
1868 struct rtl8139_private *tp, void *ioaddr)
1869 {
1870 unsigned char *rx_ring;
1871 u16 cur_rx;
1872
1873 assert (dev != NULL);
1874 assert (tp != NULL);
1875 assert (ioaddr != NULL);
1876
1877 rx_ring = tp->rx_ring;
1878 cur_rx = tp->cur_rx;
1879
1880 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1881 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1882 RTL_R16 (RxBufAddr),
1883 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1884
1885 while ((RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1886 int ring_offset = cur_rx % RX_BUF_LEN;
1887 u32 rx_status;
1888 unsigned int rx_size;
1889 unsigned int pkt_size;
1890 struct sk_buff *skb;
1891
1892 rmb();
1893
1894 /* read size+status of next frame from DMA ring buffer */
1895 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1896 rx_size = rx_status >> 16;
1897 pkt_size = rx_size - 4;
1898
1899 DPRINTK ("%s: rtl8139_rx() status %4.4x, size %4.4x,"
1900 " cur %4.4x.\n", dev->name, rx_status,
1901 rx_size, cur_rx);
1902 #if RTL8139_DEBUG > 2
1903 {
1904 int i;
1905 DPRINTK ("%s: Frame contents ", dev->name);
1906 for (i = 0; i < 70; i++)
1907 printk (" %2.2x",
1908 rx_ring[ring_offset + i]);
1909 printk (".\n");
1910 }
1911 #endif
1912
1913 /* Packet copy from FIFO still in progress.
1914 * Theoretically, this should never happen
1915 * since EarlyRx is disabled.
1916 */
1917 if (rx_size == 0xfff0) {
1918 tp->xstats.early_rx++;
1919 break;
1920 }
1921
1922 /* If Rx err or invalid rx_size/rx_status received
1923 * (which happens if we get lost in the ring),
1924 * Rx process gets reset, so we abort any further
1925 * Rx processing.
1926 */
1927 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1928 (rx_size < 8) ||
1929 (!(rx_status & RxStatusOK))) {
1930 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1931 return;
1932 }
1933
1934 /* Malloc up new buffer, compatible with net-2e. */
1935 /* Omit the four octet CRC from the length. */
1936
1937 /* TODO: consider allocating skb's outside of
1938 * interrupt context, both to speed interrupt processing,
1939 * and also to reduce the chances of having to
1940 * drop packets here under memory pressure.
1941 */
1942
1943 skb = dev_alloc_skb (pkt_size + 2);
1944 if (skb) {
1945 skb->dev = dev;
1946 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1947
1948 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1949 skb_put (skb, pkt_size);
1950
1951 skb->protocol = eth_type_trans (skb, dev);
1952 netif_rx (skb);
1953 dev->last_rx = jiffies;
1954 tp->stats.rx_bytes += pkt_size;
1955 tp->stats.rx_packets++;
1956 } else {
1957 printk (KERN_WARNING
1958 "%s: Memory squeeze, dropping packet.\n",
1959 dev->name);
1960 tp->stats.rx_dropped++;
1961 }
1962
1963 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1964 RTL_W16 (RxBufPtr, cur_rx - 16);
1965
1966 if (RTL_R16 (IntrStatus) & RxAckBits)
1967 RTL_W16_F (IntrStatus, RxAckBits);
1968 }
1969
1970 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1971 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1972 RTL_R16 (RxBufAddr),
1973 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1974
1975 tp->cur_rx = cur_rx;
1976 }
1977
1978
1979 static void rtl8139_weird_interrupt (struct net_device *dev,
1980 struct rtl8139_private *tp,
1981 void *ioaddr,
1982 int status, int link_changed)
1983 {
1984 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
1985 dev->name, status);
1986
1987 assert (dev != NULL);
1988 assert (tp != NULL);
1989 assert (ioaddr != NULL);
1990
1991 /* Update the error count. */
1992 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
1993 RTL_W32 (RxMissed, 0);
1994
1995 if ((status & RxUnderrun) && link_changed &&
1996 (tp->drv_flags & HAS_LNK_CHNG)) {
1997 /* Really link-change on new chips. */
1998 int lpar = RTL_R16 (NWayLPAR);
1999 int duplex = (lpar & LPA_100FULL) || (lpar & 0x01C0) == 0x0040
2000 || tp->mii.force_media;
2001 if (tp->mii.full_duplex != duplex) {
2002 tp->mii.full_duplex = duplex;
2003 #if 0
2004 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2005 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
2006 RTL_W8 (Cfg9346, Cfg9346_Lock);
2007 #endif
2008 }
2009 status &= ~RxUnderrun;
2010 }
2011
2012 /* XXX along with rtl8139_rx_err, are we double-counting errors? */
2013 if (status &
2014 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
2015 tp->stats.rx_errors++;
2016
2017 if (status & PCSTimeout)
2018 tp->stats.rx_length_errors++;
2019 if (status & (RxUnderrun | RxFIFOOver))
2020 tp->stats.rx_fifo_errors++;
2021 if (status & PCIErr) {
2022 u16 pci_cmd_status;
2023 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2024 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2025
2026 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2027 dev->name, pci_cmd_status);
2028 }
2029 }
2030
2031
2032 /* The interrupt handler does all of the Rx thread work and cleans up
2033 after the Tx thread. */
2034 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2035 struct pt_regs *regs)
2036 {
2037 struct net_device *dev = (struct net_device *) dev_instance;
2038 struct rtl8139_private *tp = dev->priv;
2039 int boguscnt = max_interrupt_work;
2040 void *ioaddr = tp->mmio_addr;
2041 int ackstat, status;
2042 int link_changed = 0; /* avoid bogus "uninit" warning */
2043 int handled = 0;
2044
2045 spin_lock (&tp->lock);
2046
2047 do {
2048 status = RTL_R16 (IntrStatus);
2049
2050 /* h/w no longer present (hotplug?) or major error, bail */
2051 if (status == 0xFFFF)
2052 break;
2053
2054 if ((status &
2055 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
2056 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
2057 break;
2058
2059 handled = 1;
2060
2061 /* Acknowledge all of the current interrupt sources ASAP, but
2062 an first get an additional status bit from CSCR. */
2063 if (status & RxUnderrun)
2064 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2065
2066 /* The chip takes special action when we clear RxAckBits,
2067 * so we clear them later in rtl8139_rx_interrupt
2068 */
2069 ackstat = status & ~(RxAckBits | TxErr);
2070 RTL_W16 (IntrStatus, ackstat);
2071
2072 DPRINTK ("%s: interrupt status=%#4.4x ackstat=%#4.4x new intstat=%#4.4x.\n",
2073 dev->name, ackstat, status, RTL_R16 (IntrStatus));
2074
2075 if (netif_running (dev) && (status & RxAckBits))
2076 rtl8139_rx_interrupt (dev, tp, ioaddr);
2077
2078 /* Check uncommon events with one test. */
2079 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
2080 RxFIFOOver | RxErr))
2081 rtl8139_weird_interrupt (dev, tp, ioaddr,
2082 status, link_changed);
2083
2084 if (netif_running (dev) && (status & (TxOK | TxErr))) {
2085 rtl8139_tx_interrupt (dev, tp, ioaddr);
2086 if (status & TxErr)
2087 RTL_W16 (IntrStatus, TxErr);
2088 }
2089
2090 boguscnt--;
2091 } while (boguscnt > 0);
2092
2093 if (boguscnt <= 0) {
2094 printk (KERN_WARNING "%s: Too much work at interrupt, "
2095 "IntrStatus=0x%4.4x.\n", dev->name, status);
2096
2097 /* Clear all interrupt sources. */
2098 RTL_W16 (IntrStatus, 0xffff);
2099 }
2100
2101 spin_unlock (&tp->lock);
2102
2103 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2104 dev->name, RTL_R16 (IntrStatus));
2105 return IRQ_RETVAL(handled);
2106 }
2107
2108
2109 static int rtl8139_close (struct net_device *dev)
2110 {
2111 struct rtl8139_private *tp = dev->priv;
2112 void *ioaddr = tp->mmio_addr;
2113 int ret = 0;
2114 unsigned long flags;
2115
2116 netif_stop_queue (dev);
2117
2118 if (tp->thr_pid >= 0) {
2119 tp->time_to_die = 1;
2120 wmb();
2121 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2122 if (ret) {
2123 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2124 return ret;
2125 }
2126 wait_for_completion (&tp->thr_exited);
2127 }
2128
2129 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
2130 dev->name, RTL_R16 (IntrStatus));
2131
2132 spin_lock_irqsave (&tp->lock, flags);
2133
2134 /* Stop the chip's Tx and Rx DMA processes. */
2135 RTL_W8 (ChipCmd, 0);
2136
2137 /* Disable interrupts by clearing the interrupt mask. */
2138 RTL_W16 (IntrMask, 0);
2139
2140 /* Update the error counts. */
2141 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2142 RTL_W32 (RxMissed, 0);
2143
2144 spin_unlock_irqrestore (&tp->lock, flags);
2145
2146 synchronize_irq (dev->irq); /* racy, but that's ok here */
2147 free_irq (dev->irq, dev);
2148
2149 rtl8139_tx_clear (tp);
2150
2151 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2152 tp->rx_ring, tp->rx_ring_dma);
2153 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2154 tp->tx_bufs, tp->tx_bufs_dma);
2155 tp->rx_ring = NULL;
2156 tp->tx_bufs = NULL;
2157
2158 /* Green! Put the chip in low-power mode. */
2159 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2160
2161 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2162 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2163
2164 return 0;
2165 }
2166
2167
2168 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2169 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2170 other threads or interrupts aren't messing with the 8139. */
2171 static void netdev_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
2172 {
2173 struct rtl8139_private *np = dev->priv;
2174 void *ioaddr = np->mmio_addr;
2175
2176 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2177 u8 cfg3 = RTL_R8 (Config3);
2178 u8 cfg5 = RTL_R8 (Config5);
2179
2180 wol->supported = WAKE_PHY | WAKE_MAGIC
2181 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2182
2183 wol->wolopts = 0;
2184 if (cfg3 & Cfg3_LinkUp)
2185 wol->wolopts |= WAKE_PHY;
2186 if (cfg3 & Cfg3_Magic)
2187 wol->wolopts |= WAKE_MAGIC;
2188 /* (KON)FIXME: See how netdev_set_wol() handles the
2189 following constants. */
2190 if (cfg5 & Cfg5_UWF)
2191 wol->wolopts |= WAKE_UCAST;
2192 if (cfg5 & Cfg5_MWF)
2193 wol->wolopts |= WAKE_MCAST;
2194 if (cfg5 & Cfg5_BWF)
2195 wol->wolopts |= WAKE_BCAST;
2196 }
2197 }
2198
2199
2200 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2201 that wol points to kernel memory and other threads or interrupts
2202 aren't messing with the 8139. */
2203 static int netdev_set_wol (struct net_device *dev,
2204 const struct ethtool_wolinfo *wol)
2205 {
2206 struct rtl8139_private *np = dev->priv;
2207 void *ioaddr = np->mmio_addr;
2208 u32 support;
2209 u8 cfg3, cfg5;
2210
2211 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2212 ? (WAKE_PHY | WAKE_MAGIC
2213 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2214 : 0);
2215 if (wol->wolopts & ~support)
2216 return -EINVAL;
2217
2218 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2219 if (wol->wolopts & WAKE_PHY)
2220 cfg3 |= Cfg3_LinkUp;
2221 if (wol->wolopts & WAKE_MAGIC)
2222 cfg3 |= Cfg3_Magic;
2223 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2224 RTL_W8 (Config3, cfg3);
2225 RTL_W8 (Cfg9346, Cfg9346_Lock);
2226
2227 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2228 /* (KON)FIXME: These are untested. We may have to set the
2229 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2230 documentation. */
2231 if (wol->wolopts & WAKE_UCAST)
2232 cfg5 |= Cfg5_UWF;
2233 if (wol->wolopts & WAKE_MCAST)
2234 cfg5 |= Cfg5_MWF;
2235 if (wol->wolopts & WAKE_BCAST)
2236 cfg5 |= Cfg5_BWF;
2237 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2238
2239 return 0;
2240 }
2241
2242 static int netdev_ethtool_ioctl (struct net_device *dev, void *useraddr)
2243 {
2244 struct rtl8139_private *np = dev->priv;
2245 u32 ethcmd;
2246
2247 /* dev_ioctl() in ../../net/core/dev.c has already checked
2248 capable(CAP_NET_ADMIN), so don't bother with that here. */
2249
2250 if (get_user(ethcmd, (u32 *)useraddr))
2251 return -EFAULT;
2252
2253 switch (ethcmd) {
2254
2255 case ETHTOOL_GDRVINFO: {
2256 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
2257 strcpy (info.driver, DRV_NAME);
2258 strcpy (info.version, DRV_VERSION);
2259 strcpy (info.bus_info, np->pci_dev->slot_name);
2260 info.regdump_len = np->regs_len;
2261 if (copy_to_user (useraddr, &info, sizeof (info)))
2262 return -EFAULT;
2263 return 0;
2264 }
2265
2266 /* get settings */
2267 case ETHTOOL_GSET: {
2268 struct ethtool_cmd ecmd = { ETHTOOL_GSET };
2269 spin_lock_irq(&np->lock);
2270 mii_ethtool_gset(&np->mii, &ecmd);
2271 spin_unlock_irq(&np->lock);
2272 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
2273 return -EFAULT;
2274 return 0;
2275 }
2276 /* set settings */
2277 case ETHTOOL_SSET: {
2278 int r;
2279 struct ethtool_cmd ecmd;
2280 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
2281 return -EFAULT;
2282 spin_lock_irq(&np->lock);
2283 r = mii_ethtool_sset(&np->mii, &ecmd);
2284 spin_unlock_irq(&np->lock);
2285 return r;
2286 }
2287 /* restart autonegotiation */
2288 case ETHTOOL_NWAY_RST: {
2289 return mii_nway_restart(&np->mii);
2290 }
2291 /* get link status */
2292 case ETHTOOL_GLINK: {
2293 struct ethtool_value edata = {ETHTOOL_GLINK};
2294 edata.data = mii_link_ok(&np->mii);
2295 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2296 return -EFAULT;
2297 return 0;
2298 }
2299
2300 /* get message-level */
2301 case ETHTOOL_GMSGLVL: {
2302 struct ethtool_value edata = {ETHTOOL_GMSGLVL};
2303 edata.data = debug;
2304 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2305 return -EFAULT;
2306 return 0;
2307 }
2308 /* set message-level */
2309 case ETHTOOL_SMSGLVL: {
2310 struct ethtool_value edata;
2311 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2312 return -EFAULT;
2313 debug = edata.data;
2314 return 0;
2315 }
2316
2317 case ETHTOOL_GWOL:
2318 {
2319 struct ethtool_wolinfo wol = { ETHTOOL_GWOL };
2320 spin_lock_irq (&np->lock);
2321 netdev_get_wol (dev, &wol);
2322 spin_unlock_irq (&np->lock);
2323 if (copy_to_user (useraddr, &wol, sizeof (wol)))
2324 return -EFAULT;
2325 return 0;
2326 }
2327
2328 case ETHTOOL_SWOL:
2329 {
2330 struct ethtool_wolinfo wol;
2331 int rc;
2332 if (copy_from_user (&wol, useraddr, sizeof (wol)))
2333 return -EFAULT;
2334 spin_lock_irq (&np->lock);
2335 rc = netdev_set_wol (dev, &wol);
2336 spin_unlock_irq (&np->lock);
2337 return rc;
2338 }
2339
2340 /* TODO: we are too slack to do reg dumping for pio, for now */
2341 #ifndef CONFIG_8139TOO_PIO
2342 /* NIC register dump */
2343 case ETHTOOL_GREGS: {
2344 struct ethtool_regs regs;
2345 unsigned int regs_len = np->regs_len;
2346 u8 *regbuf = kmalloc(regs_len, GFP_KERNEL);
2347 int rc;
2348
2349 if (!regbuf)
2350 return -ENOMEM;
2351 memset(regbuf, 0, regs_len);
2352
2353 rc = copy_from_user(&regs, useraddr, sizeof(regs));
2354 if (rc) {
2355 rc = -EFAULT;
2356 goto err_out_gregs;
2357 }
2358
2359 if (regs.len > regs_len)
2360 regs.len = regs_len;
2361 if (regs.len < regs_len) {
2362 rc = -EINVAL;
2363 goto err_out_gregs;
2364 }
2365
2366 regs.version = RTL_REGS_VER;
2367 rc = copy_to_user(useraddr, &regs, sizeof(regs));
2368 if (rc) {
2369 rc = -EFAULT;
2370 goto err_out_gregs;
2371 }
2372
2373 useraddr += offsetof(struct ethtool_regs, data);
2374
2375 spin_lock_irq(&np->lock);
2376 memcpy_fromio(regbuf, np->mmio_addr, regs_len);
2377 spin_unlock_irq(&np->lock);
2378
2379 if (copy_to_user(useraddr, regbuf, regs_len))
2380 rc = -EFAULT;
2381
2382 err_out_gregs:
2383 kfree(regbuf);
2384 return rc;
2385 }
2386 #endif /* CONFIG_8139TOO_PIO */
2387
2388 /* get string list(s) */
2389 case ETHTOOL_GSTRINGS: {
2390 struct ethtool_gstrings estr = { ETHTOOL_GSTRINGS };
2391
2392 if (copy_from_user(&estr, useraddr, sizeof(estr)))
2393 return -EFAULT;
2394 if (estr.string_set != ETH_SS_STATS)
2395 return -EINVAL;
2396
2397 estr.len = RTL_NUM_STATS;
2398 if (copy_to_user(useraddr, &estr, sizeof(estr)))
2399 return -EFAULT;
2400 if (copy_to_user(useraddr + sizeof(estr),
2401 &ethtool_stats_keys,
2402 sizeof(ethtool_stats_keys)))
2403 return -EFAULT;
2404 return 0;
2405 }
2406
2407 /* get NIC-specific statistics */
2408 case ETHTOOL_GSTATS: {
2409 struct ethtool_stats estats = { ETHTOOL_GSTATS };
2410 u64 *tmp_stats;
2411 const unsigned int sz = sizeof(u64) * RTL_NUM_STATS;
2412 int i;
2413
2414 estats.n_stats = RTL_NUM_STATS;
2415 if (copy_to_user(useraddr, &estats, sizeof(estats)))
2416 return -EFAULT;
2417
2418 tmp_stats = kmalloc(sz, GFP_KERNEL);
2419 if (!tmp_stats)
2420 return -ENOMEM;
2421 memset(tmp_stats, 0, sz);
2422
2423 i = 0;
2424 tmp_stats[i++] = np->xstats.early_rx;
2425 tmp_stats[i++] = np->xstats.tx_buf_mapped;
2426 tmp_stats[i++] = np->xstats.tx_timeouts;
2427 tmp_stats[i++] = np->xstats.rx_lost_in_ring;
2428 if (i != RTL_NUM_STATS)
2429 BUG();
2430
2431 i = copy_to_user(useraddr + sizeof(estats), tmp_stats, sz);
2432 kfree(tmp_stats);
2433
2434 if (i)
2435 return -EFAULT;
2436 return 0;
2437 }
2438 default:
2439 break;
2440 }
2441
2442 return -EOPNOTSUPP;
2443 }
2444
2445
2446 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2447 {
2448 struct rtl8139_private *np = dev->priv;
2449 struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
2450 int rc;
2451
2452 if (!netif_running(dev))
2453 return -EINVAL;
2454
2455 if (cmd == SIOCETHTOOL)
2456 rc = netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
2457
2458 else {
2459 spin_lock_irq(&np->lock);
2460 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
2461 spin_unlock_irq(&np->lock);
2462 }
2463
2464 return rc;
2465 }
2466
2467
2468 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2469 {
2470 struct rtl8139_private *tp = dev->priv;
2471 void *ioaddr = tp->mmio_addr;
2472 unsigned long flags;
2473
2474 if (netif_running(dev)) {
2475 spin_lock_irqsave (&tp->lock, flags);
2476 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2477 RTL_W32 (RxMissed, 0);
2478 spin_unlock_irqrestore (&tp->lock, flags);
2479 }
2480
2481 return &tp->stats;
2482 }
2483
2484 /* Set or clear the multicast filter for this adaptor.
2485 This routine is not state sensitive and need not be SMP locked. */
2486
2487 static void __set_rx_mode (struct net_device *dev)
2488 {
2489 struct rtl8139_private *tp = dev->priv;
2490 void *ioaddr = tp->mmio_addr;
2491 u32 mc_filter[2]; /* Multicast hash filter */
2492 int i, rx_mode;
2493 u32 tmp;
2494
2495 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2496 dev->name, dev->flags, RTL_R32 (RxConfig));
2497
2498 /* Note: do not reorder, GCC is clever about common statements. */
2499 if (dev->flags & IFF_PROMISC) {
2500 /* Unconditionally log net taps. */
2501 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2502 dev->name);
2503 rx_mode =
2504 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2505 AcceptAllPhys;
2506 mc_filter[1] = mc_filter[0] = 0xffffffff;
2507 } else if ((dev->mc_count > multicast_filter_limit)
2508 || (dev->flags & IFF_ALLMULTI)) {
2509 /* Too many to filter perfectly -- accept all multicasts. */
2510 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2511 mc_filter[1] = mc_filter[0] = 0xffffffff;
2512 } else {
2513 struct dev_mc_list *mclist;
2514 rx_mode = AcceptBroadcast | AcceptMyPhys;
2515 mc_filter[1] = mc_filter[0] = 0;
2516 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2517 i++, mclist = mclist->next) {
2518 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2519
2520 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2521 rx_mode |= AcceptMulticast;
2522 }
2523 }
2524
2525 /* We can safely update without stopping the chip. */
2526 tmp = rtl8139_rx_config | rx_mode;
2527 if (tp->rx_config != tmp) {
2528 RTL_W32_F (RxConfig, tmp);
2529 tp->rx_config = tmp;
2530 }
2531 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2532 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2533 }
2534
2535 static void rtl8139_set_rx_mode (struct net_device *dev)
2536 {
2537 unsigned long flags;
2538 struct rtl8139_private *tp = dev->priv;
2539
2540 spin_lock_irqsave (&tp->lock, flags);
2541 __set_rx_mode(dev);
2542 spin_unlock_irqrestore (&tp->lock, flags);
2543 }
2544
2545 #ifdef CONFIG_PM
2546
2547 static int rtl8139_suspend (struct pci_dev *pdev, u32 state)
2548 {
2549 struct net_device *dev = pci_get_drvdata (pdev);
2550 struct rtl8139_private *tp = dev->priv;
2551 void *ioaddr = tp->mmio_addr;
2552 unsigned long flags;
2553
2554 if (!netif_running (dev))
2555 return 0;
2556
2557 netif_device_detach (dev);
2558
2559 spin_lock_irqsave (&tp->lock, flags);
2560
2561 /* Disable interrupts, stop Tx and Rx. */
2562 RTL_W16 (IntrMask, 0);
2563 RTL_W8 (ChipCmd, 0);
2564
2565 /* Update the error counts. */
2566 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2567 RTL_W32 (RxMissed, 0);
2568
2569 spin_unlock_irqrestore (&tp->lock, flags);
2570 return 0;
2571 }
2572
2573
2574 static int rtl8139_resume (struct pci_dev *pdev)
2575 {
2576 struct net_device *dev = pci_get_drvdata (pdev);
2577
2578 if (!netif_running (dev))
2579 return 0;
2580 netif_device_attach (dev);
2581 rtl8139_hw_start (dev);
2582 return 0;
2583 }
2584
2585 #endif /* CONFIG_PM */
2586
2587
2588 static struct pci_driver rtl8139_pci_driver = {
2589 .name = DRV_NAME,
2590 .id_table = rtl8139_pci_tbl,
2591 .probe = rtl8139_init_one,
2592 .remove = __devexit_p(rtl8139_remove_one),
2593 #ifdef CONFIG_PM
2594 .suspend = rtl8139_suspend,
2595 .resume = rtl8139_resume,
2596 #endif /* CONFIG_PM */
2597 };
2598
2599
2600 static int __init rtl8139_init_module (void)
2601 {
2602 /* when we're a module, we always print a version message,
2603 * even if no 8139 board is found.
2604 */
2605 #ifdef MODULE
2606 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2607 #endif
2608
2609 return pci_module_init (&rtl8139_pci_driver);
2610 }
2611
2612
2613 static void __exit rtl8139_cleanup_module (void)
2614 {
2615 pci_unregister_driver (&rtl8139_pci_driver);
2616 }
2617
2618
2619 module_init(rtl8139_init_module);
2620 module_exit(rtl8139_cleanup_module);
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