1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
4 * Copyright (C) 1999-2000, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
7 * Ani Joshi / Jeff Garzik
10 * Based off of Geert's atyfb.c and vfb.c.
14 * - monitor sensing (DDC)
16 * - other platform support (only ppc/x86 supported)
17 * - hardware cursor support
20 * Please cc: your patches to brad@neruo.com.
24 * A special note of gratitude to ATI's devrel for providing documentation,
25 * example code and hardware. Thanks Nitya. -atong and brad
29 #include <linux/config.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/errno.h>
33 #include <linux/string.h>
35 #include <linux/tty.h>
36 #include <linux/malloc.h>
37 #include <linux/vmalloc.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <asm/uaccess.h>
42 #include <linux/init.h>
43 #include <linux/selection.h>
44 #include <linux/console.h>
45 #include <linux/pci.h>
46 #include <linux/ioport.h>
51 #include <asm/pci-bridge.h>
52 #include <video/macmodes.h>
54 #include <linux/nvram.h>
58 #ifdef CONFIG_FB_COMPAT_XPMAC
59 #include <asm/vc_ioctl.h>
62 #include <video/fbcon.h>
63 #include <video/fbcon-cfb8.h>
64 #include <video/fbcon-cfb16.h>
65 #include <video/fbcon-cfb24.h>
66 #include <video/fbcon-cfb32.h>
78 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
80 #define DBG(fmt, args...)
85 static struct fb_var_screeninfo default_var __initdata
= {
86 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
87 640, 480, 640, 480, 0, 0, 8, 0,
88 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
89 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
90 0, FB_VMODE_NONINTERLACED
93 #else /* CONFIG_PPC */
94 /* default to 1024x768 at 75Hz on PPC - this will work
95 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
96 static struct fb_var_screeninfo default_var
= {
97 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
98 1024, 768, 1024, 768, 0, 0, 8, 0,
99 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
100 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
101 FB_SYNC_HOR_HIGH_ACT
|FB_SYNC_VERT_HIGH_ACT
, FB_VMODE_NONINTERLACED
103 #endif /* CONFIG_PPC */
106 /* default modedb mode */
107 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
108 static struct fb_videomode defaultmode __initdata
= {
120 vmode
: FB_VMODE_NONINTERLACED
124 /* struct to hold chip description information */
125 struct aty128_chip_info
{
127 unsigned short device
;
131 /* Chip generations */
138 /* supported Rage128 chipsets */
139 static const struct aty128_chip_info aty128_pci_probe_list
[] __initdata
=
141 {"Rage128 RE (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RE
, rage_128
},
142 {"Rage128 RF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RF
, rage_128
},
143 {"Rage128 RK (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RK
, rage_128
},
144 {"Rage128 RL (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RL
, rage_128
},
145 {"Rage128 Pro PF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_PF
, rage_128_pro
},
146 {"Rage128 Pro PR (PCI)", PCI_DEVICE_ID_ATI_RAGE128_PR
, rage_128_pro
},
147 {"Rage Mobility M3 (PCI)", PCI_DEVICE_ID_ATI_RAGE128_LE
, rage_M3
},
148 {"Rage Mobility M3 (AGP)", PCI_DEVICE_ID_ATI_RAGE128_LF
, rage_M3
},
152 /* packed BIOS settings */
157 u8 accelerator_entry
;
159 u16 VGA_table_offset
;
160 u16 POST_table_offset
;
166 u16 PCLK_ref_divider
;
170 u16 MCLK_ref_divider
;
174 u16 XCLK_ref_divider
;
177 } __attribute__ ((packed
)) PLL_BLOCK
;
178 #endif /* !CONFIG_PPC */
180 /* onboard memory information */
181 struct aty128_meminfo
{
195 /* various memory configurations */
196 static const struct aty128_meminfo sdr_128
=
197 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
198 static const struct aty128_meminfo sdr_64
=
199 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
200 static const struct aty128_meminfo sdr_sgram
=
201 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
202 static const struct aty128_meminfo ddr_sgram
=
203 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
205 static const char *aty128fb_name
= "ATY Rage128";
206 static char fontname
[40] __initdata
= { 0 };
207 static int noaccel __initdata
= 0;
210 static const char *mode_option __initdata
= NULL
;
212 #if !defined(CONFIG_PPC) && !defined(__sparc__)
213 static void *bios_seg
= NULL
;
217 #ifdef CONFIG_NVRAM_NOT_DEFINED
218 static int default_vmode __initdata
= VMODE_640_480_60
;
219 static int default_cmode __initdata
= CMODE_8
;
221 static int default_vmode __initdata
= VMODE_NVRAM
;
222 static int default_cmode __initdata
= CMODE_NVRAM
;
231 struct aty128_constants
{
244 u32 h_total
, h_sync_strt_wid
;
245 u32 v_total
, v_sync_strt_wid
;
247 u32 offset
, offset_cntl
;
248 u32 xoffset
, yoffset
;
255 u32 feedback_divider
;
259 struct aty128_ddafifo
{
264 /* register values for a specific mode */
265 struct aty128fb_par
{
266 struct aty128_crtc crtc
;
267 struct aty128_pll pll
;
268 struct aty128_ddafifo fifo_reg
;
272 struct fb_info_aty128
{
273 struct fb_info fb_info
;
274 struct fb_info_aty128
*next
;
275 struct aty128_constants constants
; /* PLL and others */
276 u32 regbase_phys
; /* physical mmio */
277 void *regbase
; /* remapped mmio */
278 u32 frame_buffer_phys
; /* physical fb memory */
279 u32 frame_buffer
; /* remaped framebuffer */
280 u32 io_base
; /* unmapped io */
281 u32 vram_size
; /* onboard video ram */
283 const struct aty128_meminfo
*mem
; /* onboard mem info */
284 struct aty128fb_par default_par
, current_par
;
286 struct display_switch dispsw
; /* for cursor and font */
287 struct { u8 red
, green
, blue
, pad
; } palette
[256];
289 #ifdef FBCON_HAS_CFB16
292 #ifdef FBCON_HAS_CFB24
295 #ifdef FBCON_HAS_CFB32
300 struct pci_dev
*pdev
;
303 struct { int vram
; int vram_valid
; } mtrr
;
306 int blitter_may_be_busy
;
307 int fifo_slots
; /* free slots in FIFO (64 max) */
310 static struct fb_info_aty128
*board_list
= NULL
;
312 #define round_div(n, d) ((n+(d/2))/d)
315 * Interface used by the world
318 int aty128fb_setup(char *options
);
320 static int aty128fb_get_fix(struct fb_fix_screeninfo
*fix
, int con
,
321 struct fb_info
*info
);
322 static int aty128fb_get_var(struct fb_var_screeninfo
*var
, int con
,
323 struct fb_info
*info
);
324 static int aty128fb_set_var(struct fb_var_screeninfo
*var
, int con
,
325 struct fb_info
*info
);
326 static int aty128fb_get_cmap(struct fb_cmap
*cmap
, int kspc
, int con
,
327 struct fb_info
*info
);
328 static int aty128fb_set_cmap(struct fb_cmap
*cmap
, int kspc
, int con
,
329 struct fb_info
*info
);
330 static int aty128fb_pan_display(struct fb_var_screeninfo
*var
, int con
,
332 static int aty128fb_ioctl(struct inode
*inode
, struct file
*file
, u_int cmd
,
333 u_long arg
, int con
, struct fb_info
*info
);
334 static int aty128fb_rasterimg(struct fb_info
*info
, int start
);
338 * Interface to the low level console driver
341 int aty128fb_init(void);
342 static int aty128fbcon_switch(int con
, struct fb_info
*fb
);
343 static void aty128fbcon_blank(int blank
, struct fb_info
*fb
);
349 static void aty128_encode_fix(struct fb_fix_screeninfo
*fix
,
350 struct aty128fb_par
*par
,
351 const struct fb_info_aty128
*info
);
352 static void aty128_set_disp(struct display
*disp
,
353 struct fb_info_aty128
*info
, int bpp
, int accel
);
354 static int aty128_getcolreg(u_int regno
, u_int
*red
, u_int
*green
, u_int
*blue
,
355 u_int
*transp
, struct fb_info
*info
);
356 static int aty128_setcolreg(u_int regno
, u_int red
, u_int green
, u_int blue
,
357 u_int transp
, struct fb_info
*info
);
358 static void do_install_cmap(int con
, struct fb_info
*info
);
359 static int aty128_encode_var(struct fb_var_screeninfo
*var
,
360 const struct aty128fb_par
*par
,
361 const struct fb_info_aty128
*info
);
362 static int aty128_decode_var(struct fb_var_screeninfo
*var
,
363 struct aty128fb_par
*par
,
364 const struct fb_info_aty128
*info
);
365 static int aty128_pci_register(struct pci_dev
*pdev
,
366 const struct aty128_chip_info
*aci
);
367 static struct fb_info_aty128
*aty128_board_list_add(struct fb_info_aty128
368 *board_list
, struct fb_info_aty128
*new_node
);
369 #if !defined(CONFIG_PPC) && !defined(__sparc__)
370 static void aty128_get_pllinfo(struct fb_info_aty128
*info
);
371 static int aty128find_ROM(struct fb_info_aty128
*info
);
373 static void aty128_timings(struct fb_info_aty128
*info
);
374 static void aty128_init_engine(const struct aty128fb_par
*par
,
375 struct fb_info_aty128
*info
);
376 static void aty128_reset_engine(const struct fb_info_aty128
*info
);
377 static void aty128_flush_pixel_cache(const struct fb_info_aty128
*info
);
378 static void do_wait_for_fifo(u16 entries
, struct fb_info_aty128
*info
);
379 static void wait_for_fifo(u16 entries
, struct fb_info_aty128
*info
);
380 static void wait_for_idle(struct fb_info_aty128
*info
);
381 static u32
bpp_to_depth(u32 bpp
);
383 #ifdef FBCON_HAS_CFB8
384 static struct display_switch fbcon_aty128_8
;
385 static void fbcon_aty8_putc(struct vc_data
*conp
, struct display
*p
,
386 int c
, int yy
, int xx
);
387 static void fbcon_aty8_putcs(struct vc_data
*conp
, struct display
*p
,
388 const unsigned short *s
, int count
,
391 #ifdef FBCON_HAS_CFB16
392 static struct display_switch fbcon_aty128_16
;
393 static void fbcon_aty16_putc(struct vc_data
*conp
, struct display
*p
,
394 int c
, int yy
, int xx
);
395 static void fbcon_aty16_putcs(struct vc_data
*conp
, struct display
*p
,
396 const unsigned short *s
, int count
,
399 #ifdef FBCON_HAS_CFB24
400 static struct display_switch fbcon_aty128_24
;
401 static void fbcon_aty24_putc(struct vc_data
*conp
, struct display
*p
,
402 int c
, int yy
, int xx
);
403 static void fbcon_aty24_putcs(struct vc_data
*conp
, struct display
*p
,
404 const unsigned short *s
, int count
,
407 #ifdef FBCON_HAS_CFB32
408 static struct display_switch fbcon_aty128_32
;
409 static void fbcon_aty32_putc(struct vc_data
*conp
, struct display
*p
,
410 int c
, int yy
, int xx
);
411 static void fbcon_aty32_putcs(struct vc_data
*conp
, struct display
*p
,
412 const unsigned short *s
, int count
,
416 static struct fb_ops aty128fb_ops
= {
418 fb_get_fix
: aty128fb_get_fix
,
419 fb_get_var
: aty128fb_get_var
,
420 fb_set_var
: aty128fb_set_var
,
421 fb_get_cmap
: aty128fb_get_cmap
,
422 fb_set_cmap
: aty128fb_set_cmap
,
423 fb_pan_display
: aty128fb_pan_display
,
424 fb_ioctl
: aty128fb_ioctl
,
425 fb_rasterimg
: aty128fb_rasterimg
,
430 * Functions to read from/write to the mmio registers
431 * - endian conversions may possibly be avoided by
432 * using the other register aperture. TODO.
435 _aty_ld_le32(volatile unsigned int regindex
,
436 const struct fb_info_aty128
*info
)
440 #if defined(__powerpc__)
441 asm("lwbrx %0,%1,%2;eieio" : "=r"(val
) : "b"(regindex
), "r"(info
->regbase
));
443 val
= readl (info
->regbase
+ regindex
);
450 _aty_st_le32(volatile unsigned int regindex
, u32 val
,
451 const struct fb_info_aty128
*info
)
453 #if defined(__powerpc__)
454 asm("stwbrx %0,%1,%2;eieio" : : "r"(val
), "b"(regindex
),
455 "r"(info
->regbase
) : "memory");
457 writel (val
, info
->regbase
+ regindex
);
462 _aty_ld_8(unsigned int regindex
, const struct fb_info_aty128
*info
)
464 return readb (info
->regbase
+ regindex
);
468 _aty_st_8(unsigned int regindex
, u8 val
, const struct fb_info_aty128
*info
)
470 writeb (val
, info
->regbase
+ regindex
);
473 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, info)
474 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, info)
475 #define aty_ld_8(regindex) _aty_ld_8(regindex, info)
476 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, info)
479 * Functions to read from/write to the pll registers
482 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, info)
483 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, info)
487 _aty_ld_pll(unsigned int pll_index
,
488 const struct fb_info_aty128
*info
)
490 aty_st_8(CLOCK_CNTL_INDEX
, pll_index
& 0x1F);
491 return aty_ld_le32(CLOCK_CNTL_DATA
);
496 _aty_st_pll(unsigned int pll_index
, u32 val
,
497 const struct fb_info_aty128
*info
)
499 aty_st_8(CLOCK_CNTL_INDEX
, (pll_index
& 0x1F) | PLL_WR_EN
);
500 aty_st_le32(CLOCK_CNTL_DATA
, val
);
504 /* return true when the PLL has completed an atomic update */
506 aty_pll_readupdate(const struct fb_info_aty128
*info
)
508 return !(aty_ld_pll(PPLL_REF_DIV
) & PPLL_ATOMIC_UPDATE_R
);
513 aty_pll_wait_readupdate(const struct fb_info_aty128
*info
)
515 unsigned long timeout
= jiffies
+ HZ
/100; // should be more than enough
518 while (time_before(jiffies
, timeout
))
519 if (aty_pll_readupdate(info
)) {
524 if (reset
) /* reset engine?? */
525 printk(KERN_DEBUG
"aty128fb: PLL write timeout!");
529 /* tell PLL to update */
531 aty_pll_writeupdate(const struct fb_info_aty128
*info
)
533 aty_pll_wait_readupdate(info
);
535 aty_st_pll(PPLL_REF_DIV
,
536 aty_ld_pll(PPLL_REF_DIV
) | PPLL_ATOMIC_UPDATE_W
);
540 /* write to the scratch register to test r/w functionality */
542 register_test(const struct fb_info_aty128
*info
)
547 val
= aty_ld_le32(BIOS_0_SCRATCH
);
549 aty_st_le32(BIOS_0_SCRATCH
, 0x55555555);
550 if (aty_ld_le32(BIOS_0_SCRATCH
) == 0x55555555) {
551 aty_st_le32(BIOS_0_SCRATCH
, 0xAAAAAAAA);
553 if (aty_ld_le32(BIOS_0_SCRATCH
) == 0xAAAAAAAA)
557 aty_st_le32(BIOS_0_SCRATCH
, val
); // restore value
563 * Accelerator engine functions
566 do_wait_for_fifo(u16 entries
, struct fb_info_aty128
*info
)
571 for (i
= 0; i
< 2000000; i
++) {
572 info
->fifo_slots
= aty_ld_le32(GUI_STAT
) & 0x0fff;
573 if (info
->fifo_slots
>= entries
)
576 aty128_reset_engine(info
);
582 wait_for_idle(struct fb_info_aty128
*info
)
586 do_wait_for_fifo(64, info
);
589 for (i
= 0; i
< 2000000; i
++) {
590 if (!(aty_ld_le32(GUI_STAT
) & (1 << 31))) {
591 aty128_flush_pixel_cache(info
);
592 info
->blitter_may_be_busy
= 0;
596 aty128_reset_engine(info
);
602 wait_for_fifo(u16 entries
, struct fb_info_aty128
*info
)
604 if (info
->fifo_slots
< entries
)
605 do_wait_for_fifo(64, info
);
606 info
->fifo_slots
-= entries
;
611 aty128_flush_pixel_cache(const struct fb_info_aty128
*info
)
616 tmp
= aty_ld_le32(PC_NGUI_CTLSTAT
);
619 aty_st_le32(PC_NGUI_CTLSTAT
, tmp
);
621 for (i
= 0; i
< 2000000; i
++)
622 if (!(aty_ld_le32(PC_NGUI_CTLSTAT
) & PC_BUSY
))
628 aty128_reset_engine(const struct fb_info_aty128
*info
)
630 u32 gen_reset_cntl
, clock_cntl_index
, mclk_cntl
;
632 aty128_flush_pixel_cache(info
);
634 clock_cntl_index
= aty_ld_le32(CLOCK_CNTL_INDEX
);
635 mclk_cntl
= aty_ld_pll(MCLK_CNTL
);
637 aty_st_pll(MCLK_CNTL
, mclk_cntl
| 0x00030000);
639 gen_reset_cntl
= aty_ld_le32(GEN_RESET_CNTL
);
640 aty_st_le32(GEN_RESET_CNTL
, gen_reset_cntl
| SOFT_RESET_GUI
);
641 aty_ld_le32(GEN_RESET_CNTL
);
642 aty_st_le32(GEN_RESET_CNTL
, gen_reset_cntl
& ~(SOFT_RESET_GUI
));
643 aty_ld_le32(GEN_RESET_CNTL
);
645 aty_st_pll(MCLK_CNTL
, mclk_cntl
);
646 aty_st_le32(CLOCK_CNTL_INDEX
, clock_cntl_index
);
647 aty_st_le32(GEN_RESET_CNTL
, gen_reset_cntl
);
649 /* use old pio mode */
650 aty_st_le32(PM4_BUFFER_CNTL
, PM4_BUFFER_CNTL_NONPM4
);
657 aty128_init_engine(const struct aty128fb_par
*par
,
658 struct fb_info_aty128
*info
)
664 /* 3D scaler not spoken here */
665 wait_for_fifo(1, info
);
666 aty_st_le32(SCALE_3D_CNTL
, 0x00000000);
668 aty128_reset_engine(info
);
670 pitch_value
= par
->crtc
.pitch
;
671 if (par
->crtc
.bpp
== 24) {
672 pitch_value
= pitch_value
* 3;
675 wait_for_fifo(4, info
);
676 /* setup engine offset registers */
677 aty_st_le32(DEFAULT_OFFSET
, 0x00000000);
679 /* setup engine pitch registers */
680 aty_st_le32(DEFAULT_PITCH
, pitch_value
);
682 /* set the default scissor register to max dimensions */
683 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT
, (0x1FFF << 16) | 0x1FFF);
685 /* set the drawing controls registers */
686 aty_st_le32(DP_GUI_MASTER_CNTL
,
687 GMC_SRC_PITCH_OFFSET_DEFAULT
|
688 GMC_DST_PITCH_OFFSET_DEFAULT
|
689 GMC_SRC_CLIP_DEFAULT
|
690 GMC_DST_CLIP_DEFAULT
|
691 GMC_BRUSH_SOLIDCOLOR
|
692 (bpp_to_depth(par
->crtc
.bpp
) << 8) |
694 GMC_BYTE_ORDER_MSB_TO_LSB
|
695 GMC_DP_CONVERSION_TEMP_6500
|
699 GMC_DST_CLR_CMP_FCN_CLEAR
|
703 wait_for_fifo(8, info
);
704 /* clear the line drawing registers */
705 aty_st_le32(DST_BRES_ERR
, 0);
706 aty_st_le32(DST_BRES_INC
, 0);
707 aty_st_le32(DST_BRES_DEC
, 0);
709 /* set brush color registers */
710 aty_st_le32(DP_BRUSH_FRGD_CLR
, 0xFFFFFFFF); /* white */
711 aty_st_le32(DP_BRUSH_BKGD_CLR
, 0x00000000); /* black */
713 /* set source color registers */
714 aty_st_le32(DP_SRC_FRGD_CLR
, 0xFFFFFFFF); /* white */
715 aty_st_le32(DP_SRC_BKGD_CLR
, 0x00000000); /* black */
717 /* default write mask */
718 aty_st_le32(DP_WRITE_MASK
, 0xFFFFFFFF);
720 /* Wait for all the writes to be completed before returning */
725 /* convert bpp values to their register representation */
727 bpp_to_depth(u32 bpp
)
746 /* Program the CRTC registers */
748 aty128_set_crtc(const struct aty128_crtc
*crtc
,
749 const struct fb_info_aty128
*info
)
751 aty_st_le32(CRTC_GEN_CNTL
, crtc
->gen_cntl
);
752 aty_st_le32(CRTC_H_TOTAL_DISP
, crtc
->h_total
);
753 aty_st_le32(CRTC_H_SYNC_STRT_WID
, crtc
->h_sync_strt_wid
);
754 aty_st_le32(CRTC_V_TOTAL_DISP
, crtc
->v_total
);
755 aty_st_le32(CRTC_V_SYNC_STRT_WID
, crtc
->v_sync_strt_wid
);
756 aty_st_le32(CRTC_PITCH
, crtc
->pitch
);
757 aty_st_le32(CRTC_OFFSET
, crtc
->offset
);
758 aty_st_le32(CRTC_OFFSET_CNTL
, crtc
->offset_cntl
);
759 /* Disable ATOMIC updating. Is this the right place?
760 * -- BenH: Breaks on my G4
763 aty_st_le32(PPLL_CNTL
, aty_ld_le32(PPLL_CNTL
) & ~(0x00030000));
769 aty128_var_to_crtc(const struct fb_var_screeninfo
*var
,
770 struct aty128_crtc
*crtc
,
771 const struct fb_info_aty128
*info
)
773 u32 xres
, yres
, vxres
, vyres
, xoffset
, yoffset
, bpp
;
774 u32 left
, right
, upper
, lower
, hslen
, vslen
, sync
, vmode
;
775 u32 h_total
, h_disp
, h_sync_strt
, h_sync_wid
, h_sync_pol
;
776 u32 v_total
, v_disp
, v_sync_strt
, v_sync_wid
, v_sync_pol
, c_sync
;
778 u8 hsync_strt_pix
[5] = { 0, 0x12, 9, 6, 5 };
779 u8 mode_bytpp
[7] = { 0, 0, 1, 2, 2, 3, 4 };
784 vxres
= var
->xres_virtual
;
785 vyres
= var
->yres_virtual
;
786 xoffset
= var
->xoffset
;
787 yoffset
= var
->yoffset
;
788 bpp
= var
->bits_per_pixel
;
789 left
= var
->left_margin
;
790 right
= var
->right_margin
;
791 upper
= var
->upper_margin
;
792 lower
= var
->lower_margin
;
793 hslen
= var
->hsync_len
;
794 vslen
= var
->vsync_len
;
798 /* check for mode eligibility
799 * accept only non interlaced modes */
800 if ((vmode
& FB_VMODE_MASK
) != FB_VMODE_NONINTERLACED
)
803 /* convert (and round up) and validate */
804 xres
= (xres
+ 7) & ~7;
805 xoffset
= (xoffset
+ 7) & ~7;
807 if (vxres
< xres
+ xoffset
)
808 vxres
= xres
+ xoffset
;
810 if (vyres
< yres
+ yoffset
)
811 vyres
= yres
+ yoffset
;
813 /* convert bpp into ATI register depth */
814 depth
= bpp_to_depth(bpp
);
816 /* make sure we didn't get an invalid depth */
817 if (depth
== -EINVAL
) {
818 printk(KERN_ERR
"aty128fb: Invalid depth\n");
822 /* convert depth to bpp */
823 bytpp
= mode_bytpp
[depth
];
825 /* make sure there is enough video ram for the mode */
826 if ((u32
)(vxres
* vyres
* bytpp
) > info
->vram_size
) {
827 printk(KERN_ERR
"aty128fb: Not enough memory for mode\n");
831 h_disp
= (xres
>> 3) - 1;
832 h_total
= (((xres
+ right
+ hslen
+ left
) >> 3) - 1) & 0xFFFFL
;
835 v_total
= (yres
+ upper
+ vslen
+ lower
- 1) & 0xFFFFL
;
837 /* check to make sure h_total and v_total are in range */
838 if (((h_total
>> 3) - 1) > 0x1ff || (v_total
- 1) > 0x7FF) {
839 printk(KERN_ERR
"aty128fb: invalid width ranges\n");
843 h_sync_wid
= (hslen
+ 7) >> 3;
846 else if (h_sync_wid
> 0x3f) /* 0x3f = max hwidth */
849 h_sync_strt
= h_disp
+ (right
>> 3);
854 else if (v_sync_wid
> 0x1f) /* 0x1f = max vwidth */
857 v_sync_strt
= v_disp
+ lower
;
859 h_sync_pol
= sync
& FB_SYNC_HOR_HIGH_ACT
? 0 : 1;
860 v_sync_pol
= sync
& FB_SYNC_VERT_HIGH_ACT
? 0 : 1;
862 c_sync
= sync
& FB_SYNC_COMP_HIGH_ACT
? (1 << 4) : 0;
864 crtc
->gen_cntl
= 0x3000000L
| c_sync
| (depth
<< 8);
866 crtc
->h_total
= h_total
| (h_disp
<< 16);
867 crtc
->v_total
= v_total
| (v_disp
<< 16);
869 crtc
->h_sync_strt_wid
= hsync_strt_pix
[bytpp
] | (h_sync_strt
<< 3) |
870 (h_sync_wid
<< 16) | (h_sync_pol
<< 23);
871 crtc
->v_sync_strt_wid
= v_sync_strt
| (v_sync_wid
<< 16) |
874 crtc
->pitch
= vxres
>> 3;
877 crtc
->offset_cntl
= 0;
881 crtc
->xoffset
= xoffset
;
882 crtc
->yoffset
= yoffset
;
890 aty128_bpp_to_var(int pix_width
, struct fb_var_screeninfo
*var
)
893 /* fill in pixel info */
895 case CRTC_PIX_WIDTH_8BPP
:
896 var
->bits_per_pixel
= 8;
899 var
->green
.offset
= 0;
900 var
->green
.length
= 8;
901 var
->blue
.offset
= 0;
902 var
->blue
.length
= 8;
903 var
->transp
.offset
= 0;
904 var
->transp
.length
= 0;
906 case CRTC_PIX_WIDTH_15BPP
:
907 case CRTC_PIX_WIDTH_16BPP
:
908 var
->bits_per_pixel
= 16;
909 var
->red
.offset
= 10;
911 var
->green
.offset
= 5;
912 var
->green
.length
= 5;
913 var
->blue
.offset
= 0;
914 var
->blue
.length
= 5;
915 var
->transp
.offset
= 0;
916 var
->transp
.length
= 0;
918 case CRTC_PIX_WIDTH_24BPP
:
919 var
->bits_per_pixel
= 24;
920 var
->red
.offset
= 16;
922 var
->green
.offset
= 8;
923 var
->green
.length
= 8;
924 var
->blue
.offset
= 0;
925 var
->blue
.length
= 8;
926 var
->transp
.offset
= 0;
927 var
->transp
.length
= 0;
929 case CRTC_PIX_WIDTH_32BPP
:
930 var
->bits_per_pixel
= 32;
931 var
->red
.offset
= 16;
933 var
->green
.offset
= 8;
934 var
->green
.length
= 8;
935 var
->blue
.offset
= 0;
936 var
->blue
.length
= 8;
937 var
->transp
.offset
= 24;
938 var
->transp
.length
= 8;
941 printk(KERN_ERR
"aty128fb: Invalid pixel width\n");
950 aty128_crtc_to_var(const struct aty128_crtc
*crtc
,
951 struct fb_var_screeninfo
*var
)
953 u32 xres
, yres
, left
, right
, upper
, lower
, hslen
, vslen
, sync
;
954 u32 h_total
, h_disp
, h_sync_strt
, h_sync_dly
, h_sync_wid
, h_sync_pol
;
955 u32 v_total
, v_disp
, v_sync_strt
, v_sync_wid
, v_sync_pol
, c_sync
;
958 /* fun with masking */
959 h_total
= crtc
->h_total
& 0x1ff;
960 h_disp
= (crtc
->h_total
>> 16) & 0xff;
961 h_sync_strt
= (crtc
->h_sync_strt_wid
>> 3) & 0x1ff;
962 h_sync_dly
= crtc
->h_sync_strt_wid
& 0x7;
963 h_sync_wid
= (crtc
->h_sync_strt_wid
>> 16) & 0x3f;
964 h_sync_pol
= (crtc
->h_sync_strt_wid
>> 23) & 0x1;
965 v_total
= crtc
->v_total
& 0x7ff;
966 v_disp
= (crtc
->v_total
>> 16) & 0x7ff;
967 v_sync_strt
= crtc
->v_sync_strt_wid
& 0x7ff;
968 v_sync_wid
= (crtc
->v_sync_strt_wid
>> 16) & 0x1f;
969 v_sync_pol
= (crtc
->v_sync_strt_wid
>> 23) & 0x1;
970 c_sync
= crtc
->gen_cntl
& CRTC_CSYNC_EN
? 1 : 0;
971 pix_width
= crtc
->gen_cntl
& CRTC_PIX_WIDTH_MASK
;
974 xres
= (h_disp
+ 1) << 3;
976 left
= ((h_total
- h_sync_strt
- h_sync_wid
) << 3) - h_sync_dly
;
977 right
= ((h_sync_strt
- h_disp
) << 3) + h_sync_dly
;
978 hslen
= h_sync_wid
<< 3;
979 upper
= v_total
- v_sync_strt
- v_sync_wid
;
980 lower
= v_sync_strt
- v_disp
;
982 sync
= (h_sync_pol
? 0 : FB_SYNC_HOR_HIGH_ACT
) |
983 (v_sync_pol
? 0 : FB_SYNC_VERT_HIGH_ACT
) |
984 (c_sync
? FB_SYNC_COMP_HIGH_ACT
: 0);
986 aty128_bpp_to_var(pix_width
, var
);
990 var
->xres_virtual
= crtc
->vxres
;
991 var
->yres_virtual
= crtc
->vyres
;
992 var
->xoffset
= crtc
->xoffset
;
993 var
->yoffset
= crtc
->yoffset
;
994 var
->left_margin
= left
;
995 var
->right_margin
= right
;
996 var
->upper_margin
= upper
;
997 var
->lower_margin
= lower
;
998 var
->hsync_len
= hslen
;
999 var
->vsync_len
= vslen
;
1001 var
->vmode
= FB_VMODE_NONINTERLACED
;
1007 aty128_set_pll(struct aty128_pll
*pll
, const struct fb_info_aty128
*info
)
1011 unsigned char post_conv
[] = /* register values for post dividers */
1012 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1014 /* select PPLL_DIV_3 */
1015 aty_st_le32(CLOCK_CNTL_INDEX
, aty_ld_le32(CLOCK_CNTL_INDEX
) | (3 << 8));
1018 aty_st_pll(PPLL_CNTL
,
1019 aty_ld_pll(PPLL_CNTL
) | PPLL_RESET
| PPLL_ATOMIC_UPDATE_EN
);
1021 /* write the reference divider */
1022 aty_pll_wait_readupdate(info
);
1023 aty_st_pll(PPLL_REF_DIV
, info
->constants
.ref_divider
& 0x3ff);
1024 aty_pll_writeupdate(info
);
1026 div3
= aty_ld_pll(PPLL_DIV_3
);
1027 div3
&= ~PPLL_FB3_DIV_MASK
;
1028 div3
|= pll
->feedback_divider
;
1029 div3
&= ~PPLL_POST3_DIV_MASK
;
1030 div3
|= post_conv
[pll
->post_divider
] << 16;
1032 /* write feedback and post dividers */
1033 aty_pll_wait_readupdate(info
);
1034 aty_st_pll(PPLL_DIV_3
, div3
);
1035 aty_pll_writeupdate(info
);
1037 aty_pll_wait_readupdate(info
);
1038 aty_st_pll(HTOTAL_CNTL
, 0); /* no horiz crtc adjustment */
1039 aty_pll_writeupdate(info
);
1041 /* clear the reset, just in case */
1042 aty_st_pll(PPLL_CNTL
, aty_ld_pll(PPLL_CNTL
) & ~PPLL_RESET
);
1047 aty128_var_to_pll(u32 period_in_ps
, struct aty128_pll
*pll
,
1048 const struct fb_info_aty128
*info
)
1050 const struct aty128_constants c
= info
->constants
;
1051 unsigned char post_dividers
[] = {1,2,4,8,3,6,12};
1053 u32 vclk
; /* in .01 MHz */
1057 vclk
= 100000000 / period_in_ps
; /* convert units to 10 kHz */
1059 /* adjust pixel clock if necessary */
1060 if (vclk
> c
.ppll_max
)
1062 if (vclk
* 12 < c
.ppll_min
)
1063 vclk
= c
.ppll_min
/12;
1065 /* now, find an acceptable divider */
1066 for (i
= 0; i
< sizeof(post_dividers
); i
++) {
1067 output_freq
= post_dividers
[i
] * vclk
;
1068 if (output_freq
>= c
.ppll_min
&& output_freq
<= c
.ppll_max
)
1072 /* calculate feedback divider */
1073 n
= c
.ref_divider
* output_freq
;
1076 pll
->post_divider
= post_dividers
[i
];
1077 pll
->feedback_divider
= round_div(n
, d
);
1080 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1081 "vclk_per: %d\n", pll
->post_divider
,
1082 pll
->feedback_divider
, vclk
, output_freq
,
1083 c
.ref_divider
, period_in_ps
);
1090 aty128_pll_to_var(const struct aty128_pll
*pll
, struct fb_var_screeninfo
*var
,
1091 const struct fb_info_aty128
*info
)
1093 var
->pixclock
= 100000000 / pll
->vclk
;
1100 aty128_set_fifo(const struct aty128_ddafifo
*dsp
,
1101 const struct fb_info_aty128
*info
)
1103 aty_st_le32(DDA_CONFIG
, dsp
->dda_config
);
1104 aty_st_le32(DDA_ON_OFF
, dsp
->dda_on_off
);
1109 aty128_ddafifo(struct aty128_ddafifo
*dsp
,
1110 const struct aty128_pll
*pll
,
1112 const struct fb_info_aty128
*info
)
1114 const struct aty128_meminfo
*m
= info
->mem
;
1115 u32 xclk
= info
->constants
.xclk
;
1116 u32 fifo_width
= info
->constants
.fifo_width
;
1117 u32 fifo_depth
= info
->constants
.fifo_depth
;
1118 s32 x
, b
, p
, ron
, roff
;
1121 /* 15bpp is really 16bpp */
1125 n
= xclk
* fifo_width
;
1126 d
= pll
->vclk
* bpp
;
1127 x
= round_div(n
, d
);
1130 3 * ((m
->Trcd
- 2 > 0) ? m
->Trcd
- 2 : 0) +
1149 x
= round_div(n
, d
);
1150 roff
= x
* (fifo_depth
- 4);
1152 if ((ron
+ m
->Rloop
) >= roff
) {
1153 printk(KERN_ERR
"aty128fb: Mode out of range!\n");
1157 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1158 p
, m
->Rloop
, x
, ron
, roff
);
1160 dsp
->dda_config
= p
<< 16 | m
->Rloop
<< 20 | x
;
1161 dsp
->dda_on_off
= ron
<< 16 | roff
;
1168 * This actually sets the video mode.
1171 aty128_set_par(struct aty128fb_par
*par
,
1172 struct fb_info_aty128
*info
)
1176 info
->current_par
= *par
;
1178 if (info
->blitter_may_be_busy
)
1179 wait_for_idle(info
);
1181 /* clear all registers that may interfere with mode setting */
1182 aty_st_le32(OVR_CLR
, 0);
1183 aty_st_le32(OVR_WID_LEFT_RIGHT
, 0);
1184 aty_st_le32(OVR_WID_TOP_BOTTOM
, 0);
1185 aty_st_le32(OV0_SCALE_CNTL
, 0);
1186 aty_st_le32(MPP_TB_CONFIG
, 0);
1187 aty_st_le32(MPP_GP_CONFIG
, 0);
1188 aty_st_le32(SUBPIC_CNTL
, 0);
1189 aty_st_le32(VIPH_CONTROL
, 0);
1190 aty_st_le32(I2C_CNTL_1
, 0); /* turn off i2c */
1191 aty_st_le32(GEN_INT_CNTL
, 0); /* turn off interrupts */
1192 aty_st_le32(CAP0_TRIG_CNTL
, 0);
1193 aty_st_le32(CAP1_TRIG_CNTL
, 0);
1195 aty_st_8(CRTC_EXT_CNTL
+ 1, 4); /* turn video off */
1197 aty128_set_crtc(&par
->crtc
, info
);
1198 aty128_set_pll(&par
->pll
, info
);
1199 aty128_set_fifo(&par
->fifo_reg
, info
);
1201 config
= aty_ld_le32(CONFIG_CNTL
) & ~3;
1203 #if defined(__BIG_ENDIAN)
1204 if (par
->crtc
.bpp
>= 24)
1205 config
|= 2; /* make aperture do 32 byte swapping */
1206 else if (par
->crtc
.bpp
> 8)
1207 config
|= 1; /* make aperture do 16 byte swapping */
1210 aty_st_le32(CONFIG_CNTL
, config
);
1211 aty_st_8(CRTC_EXT_CNTL
+ 1, 0); /* turn the video back on */
1213 if (par
->accel_flags
& FB_ACCELF_TEXT
)
1214 aty128_init_engine(par
, info
);
1216 #ifdef CONFIG_FB_COMPAT_XPMAC
1217 if (!console_fb_info
|| console_fb_info
== &info
->fb_info
) {
1218 struct fb_var_screeninfo var
;
1221 display_info
.height
= ((par
->crtc
.v_total
>> 16) & 0x7ff) + 1;
1222 display_info
.width
= (((par
->crtc
.h_total
>> 16) & 0xff) + 1) << 3;
1223 display_info
.depth
= par
->crtc
.bpp
;
1224 display_info
.pitch
= (par
->crtc
.vxres
* par
->crtc
.bpp
) >> 3;
1225 aty128_encode_var(&var
, par
, info
);
1226 if (mac_var_to_vmode(&var
, &vmode
, &cmode
))
1227 display_info
.mode
= 0;
1229 display_info
.mode
= vmode
;
1230 strcpy(display_info
.name
, aty128fb_name
);
1231 display_info
.fb_address
= info
->frame_buffer_phys
;
1232 display_info
.cmap_adr_address
= 0;
1233 display_info
.cmap_data_address
= 0;
1234 display_info
.disp_reg_address
= info
->regbase_phys
;
1236 #endif /* CONFIG_FB_COMPAT_XPMAC */
1240 * encode/decode the User Defined Part of the Display
1244 aty128_decode_var(struct fb_var_screeninfo
*var
, struct aty128fb_par
*par
,
1245 const struct fb_info_aty128
*info
)
1249 if ((err
= aty128_var_to_crtc(var
, &par
->crtc
, info
)))
1252 if ((err
= aty128_var_to_pll(var
->pixclock
, &par
->pll
, info
)))
1255 if ((err
= aty128_ddafifo(&par
->fifo_reg
, &par
->pll
, par
->crtc
.bpp
, info
)))
1258 if (var
->accel_flags
& FB_ACCELF_TEXT
)
1259 par
->accel_flags
= FB_ACCELF_TEXT
;
1261 par
->accel_flags
= 0;
1268 aty128_encode_var(struct fb_var_screeninfo
*var
,
1269 const struct aty128fb_par
*par
,
1270 const struct fb_info_aty128
*info
)
1274 if ((err
= aty128_crtc_to_var(&par
->crtc
, var
)))
1277 if ((err
= aty128_pll_to_var(&par
->pll
, var
, info
)))
1280 var
->red
.msb_right
= 0;
1281 var
->green
.msb_right
= 0;
1282 var
->blue
.msb_right
= 0;
1283 var
->transp
.msb_right
= 0;
1290 var
->accel_flags
= par
->accel_flags
;
1297 * Get the User Defined Part of the Display
1301 aty128fb_get_var(struct fb_var_screeninfo
*var
, int con
, struct fb_info
*fb
)
1303 const struct fb_info_aty128
*info
= (struct fb_info_aty128
*)fb
;
1306 aty128_encode_var(var
, &info
->default_par
, info
);
1308 *var
= fb_display
[con
].var
;
1314 * Set the User Defined Part of the Display
1318 aty128fb_set_var(struct fb_var_screeninfo
*var
, int con
, struct fb_info
*fb
)
1320 struct fb_info_aty128
*info
= (struct fb_info_aty128
*)fb
;
1321 struct aty128fb_par par
;
1322 struct display
*display
;
1323 int oldxres
, oldyres
, oldvxres
, oldvyres
, oldbpp
, oldaccel
;
1326 display
= (con
>= 0) ? &fb_display
[con
] : fb
->disp
;
1328 /* basic (in)sanity checks */
1333 if (var
->xres
> var
->xres_virtual
)
1334 var
->xres_virtual
= var
->xres
;
1335 if (var
->yres
> var
->yres_virtual
)
1336 var
->yres_virtual
= var
->yres
;
1338 switch (var
->bits_per_pixel
) {
1340 var
->bits_per_pixel
= 8;
1343 var
->bits_per_pixel
= 16;
1346 var
->bits_per_pixel
= 24;
1349 var
->bits_per_pixel
= 32;
1355 if ((err
= aty128_decode_var(var
, &par
, info
)))
1358 aty128_encode_var(var
, &par
, info
);
1360 if ((var
->activate
& FB_ACTIVATE_MASK
) != FB_ACTIVATE_NOW
)
1363 oldxres
= display
->var
.xres
;
1364 oldyres
= display
->var
.yres
;
1365 oldvxres
= display
->var
.xres_virtual
;
1366 oldvyres
= display
->var
.yres_virtual
;
1367 oldbpp
= display
->var
.bits_per_pixel
;
1368 oldaccel
= display
->var
.accel_flags
;
1369 display
->var
= *var
;
1370 if (oldxres
!= var
->xres
|| oldyres
!= var
->yres
||
1371 oldvxres
!= var
->xres_virtual
|| oldvyres
!= var
->yres_virtual
||
1372 oldbpp
!= var
->bits_per_pixel
|| oldaccel
!= var
->accel_flags
) {
1374 struct fb_fix_screeninfo fix
;
1376 aty128_encode_fix(&fix
, &par
, info
);
1377 display
->screen_base
= (char *)info
->frame_buffer
;
1378 display
->visual
= fix
.visual
;
1379 display
->type
= fix
.type
;
1380 display
->type_aux
= fix
.type_aux
;
1381 display
->ypanstep
= fix
.ypanstep
;
1382 display
->ywrapstep
= fix
.ywrapstep
;
1383 display
->line_length
= fix
.line_length
;
1384 display
->can_soft_blank
= 1;
1385 display
->inverse
= 0;
1387 accel
= var
->accel_flags
& FB_ACCELF_TEXT
;
1388 aty128_set_disp(display
, info
, par
.crtc
.bpp
, accel
);
1391 display
->scrollmode
= SCROLL_YNOMOVE
;
1393 display
->scrollmode
= SCROLL_YREDRAW
;
1395 if (info
->fb_info
.changevar
)
1396 (*info
->fb_info
.changevar
)(con
);
1399 if (!info
->fb_info
.display_fg
|| info
->fb_info
.display_fg
->vc_num
== con
)
1400 aty128_set_par(&par
, info
);
1402 if (oldbpp
!= var
->bits_per_pixel
) {
1403 if ((err
= fb_alloc_cmap(&display
->cmap
, 0, 0)))
1405 do_install_cmap(con
, &info
->fb_info
);
1413 aty128_set_disp(struct display
*disp
,
1414 struct fb_info_aty128
*info
, int bpp
, int accel
)
1417 #ifdef FBCON_HAS_CFB8
1419 info
->dispsw
= accel
? fbcon_aty128_8
: fbcon_cfb8
;
1420 disp
->dispsw
= &info
->dispsw
;
1423 #ifdef FBCON_HAS_CFB16
1426 info
->dispsw
= accel
? fbcon_aty128_16
: fbcon_cfb16
;
1427 disp
->dispsw
= &info
->dispsw
;
1428 disp
->dispsw_data
= info
->fbcon_cmap
.cfb16
;
1431 #ifdef FBCON_HAS_CFB24
1433 info
->dispsw
= accel
? fbcon_aty128_24
: fbcon_cfb24
;
1434 disp
->dispsw
= &info
->dispsw
;
1435 disp
->dispsw_data
= info
->fbcon_cmap
.cfb24
;
1438 #ifdef FBCON_HAS_CFB32
1440 info
->dispsw
= accel
? fbcon_aty128_32
: fbcon_cfb32
;
1441 disp
->dispsw
= &info
->dispsw
;
1442 disp
->dispsw_data
= info
->fbcon_cmap
.cfb32
;
1446 disp
->dispsw
= &fbcon_dummy
;
1452 aty128_encode_fix(struct fb_fix_screeninfo
*fix
,
1453 struct aty128fb_par
*par
,
1454 const struct fb_info_aty128
*info
)
1456 memset(fix
, 0, sizeof(struct fb_fix_screeninfo
));
1458 strcpy(fix
->id
, aty128fb_name
);
1460 fix
->smem_start
= (unsigned long)info
->frame_buffer_phys
;
1461 fix
->mmio_start
= (unsigned long)info
->regbase_phys
;
1463 fix
->smem_len
= info
->vram_size
;
1464 fix
->mmio_len
= 0x1fff;
1466 fix
->type
= FB_TYPE_PACKED_PIXELS
;
1468 fix
->line_length
= (par
->crtc
.vxres
* par
->crtc
.bpp
) >> 3;
1469 fix
->visual
= par
->crtc
.bpp
<= 8 ? FB_VISUAL_PSEUDOCOLOR
1470 : FB_VISUAL_DIRECTCOLOR
;
1475 fix
->accel
= FB_ACCEL_ATI_RAGE128
;
1482 * Get the Fixed Part of the Display
1485 aty128fb_get_fix(struct fb_fix_screeninfo
*fix
, int con
, struct fb_info
*fb
)
1487 const struct fb_info_aty128
*info
= (struct fb_info_aty128
*)fb
;
1488 struct aty128fb_par par
;
1491 par
= info
->default_par
;
1493 aty128_decode_var(&fb_display
[con
].var
, &par
, info
);
1495 aty128_encode_fix(fix
, &par
, info
);
1502 * Pan or Wrap the Display
1504 * Not supported (yet!)
1507 aty128fb_pan_display(struct fb_var_screeninfo
*var
, int con
,
1510 struct fb_info_aty128
*info
= (struct fb_info_aty128
*)fb
;
1511 struct aty128fb_par
*par
= &info
->current_par
;
1512 u32 xoffset
, yoffset
;
1516 xres
= (((par
->crtc
.h_total
>> 16) & 0xff) + 1) << 3;
1517 yres
= ((par
->crtc
.v_total
>> 16) & 0x7ff) + 1;
1519 xoffset
= (var
->xoffset
+7) & ~7;
1520 yoffset
= var
->yoffset
;
1522 if (xoffset
+xres
> par
->crtc
.vxres
|| yoffset
+yres
> par
->crtc
.vyres
)
1525 par
->crtc
.xoffset
= xoffset
;
1526 par
->crtc
.yoffset
= yoffset
;
1528 offset
= ((yoffset
* par
->crtc
.vxres
+ xoffset
) * par
->crtc
.bpp
) >> 6;
1530 aty_st_le32(CRTC_OFFSET
, offset
);
1541 aty128fb_get_cmap(struct fb_cmap
*cmap
, int kspc
, int con
,
1542 struct fb_info
*info
)
1545 fb_copy_cmap(&info
->cmap
, cmap
, kspc
? 0 : 2);
1547 struct fb_info_aty128 fb
= (struct fb_info_aty128
*)info
;
1549 if (con
== fb
->currcon
) /* current console? */
1550 return fb_get_cmap(cmap
, kspc
, aty128_getcolreg
, info
);
1551 else if (fb_display
[con
].cmap
.len
) /* non default colormap? */
1552 fb_copy_cmap(&fb_display
[con
].cmap
, cmap
, kspc
? 0 : 2);
1554 int size
= (fb_display
[con
].var
.bits_per_pixel
<= 8) ? 256 : 32;
1555 fb_copy_cmap(fb_default_cmap(size
), cmap
, kspc
? 0 : 2);
1567 aty128fb_set_cmap(struct fb_cmap
*cmap
, int kspc
, int con
,
1568 struct fb_info
*info
)
1571 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)info
;
1572 struct display
*disp
;
1575 disp
= &fb_display
[con
];
1579 if (!disp
->cmap
.len
) { /* no colormap allocated? */
1580 int size
= (disp
->var
.bits_per_pixel
<= 8) ? 256 : 32;
1581 if ((err
= fb_alloc_cmap(&disp
->cmap
, size
, 0)))
1585 if (con
== fb
->currcon
) /* current console? */
1586 return fb_set_cmap(cmap
, kspc
, aty128_setcolreg
, info
);
1588 fb_copy_cmap(cmap
, &disp
->cmap
, kspc
? 0 : 1);
1594 * Frame Buffer Specific ioctls
1598 aty128fb_ioctl(struct inode
*inode
, struct file
*file
, u_int cmd
,
1599 u_long arg
, int con
, struct fb_info
*info
)
1606 aty128fb_rasterimg(struct fb_info
*info
, int start
)
1608 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)info
;
1610 if (fb
->blitter_may_be_busy
)
1619 aty128fb_setup(char *options
)
1623 if (!options
|| !*options
)
1626 for (this_opt
= strtok(options
, ","); this_opt
;
1627 this_opt
= strtok(NULL
, ",")) {
1628 if (!strncmp(this_opt
, "font:", 5)) {
1633 for (i
= 0; i
< sizeof(fontname
) - 1; i
++)
1634 if (!*p
|| *p
== ' ' || *p
== ',')
1636 memcpy(fontname
, this_opt
+ 5, i
);
1638 } else if (!strncmp(this_opt
, "noaccel", 7)) {
1642 else if(!strncmp(this_opt
, "nomtrr", 6)) {
1647 /* vmode and cmode depreciated */
1648 else if (!strncmp(this_opt
, "vmode:", 6)) {
1649 unsigned int vmode
= simple_strtoul(this_opt
+6, NULL
, 0);
1650 if (vmode
> 0 && vmode
<= VMODE_MAX
)
1651 default_vmode
= vmode
;
1652 } else if (!strncmp(this_opt
, "cmode:", 6)) {
1653 unsigned int cmode
= simple_strtoul(this_opt
+6, NULL
, 0);
1657 default_cmode
= CMODE_8
;
1661 default_cmode
= CMODE_16
;
1665 default_cmode
= CMODE_32
;
1669 #endif /* CONFIG_PPC */
1671 mode_option
= this_opt
;
1675 #endif /* !MODULE */
1683 aty128_init(struct fb_info_aty128
*info
, const char *name
)
1685 struct fb_var_screeninfo var
;
1689 const struct aty128_chip_info
*aci
= &aty128_pci_probe_list
[0];
1690 char *video_card
= "Rage128";
1692 if (!info
->vram_size
) /* may have already been probed */
1693 info
->vram_size
= aty_ld_le32(CONFIG_MEMSIZE
) & 0x03FFFFFF;
1695 /* Get the chip revision */
1696 chip_rev
= (aty_ld_le32(CONFIG_CNTL
) >> 16) & 0x1F;
1698 /* put a name with the face */
1699 while (aci
->name
&& info
->pdev
->device
!= aci
->device
) { aci
++; }
1700 video_card
= (char *)aci
->name
;
1701 info
->chip_gen
= aci
->chip_gen
;
1703 printk(KERN_INFO
"aty128fb: %s [chip rev 0x%x] ", video_card
, chip_rev
);
1705 if (info
->vram_size
% (1024 * 1024) == 0)
1706 printk("%dM %s\n", info
->vram_size
/ (1024*1024), info
->mem
->name
);
1708 printk("%dk %s\n", info
->vram_size
/ 1024, info
->mem
->name
);
1711 strcpy(info
->fb_info
.modename
, aty128fb_name
);
1712 info
->fb_info
.node
= -1;
1713 info
->fb_info
.fbops
= &aty128fb_ops
;
1714 info
->fb_info
.disp
= &info
->disp
;
1715 strcpy(info
->fb_info
.fontname
, fontname
);
1716 info
->fb_info
.changevar
= NULL
;
1717 info
->fb_info
.switch_con
= &aty128fbcon_switch
;
1718 info
->fb_info
.updatevar
= NULL
;
1719 info
->fb_info
.blank
= &aty128fbcon_blank
;
1720 info
->fb_info
.flags
= FBINFO_FLAG_DEFAULT
;
1725 memset(&var
, 0, sizeof(var
));
1727 if (_machine
== _MACH_Pmac
) {
1729 if (!mac_find_mode(&var
, &info
->fb_info
, mode_option
, 8))
1733 if (default_vmode
== VMODE_NVRAM
)
1734 default_vmode
= nvram_read_byte(NV_VMODE
);
1736 if (default_cmode
== CMODE_NVRAM
)
1737 default_cmode
= nvram_read_byte(NV_CMODE
);
1739 if (default_vmode
<= 0 || default_vmode
> VMODE_MAX
)
1740 default_vmode
= VMODE_640_480_60
;
1742 if (default_cmode
< CMODE_8
|| default_cmode
> CMODE_32
)
1743 default_cmode
= CMODE_8
;
1745 if (mac_vmode_to_var(default_vmode
, default_cmode
, &var
))
1749 #endif /* CONFIG_PPC */
1751 if (fb_find_mode(&var
, &info
->fb_info
, mode_option
, NULL
, 0,
1752 &defaultmode
, 8) == 0)
1758 var
.accel_flags
&= ~FB_ACCELF_TEXT
;
1760 var
.accel_flags
|= FB_ACCELF_TEXT
;
1762 if (aty128_decode_var(&var
, &info
->default_par
, info
)) {
1763 printk(KERN_ERR
"aty128fb: Cannot set default mode.\n");
1767 /* load up the palette with default colors */
1768 for (j
= 0; j
< 16; j
++) {
1770 info
->palette
[j
].red
= default_red
[k
];
1771 info
->palette
[j
].green
= default_grn
[k
];
1772 info
->palette
[j
].blue
= default_blu
[k
];
1775 /* setup the DAC the way we like it */
1776 dac
= aty_ld_le32(DAC_CNTL
);
1777 dac
|= (DAC_8BIT_EN
| DAC_RANGE_CNTL
);
1779 aty_st_le32(DAC_CNTL
, dac
);
1781 /* turn off bus mastering, just in case */
1782 aty_st_le32(BUS_CNTL
, aty_ld_le32(BUS_CNTL
) | BUS_MASTER_DIS
);
1784 aty128fb_set_var(&var
, -1, &info
->fb_info
);
1785 aty128_init_engine(&info
->default_par
, info
);
1787 board_list
= aty128_board_list_add(board_list
, info
);
1789 if (register_framebuffer(&info
->fb_info
) < 0)
1792 printk(KERN_INFO
"fb%d: %s frame buffer device on %s\n",
1793 GET_FB_IDX(info
->fb_info
.node
), aty128fb_name
, name
);
1795 return 1; /* success! */
1799 /* add a new card to the list ++ajoshi */
1801 fb_info_aty128
*aty128_board_list_add(struct fb_info_aty128
*board_list
,
1802 struct fb_info_aty128
*new_node
)
1804 struct fb_info_aty128
*i_p
= board_list
;
1806 new_node
->next
= NULL
;
1807 if(board_list
== NULL
)
1809 while(i_p
->next
!= NULL
)
1811 i_p
->next
= new_node
;
1821 struct pci_dev
*pdev
= NULL
;
1822 const struct aty128_chip_info
*aci
= &aty128_pci_probe_list
[0];
1824 while (aci
->name
!= NULL
) {
1825 pdev
= pci_find_device(PCI_VENDOR_ID_ATI
, aci
->device
, pdev
);
1826 while (pdev
!= NULL
) {
1827 if (aty128_pci_register(pdev
, aci
) == 0)
1829 pdev
= pci_find_device(PCI_VENDOR_ID_ATI
, aci
->device
, pdev
);
1840 /* register a card ++ajoshi */
1842 aty128_pci_register(struct pci_dev
*pdev
,
1843 const struct aty128_chip_info
*aci
)
1845 struct fb_info_aty128
*info
= NULL
;
1846 u32 fb_addr
, reg_addr
, io_addr
= 0;
1849 fb_addr
= pci_resource_start(pdev
, 0);
1850 if (!request_mem_region(fb_addr
, pci_resource_len(pdev
, 0),
1852 printk(KERN_ERR
"aty128fb: cannot reserve frame buffer memory\n");
1856 reg_addr
= pci_resource_start(pdev
, 2);
1857 if (!request_mem_region(reg_addr
, pci_resource_len(pdev
, 2),
1859 printk(KERN_ERR
"aty128fb: cannot reserve MMIO region\n");
1863 /* We have the resources. Now virtualize them */
1864 info
= kmalloc(sizeof(struct fb_info_aty128
), GFP_ATOMIC
);
1866 printk(KERN_ERR
"aty128fb: can't alloc fb_info_aty128\n");
1869 memset(info
, 0, sizeof(struct fb_info_aty128
));
1871 /* Copy PCI device info into info->pdev */
1876 /* Virtualize mmio region */
1877 info
->regbase_phys
= reg_addr
;
1878 info
->regbase
= ioremap(reg_addr
, 0x1FFF);
1884 info
->io_base
= io_addr
;
1886 /* Grab memory size from the card */
1887 info
->vram_size
= aty_ld_le32(CONFIG_MEMSIZE
) & 0x03FFFFFF;
1889 /* Virtualize the framebuffer */
1890 info
->frame_buffer_phys
= fb_addr
;
1891 info
->frame_buffer
= (u32
)ioremap(fb_addr
, info
->vram_size
);
1893 if (!info
->frame_buffer
) {
1894 iounmap((void *)info
->regbase
);
1898 /* Enable device in PCI config */
1899 err
= pci_enable_device(pdev
);
1901 printk(KERN_ERR
"aty128fb: Cannot enable PCI device: %d\n", err
);
1905 /* If we can't test scratch registers, something is seriously wrong */
1906 if (!register_test(info
)) {
1907 printk(KERN_ERR
"aty128fb: Can't write to video register!\n");
1911 #if !defined(CONFIG_PPC) && !defined(__sparc__)
1912 if (!aty128find_ROM(info
))
1913 printk(KERN_INFO
"aty128fb: Rage128 BIOS not located. Guessing...\n");
1915 aty128_get_pllinfo(info
);
1917 aty128_timings(info
);
1919 if (!aty128_init(info
, "PCI"))
1924 info
->mtrr
.vram
= mtrr_add(info
->frame_buffer_phys
, info
->vram_size
,
1925 MTRR_TYPE_WRCOMB
, 1);
1926 info
->mtrr
.vram_valid
= 1;
1927 /* let there be speed */
1928 printk(KERN_INFO
"aty128fb: Rage128 MTRR set to ON\n");
1930 #endif /* CONFIG_MTRR */
1935 iounmap((void *)info
->frame_buffer
);
1936 iounmap((void *)info
->regbase
);
1940 release_mem_region(pci_resource_start(pdev
, 2),
1941 pci_resource_len(pdev
, 2));
1943 release_mem_region(pci_resource_start(pdev
, 0),
1944 pci_resource_len(pdev
, 0));
1946 release_mem_region(pci_resource_start(pdev
, 1),
1947 pci_resource_len(pdev
, 1));
1950 #endif /* CONFIG_PCI */
1953 /* PPC and Sparc cannot read video ROM */
1954 #if !defined(CONFIG_PPC) && !defined(__sparc__)
1956 aty128find_ROM(struct fb_info_aty128
*info
)
1964 char aty_rom_sig
[] = "761295520"; /* ATI ROM Signature */
1965 char R128_sig
[] = "R128"; /* Rage128 ROM identifier */
1967 for (segstart
=0x000c0000; segstart
<0x000f0000; segstart
+=0x00001000) {
1970 rom_base
= (char *) ioremap(segstart
, 0x1000);
1972 if ((*rom_base
== 0x55) && (((*(rom_base
+ 1)) & 0xff) == 0xaa))
1981 for (i
= 0; (i
< 128 - strlen(aty_rom_sig
)) && (stage
!= 3); i
++) {
1982 if (aty_rom_sig
[0] == *rom
) {
1983 if (strncmp(aty_rom_sig
, rom
, strlen(aty_rom_sig
)) == 0) {
1995 /* ATI signature found. Let's see if it's a Rage128 */
1996 for (i
= 0; (i
< 512) && (stage
!= 4); i
++) {
1997 if (R128_sig
[0] == *rom
) {
1998 if (strncmp(R128_sig
, rom
, strlen(R128_sig
)) == 0) {
2009 bios_seg
= rom_base
;
2010 printk(KERN_INFO
"aty128fb: Rage128 BIOS located at segment %4.4X\n",
2011 (unsigned int)rom_base
);
2020 aty128_get_pllinfo(struct fb_info_aty128
*info
)
2024 u16 bios_header_offset
, pll_info_offset
;
2027 bios_header
= bios_seg
+ 0x48L
;
2028 header_ptr
= bios_header
;
2030 bios_header_offset
= readw(header_ptr
);
2031 bios_header
= bios_seg
+ bios_header_offset
;
2032 bios_header
+= 0x30;
2034 header_ptr
= bios_header
;
2035 pll_info_offset
= readw(header_ptr
);
2036 header_ptr
= bios_seg
+ pll_info_offset
;
2038 memcpy_fromio(&pll
, header_ptr
, 50);
2040 info
->constants
.ppll_max
= pll
.PCLK_max_freq
;
2041 info
->constants
.ppll_min
= pll
.PCLK_min_freq
;
2042 info
->constants
.xclk
= (u32
)pll
.XCLK
;
2043 info
->constants
.ref_divider
= (u32
)pll
.PCLK_ref_divider
;
2044 info
->constants
.dotclock
= (u32
)pll
.PCLK_ref_freq
;
2046 /* free up to be un-used resources. bios_seg is mapped by
2047 * aty128find_ROM() and used by aty128_get_pllinfo()
2049 * TODO: make more elegant. doesn't need to be global */
2053 DBG("ppll_max %d ppll_min %d xclk %d "
2054 "ref_divider %d dotclock %d\n",
2055 info
->constants
.ppll_max
, info
->constants
.ppll_min
,
2056 info
->constants
.xclk
, info
->constants
.ref_divider
,
2057 info
->constants
.dotclock
);
2061 #endif /* !CONFIG_PPC */
2064 /* fill in known card constants if pll_block is not available */
2066 aty128_timings(struct fb_info_aty128
*info
)
2069 /* instead of a table lookup, assume OF has properly
2070 * setup the PLL registers and use their values
2071 * to set the XCLK values and reference divider values */
2073 u32 x_mpll_ref_fb_div
;
2076 unsigned PostDivSet
[] =
2077 { 0, 1, 2, 4, 8, 3, 6, 12 };
2080 if (!info
->constants
.dotclock
)
2081 info
->constants
.dotclock
= 2950;
2084 x_mpll_ref_fb_div
= aty_ld_pll(X_MPLL_REF_FB_DIV
);
2085 xclk_cntl
= aty_ld_pll(XCLK_CNTL
) & 0x7;
2086 Nx
= (x_mpll_ref_fb_div
& 0x00ff00) >> 8;
2087 M
= x_mpll_ref_fb_div
& 0x0000ff;
2089 info
->constants
.xclk
= round_div((2 * Nx
*
2090 info
->constants
.dotclock
), (M
* PostDivSet
[xclk_cntl
]));
2092 info
->constants
.ref_divider
=
2093 aty_ld_pll(PPLL_REF_DIV
) & PPLL_REF_DIV_MASK
;
2096 if (!info
->constants
.ref_divider
) {
2097 info
->constants
.ref_divider
= 0x3b;
2099 aty_st_pll(X_MPLL_REF_FB_DIV
, 0x004c4c1e);
2100 aty_pll_writeupdate(info
);
2102 aty_st_pll(PPLL_REF_DIV
, info
->constants
.ref_divider
);
2103 aty_pll_writeupdate(info
);
2105 /* from documentation */
2106 if (!info
->constants
.ppll_min
)
2107 info
->constants
.ppll_min
= 12500;
2108 if (!info
->constants
.ppll_max
)
2109 info
->constants
.ppll_max
= 25000; /* 23000 on some cards? */
2110 if (!info
->constants
.xclk
)
2111 info
->constants
.xclk
= 0x1d4d; /* same as mclk */
2113 info
->constants
.fifo_width
= 128;
2114 info
->constants
.fifo_depth
= 32;
2116 switch (aty_ld_le32(MEM_CNTL
) & 0x3) {
2118 info
->mem
= &sdr_128
;
2121 info
->mem
= &sdr_sgram
;
2124 info
->mem
= &ddr_sgram
;
2127 info
->mem
= &sdr_sgram
;
2133 aty128fbcon_switch(int con
, struct fb_info
*fb
)
2135 struct fb_info_aty128
*info
= (struct fb_info_aty128
*)fb
;
2136 struct aty128fb_par par
;
2138 /* Do we have to save the colormap? */
2139 if (fb_display
[info
->currcon
].cmap
.len
)
2140 fb_get_cmap(&fb_display
[info
->currcon
].cmap
, 1,
2141 aty128_getcolreg
, fb
);
2143 /* set the current console */
2144 info
->currcon
= con
;
2146 aty128_decode_var(&fb_display
[con
].var
, &par
, info
);
2147 aty128_set_par(&par
, info
);
2149 aty128_set_disp(&fb_display
[con
], info
, par
.crtc
.bpp
,
2150 par
.accel_flags
& FB_ACCELF_TEXT
);
2152 do_install_cmap(con
, fb
);
2159 * Blank the display.
2162 aty128fbcon_blank(int blank
, struct fb_info
*fb
)
2164 struct fb_info_aty128
*info
= (struct fb_info_aty128
*)fb
;
2167 if (blank
& VESA_VSYNC_SUSPEND
)
2169 if (blank
& VESA_HSYNC_SUSPEND
)
2171 if (blank
& VESA_POWERDOWN
)
2174 aty_st_8(CRTC_EXT_CNTL
+1, state
);
2179 * Read a single color register and split it into
2180 * colors/transparent. Return != 0 for invalid regno.
2183 aty128_getcolreg(u_int regno
, u_int
*red
, u_int
*green
, u_int
*blue
,
2184 u_int
*transp
, struct fb_info
*fb
)
2186 struct fb_info_aty128
*info
= (struct fb_info_aty128
*) fb
;
2191 *red
= (info
->palette
[regno
].red
<<8) | info
->palette
[regno
].red
;
2192 *green
= (info
->palette
[regno
].green
<<8) | info
->palette
[regno
].green
;
2193 *blue
= (info
->palette
[regno
].blue
<<8) | info
->palette
[regno
].blue
;
2200 * Set a single color register. The values supplied are already
2201 * rounded down to the hardware's capabilities (according to the
2202 * entries in the var structure). Return != 0 for invalid regno.
2205 aty128_setcolreg(u_int regno
, u_int red
, u_int green
, u_int blue
,
2206 u_int transp
, struct fb_info
*fb
)
2208 struct fb_info_aty128
*info
= (struct fb_info_aty128
*)fb
;
2217 info
->palette
[regno
].red
= red
;
2218 info
->palette
[regno
].green
= green
;
2219 info
->palette
[regno
].blue
= blue
;
2221 /* Note: For now, on M3, we set palette on both heads, which may
2222 * be useless. Can someone with a M3 check this ? */
2224 /* initialize gamma ramp for hi-color+ */
2226 if ((info
->current_par
.crtc
.bpp
> 8) && (regno
== 0)) {
2229 if (info
->chip_gen
== rage_M3
)
2230 aty_st_le32(DAC_CNTL
, aty_ld_le32(DAC_CNTL
) & ~PALETTE_ACCESS_CNTL
);
2232 for (i
=16; i
<256; i
++) {
2233 aty_st_8(PALETTE_INDEX
, i
);
2234 col
= (i
<< 16) | (i
<< 8) | i
;
2235 aty_st_le32(PALETTE_DATA
, col
);
2238 if (info
->chip_gen
== rage_M3
) {
2239 aty_st_le32(DAC_CNTL
, aty_ld_le32(DAC_CNTL
) | PALETTE_ACCESS_CNTL
);
2241 for (i
=16; i
<256; i
++) {
2242 aty_st_8(PALETTE_INDEX
, i
);
2243 col
= (i
<< 16) | (i
<< 8) | i
;
2244 aty_st_le32(PALETTE_DATA
, col
);
2249 /* initialize palette */
2251 if (info
->chip_gen
== rage_M3
)
2252 aty_st_le32(DAC_CNTL
, aty_ld_le32(DAC_CNTL
) & ~PALETTE_ACCESS_CNTL
);
2254 if (info
->current_par
.crtc
.bpp
== 16)
2255 aty_st_8(PALETTE_INDEX
, (regno
<< 3));
2257 aty_st_8(PALETTE_INDEX
, regno
);
2258 col
= (red
<< 16) | (green
<< 8) | blue
;
2259 aty_st_le32(PALETTE_DATA
, col
);
2260 if (info
->chip_gen
== rage_M3
) {
2261 aty_st_le32(DAC_CNTL
, aty_ld_le32(DAC_CNTL
) | PALETTE_ACCESS_CNTL
);
2262 if (info
->current_par
.crtc
.bpp
== 16)
2263 aty_st_8(PALETTE_INDEX
, (regno
<< 3));
2265 aty_st_8(PALETTE_INDEX
, regno
);
2266 aty_st_le32(PALETTE_DATA
, col
);
2270 switch (info
->current_par
.crtc
.bpp
) {
2271 #ifdef FBCON_HAS_CFB16
2273 info
->fbcon_cmap
.cfb16
[regno
] = (regno
<< 10) | (regno
<< 5) |
2277 #ifdef FBCON_HAS_CFB24
2279 info
->fbcon_cmap
.cfb24
[regno
] = (regno
<< 16) | (regno
<< 8) |
2283 #ifdef FBCON_HAS_CFB32
2287 i
= (regno
<< 8) | regno
;
2288 info
->fbcon_cmap
.cfb32
[regno
] = (i
<< 16) | i
;
2298 do_install_cmap(int con
, struct fb_info
*info
)
2300 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)info
;
2302 if (con
!= fb
->currcon
)
2305 if (fb_display
[con
].cmap
.len
)
2306 fb_set_cmap(&fb_display
[con
].cmap
, 1, aty128_setcolreg
, info
);
2308 int size
= (fb_display
[con
].var
.bits_per_pixel
<= 8) ? 256 : 16;
2309 fb_set_cmap(fb_default_cmap(size
), 1, aty128_setcolreg
, info
);
2315 * Accelerated functions
2319 aty128_rectcopy(int srcx
, int srcy
, int dstx
, int dsty
,
2320 u_int width
, u_int height
,
2321 struct fb_info_aty128
*info
)
2323 u32 save_dp_datatype
, save_dp_cntl
, bppval
;
2325 if (!width
|| !height
)
2328 bppval
= bpp_to_depth(info
->current_par
.crtc
.bpp
);
2329 if (bppval
== DST_24BPP
) {
2333 } else if (bppval
== -EINVAL
) {
2334 printk("aty128fb: invalid depth\n");
2338 wait_for_fifo(2, info
);
2339 save_dp_datatype
= aty_ld_le32(DP_DATATYPE
);
2340 save_dp_cntl
= aty_ld_le32(DP_CNTL
);
2342 wait_for_fifo(6, info
);
2343 aty_st_le32(SRC_Y_X
, (srcy
<< 16) | srcx
);
2344 aty_st_le32(DP_MIX
, ROP3_SRCCOPY
| DP_SRC_RECT
);
2345 aty_st_le32(DP_CNTL
, DST_X_LEFT_TO_RIGHT
| DST_Y_TOP_TO_BOTTOM
);
2346 aty_st_le32(DP_DATATYPE
, save_dp_datatype
| bppval
| SRC_DSTCOLOR
);
2348 aty_st_le32(DST_Y_X
, (dsty
<< 16) | dstx
);
2349 aty_st_le32(DST_HEIGHT_WIDTH
, (height
<< 16) | width
);
2351 info
->blitter_may_be_busy
= 1;
2353 wait_for_fifo(2, info
);
2354 aty_st_le32(DP_DATATYPE
, save_dp_datatype
);
2355 aty_st_le32(DP_CNTL
, save_dp_cntl
);
2360 * Text mode accelerated functions
2364 fbcon_aty128_bmove(struct display
*p
, int sy
, int sx
, int dy
, int dx
,
2365 int height
, int width
)
2368 sy
*= fontheight(p
);
2370 dy
*= fontheight(p
);
2371 width
*= fontwidth(p
);
2372 height
*= fontheight(p
);
2374 aty128_rectcopy(sx
, sy
, dx
, dy
, width
, height
,
2375 (struct fb_info_aty128
*)p
->fb_info
);
2379 #ifdef FBCON_HAS_CFB8
2380 static void fbcon_aty8_putc(struct vc_data
*conp
, struct display
*p
,
2381 int c
, int yy
, int xx
)
2383 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2385 if (fb
->blitter_may_be_busy
)
2388 fbcon_cfb8_putc(conp
, p
, c
, yy
, xx
);
2392 static void fbcon_aty8_putcs(struct vc_data
*conp
, struct display
*p
,
2393 const unsigned short *s
, int count
,
2396 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2398 if (fb
->blitter_may_be_busy
)
2401 fbcon_cfb8_putcs(conp
, p
, s
, count
, yy
, xx
);
2405 static void fbcon_aty8_clear_margins(struct vc_data
*conp
,
2406 struct display
*p
, int bottom_only
)
2408 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2410 if (fb
->blitter_may_be_busy
)
2413 fbcon_cfb8_clear_margins(conp
, p
, bottom_only
);
2416 static struct display_switch fbcon_aty128_8
= {
2417 fbcon_cfb8_setup
, fbcon_aty128_bmove
, fbcon_cfb8_clear
,
2418 fbcon_aty8_putc
, fbcon_aty8_putcs
, fbcon_cfb8_revc
, NULL
, NULL
,
2419 fbcon_aty8_clear_margins
,
2420 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2423 #ifdef FBCON_HAS_CFB16
2424 static void fbcon_aty16_putc(struct vc_data
*conp
, struct display
*p
,
2425 int c
, int yy
, int xx
)
2427 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2429 if (fb
->blitter_may_be_busy
)
2432 fbcon_cfb16_putc(conp
, p
, c
, yy
, xx
);
2436 static void fbcon_aty16_putcs(struct vc_data
*conp
, struct display
*p
,
2437 const unsigned short *s
, int count
,
2440 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2442 if (fb
->blitter_may_be_busy
)
2445 fbcon_cfb16_putcs(conp
, p
, s
, count
, yy
, xx
);
2449 static void fbcon_aty16_clear_margins(struct vc_data
*conp
,
2450 struct display
*p
, int bottom_only
)
2452 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2454 if (fb
->blitter_may_be_busy
)
2457 fbcon_cfb16_clear_margins(conp
, p
, bottom_only
);
2460 static struct display_switch fbcon_aty128_16
= {
2461 fbcon_cfb16_setup
, fbcon_aty128_bmove
, fbcon_cfb16_clear
,
2462 fbcon_aty16_putc
, fbcon_aty16_putcs
, fbcon_cfb16_revc
, NULL
, NULL
,
2463 fbcon_aty16_clear_margins
,
2464 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2467 #ifdef FBCON_HAS_CFB24
2468 static void fbcon_aty24_putc(struct vc_data
*conp
, struct display
*p
,
2469 int c
, int yy
, int xx
)
2471 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2473 if (fb
->blitter_may_be_busy
)
2476 fbcon_cfb24_putc(conp
, p
, c
, yy
, xx
);
2480 static void fbcon_aty24_putcs(struct vc_data
*conp
, struct display
*p
,
2481 const unsigned short *s
, int count
,
2484 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2486 if (fb
->blitter_may_be_busy
)
2489 fbcon_cfb24_putcs(conp
, p
, s
, count
, yy
, xx
);
2493 static void fbcon_aty24_clear_margins(struct vc_data
*conp
,
2494 struct display
*p
, int bottom_only
)
2496 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2498 if (fb
->blitter_may_be_busy
)
2501 fbcon_cfb24_clear_margins(conp
, p
, bottom_only
);
2504 static struct display_switch fbcon_aty128_24
= {
2505 fbcon_cfb24_setup
, fbcon_aty128_bmove
, fbcon_cfb24_clear
,
2506 fbcon_aty24_putc
, fbcon_aty24_putcs
, fbcon_cfb24_revc
, NULL
, NULL
,
2507 fbcon_aty24_clear_margins
,
2508 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2511 #ifdef FBCON_HAS_CFB32
2512 static void fbcon_aty32_putc(struct vc_data
*conp
, struct display
*p
,
2513 int c
, int yy
, int xx
)
2515 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2517 if (fb
->blitter_may_be_busy
)
2520 fbcon_cfb32_putc(conp
, p
, c
, yy
, xx
);
2524 static void fbcon_aty32_putcs(struct vc_data
*conp
, struct display
*p
,
2525 const unsigned short *s
, int count
,
2528 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2530 if (fb
->blitter_may_be_busy
)
2533 fbcon_cfb32_putcs(conp
, p
, s
, count
, yy
, xx
);
2537 static void fbcon_aty32_clear_margins(struct vc_data
*conp
,
2538 struct display
*p
, int bottom_only
)
2540 struct fb_info_aty128
*fb
= (struct fb_info_aty128
*)(p
->fb_info
);
2542 if (fb
->blitter_may_be_busy
)
2545 fbcon_cfb32_clear_margins(conp
, p
, bottom_only
);
2548 static struct display_switch fbcon_aty128_32
= {
2549 fbcon_cfb32_setup
, fbcon_aty128_bmove
, fbcon_cfb32_clear
,
2550 fbcon_aty32_putc
, fbcon_aty32_putcs
, fbcon_cfb32_revc
, NULL
, NULL
,
2551 fbcon_aty32_clear_margins
,
2552 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2557 MODULE_AUTHOR("(c)1999-2000 Brad Douglas <brad@neruo.com>");
2558 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2568 cleanup_module(void)
2570 struct fb_info_aty128
*info
= board_list
;
2572 while (board_list
) {
2574 board_list
= board_list
->next
;
2576 unregister_framebuffer(&info
->fb_info
);
2578 if (info
->mtrr
.vram_valid
)
2579 mtrr_del(info
->mtrr
.vram
, info
->frame_buffer_phys
,
2581 #endif /* CONFIG_MTRR */
2582 iounmap(info
->regbase
);
2583 iounmap(&info
->frame_buffer
);
2585 release_mem_region(pci_resource_start(info
->pdev
, 0),
2586 pci_resource_len(info
->pdev
, 0));
2587 release_mem_region(pci_resource_start(info
->pdev
, 1),
2588 pci_resource_len(info
->pdev
, 1));
2589 release_mem_region(pci_resource_start(info
->pdev
, 2),
2590 pci_resource_len(info
->pdev
, 2));