?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
This is pre8 ...
[linux-2.6/linux-mips.git] / drivers / video / aty128fb.c
blob0770f4448fa2f0fe4899f0b56bd54e35003f702d
1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2000, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Based off of Geert's atyfb.c and vfb.c.
11 *
12 * TODO:
13 * - panning
14 * - monitor sensing (DDC)
15 * - virtual display
16 * - other platform support (only ppc/x86 supported)
17 * - hardware cursor support
18 * - ioctl()'s
19 *
20 * Please cc: your patches to brad@neruo.com.
21 */
22
23 /*
24 * A special note of gratitude to ATI's devrel for providing documentation,
25 * example code and hardware. Thanks Nitya. -atong and brad
26 */
27
28
29 #include <linux/config.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/errno.h>
33 #include <linux/string.h>
34 #include <linux/mm.h>
35 #include <linux/tty.h>
36 #include <linux/malloc.h>
37 #include <linux/vmalloc.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <asm/uaccess.h>
41 #include <linux/fb.h>
42 #include <linux/init.h>
43 #include <linux/selection.h>
44 #include <linux/console.h>
45 #include <linux/pci.h>
46 #include <linux/ioport.h>
47 #include <asm/io.h>
48
49 #ifdef CONFIG_PPC
50 #include <asm/prom.h>
51 #include <asm/pci-bridge.h>
52 #include <video/macmodes.h>
53 #ifdef CONFIG_NVRAM
54 #include <linux/nvram.h>
55 #endif
56 #endif
57
58 #ifdef CONFIG_FB_COMPAT_XPMAC
59 #include <asm/vc_ioctl.h>
60 #endif
61
62 #include <video/fbcon.h>
63 #include <video/fbcon-cfb8.h>
64 #include <video/fbcon-cfb16.h>
65 #include <video/fbcon-cfb24.h>
66 #include <video/fbcon-cfb32.h>
67
68 #ifdef CONFIG_MTRR
69 #include <asm/mtrr.h>
70 #endif
71
72 #include "aty128.h"
73
74 /* Debug flag */
75 #undef DEBUG
76
77 #ifdef DEBUG
78 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
79 #else
80 #define DBG(fmt, args...)
81 #endif
82
83 #ifndef CONFIG_PPC
84 /* default mode */
85 static struct fb_var_screeninfo default_var __initdata = {
86 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
87 640, 480, 640, 480, 0, 0, 8, 0,
88 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
89 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
90 0, FB_VMODE_NONINTERLACED
91 };
92
93 #else /* CONFIG_PPC */
94 /* default to 1024x768 at 75Hz on PPC - this will work
95 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
96 static struct fb_var_screeninfo default_var = {
97 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
98 1024, 768, 1024, 768, 0, 0, 8, 0,
99 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
100 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
101 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
102 };
103 #endif /* CONFIG_PPC */
104
105 #ifndef MODULE
106 /* default modedb mode */
107 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
108 static struct fb_videomode defaultmode __initdata = {
109 refresh: 60,
110 xres: 640,
111 yres: 480,
112 pixclock: 39722,
113 left_margin: 48,
114 right_margin: 16,
115 upper_margin: 33,
116 lower_margin: 10,
117 hsync_len: 96,
118 vsync_len: 2,
119 sync: 0,
120 vmode: FB_VMODE_NONINTERLACED
121 };
122 #endif /* MODULE */
123
124 /* struct to hold chip description information */
125 struct aty128_chip_info {
126 const char *name;
127 unsigned short device;
128 int chip_gen;
129 };
130
131 /* Chip generations */
132 enum {
133 rage_128,
134 rage_128_pro,
135 rage_M3
136 };
137
138 /* supported Rage128 chipsets */
139 static const struct aty128_chip_info aty128_pci_probe_list[] __initdata =
140 {
141 {"Rage128 RE (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RE, rage_128},
142 {"Rage128 RF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RF, rage_128},
143 {"Rage128 RK (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RK, rage_128},
144 {"Rage128 RL (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RL, rage_128},
145 {"Rage128 Pro PF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_PF, rage_128_pro},
146 {"Rage128 Pro PR (PCI)", PCI_DEVICE_ID_ATI_RAGE128_PR, rage_128_pro},
147 {"Rage Mobility M3 (PCI)", PCI_DEVICE_ID_ATI_RAGE128_LE, rage_M3},
148 {"Rage Mobility M3 (AGP)", PCI_DEVICE_ID_ATI_RAGE128_LF, rage_M3},
149 {NULL, 0, rage_128}
150 };
151
152 /* packed BIOS settings */
153 #ifndef CONFIG_PPC
154 typedef struct {
155 u8 clock_chip_type;
156 u8 struct_size;
157 u8 accelerator_entry;
158 u8 VGA_entry;
159 u16 VGA_table_offset;
160 u16 POST_table_offset;
161 u16 XCLK;
162 u16 MCLK;
163 u8 num_PLL_blocks;
164 u8 size_PLL_blocks;
165 u16 PCLK_ref_freq;
166 u16 PCLK_ref_divider;
167 u32 PCLK_min_freq;
168 u32 PCLK_max_freq;
169 u16 MCLK_ref_freq;
170 u16 MCLK_ref_divider;
171 u32 MCLK_min_freq;
172 u32 MCLK_max_freq;
173 u16 XCLK_ref_freq;
174 u16 XCLK_ref_divider;
175 u32 XCLK_min_freq;
176 u32 XCLK_max_freq;
177 } __attribute__ ((packed)) PLL_BLOCK;
178 #endif /* !CONFIG_PPC */
179
180 /* onboard memory information */
181 struct aty128_meminfo {
182 u8 ML;
183 u8 MB;
184 u8 Trcd;
185 u8 Trp;
186 u8 Twr;
187 u8 CL;
188 u8 Tr2w;
189 u8 LoopLatency;
190 u8 DspOn;
191 u8 Rloop;
192 const char *name;
193 };
194
195 /* various memory configurations */
196 static const struct aty128_meminfo sdr_128 =
197 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
198 static const struct aty128_meminfo sdr_64 =
199 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
200 static const struct aty128_meminfo sdr_sgram =
201 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
202 static const struct aty128_meminfo ddr_sgram =
203 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
204
205 static const char *aty128fb_name = "ATY Rage128";
206 static char fontname[40] __initdata = { 0 };
207 static int noaccel __initdata = 0;
208
209 #ifndef MODULE
210 static const char *mode_option __initdata = NULL;
211 #endif
212 #if !defined(CONFIG_PPC) && !defined(__sparc__)
213 static void *bios_seg = NULL;
214 #endif
215
216 #ifdef CONFIG_PPC
217 #ifdef CONFIG_NVRAM_NOT_DEFINED
218 static int default_vmode __initdata = VMODE_640_480_60;
219 static int default_cmode __initdata = CMODE_8;
220 #else
221 static int default_vmode __initdata = VMODE_NVRAM;
222 static int default_cmode __initdata = CMODE_NVRAM;
223 #endif
224 #endif
225
226 #ifdef CONFIG_MTRR
227 static int mtrr = 1;
228 #endif
229
230 /* PLL constants */
231 struct aty128_constants {
232 u32 dotclock;
233 u32 ppll_min;
234 u32 ppll_max;
235 u32 ref_divider;
236 u32 xclk;
237 u32 fifo_width;
238 u32 fifo_depth;
239 };
240
241 struct aty128_crtc {
242 u32 gen_cntl;
243 u32 ext_cntl;
244 u32 h_total, h_sync_strt_wid;
245 u32 v_total, v_sync_strt_wid;
246 u32 pitch;
247 u32 offset, offset_cntl;
248 u32 xoffset, yoffset;
249 u32 vxres, vyres;
250 u32 bpp;
251 };
252
253 struct aty128_pll {
254 u32 post_divider;
255 u32 feedback_divider;
256 u32 vclk;
257 };
258
259 struct aty128_ddafifo {
260 u32 dda_config;
261 u32 dda_on_off;
262 };
263
264 /* register values for a specific mode */
265 struct aty128fb_par {
266 struct aty128_crtc crtc;
267 struct aty128_pll pll;
268 struct aty128_ddafifo fifo_reg;
269 u32 accel_flags;
270 };
271
272 struct fb_info_aty128 {
273 struct fb_info fb_info;
274 struct fb_info_aty128 *next;
275 struct aty128_constants constants; /* PLL and others */
276 u32 regbase_phys; /* physical mmio */
277 void *regbase; /* remapped mmio */
278 u32 frame_buffer_phys; /* physical fb memory */
279 u32 frame_buffer; /* remaped framebuffer */
280 u32 io_base; /* unmapped io */
281 u32 vram_size; /* onboard video ram */
282 int chip_gen;
283 const struct aty128_meminfo *mem; /* onboard mem info */
284 struct aty128fb_par default_par, current_par;
285 struct display disp;
286 struct display_switch dispsw; /* for cursor and font */
287 struct { u8 red, green, blue, pad; } palette[256];
288 union {
289 #ifdef FBCON_HAS_CFB16
290 u16 cfb16[16];
291 #endif
292 #ifdef FBCON_HAS_CFB24
293 u32 cfb24[16];
294 #endif
295 #ifdef FBCON_HAS_CFB32
296 u32 cfb32[16];
297 #endif
298 } fbcon_cmap;
299 #ifdef CONFIG_PCI
300 struct pci_dev *pdev;
301 #endif
302 #ifdef CONFIG_MTRR
303 struct { int vram; int vram_valid; } mtrr;
304 #endif
305 int currcon;
306 int blitter_may_be_busy;
307 int fifo_slots; /* free slots in FIFO (64 max) */
308 };
309
310 static struct fb_info_aty128 *board_list = NULL;
311
312 #define round_div(n, d) ((n+(d/2))/d)
313
314 /*
315 * Interface used by the world
316 */
317
318 int aty128fb_setup(char *options);
319
320 static int aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con,
321 struct fb_info *info);
322 static int aty128fb_get_var(struct fb_var_screeninfo *var, int con,
323 struct fb_info *info);
324 static int aty128fb_set_var(struct fb_var_screeninfo *var, int con,
325 struct fb_info *info);
326 static int aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
327 struct fb_info *info);
328 static int aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
329 struct fb_info *info);
330 static int aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
331 struct fb_info *fb);
332 static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
333 u_long arg, int con, struct fb_info *info);
334 static int aty128fb_rasterimg(struct fb_info *info, int start);
335
336
337 /*
338 * Interface to the low level console driver
339 */
340
341 int aty128fb_init(void);
342 static int aty128fbcon_switch(int con, struct fb_info *fb);
343 static void aty128fbcon_blank(int blank, struct fb_info *fb);
344
345 /*
346 * Internal routines
347 */
348
349 static void aty128_encode_fix(struct fb_fix_screeninfo *fix,
350 struct aty128fb_par *par,
351 const struct fb_info_aty128 *info);
352 static void aty128_set_disp(struct display *disp,
353 struct fb_info_aty128 *info, int bpp, int accel);
354 static int aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
355 u_int *transp, struct fb_info *info);
356 static int aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
357 u_int transp, struct fb_info *info);
358 static void do_install_cmap(int con, struct fb_info *info);
359 static int aty128_encode_var(struct fb_var_screeninfo *var,
360 const struct aty128fb_par *par,
361 const struct fb_info_aty128 *info);
362 static int aty128_decode_var(struct fb_var_screeninfo *var,
363 struct aty128fb_par *par,
364 const struct fb_info_aty128 *info);
365 static int aty128_pci_register(struct pci_dev *pdev,
366 const struct aty128_chip_info *aci);
367 static struct fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128
368 *board_list, struct fb_info_aty128 *new_node);
369 #if !defined(CONFIG_PPC) && !defined(__sparc__)
370 static void aty128_get_pllinfo(struct fb_info_aty128 *info);
371 static int aty128find_ROM(struct fb_info_aty128 *info);
372 #endif
373 static void aty128_timings(struct fb_info_aty128 *info);
374 static void aty128_init_engine(const struct aty128fb_par *par,
375 struct fb_info_aty128 *info);
376 static void aty128_reset_engine(const struct fb_info_aty128 *info);
377 static void aty128_flush_pixel_cache(const struct fb_info_aty128 *info);
378 static void do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info);
379 static void wait_for_fifo(u16 entries, struct fb_info_aty128 *info);
380 static void wait_for_idle(struct fb_info_aty128 *info);
381 static u32 bpp_to_depth(u32 bpp);
382
383 #ifdef FBCON_HAS_CFB8
384 static struct display_switch fbcon_aty128_8;
385 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
386 int c, int yy, int xx);
387 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
388 const unsigned short *s, int count,
389 int yy, int xx);
390 #endif
391 #ifdef FBCON_HAS_CFB16
392 static struct display_switch fbcon_aty128_16;
393 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
394 int c, int yy, int xx);
395 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
396 const unsigned short *s, int count,
397 int yy, int xx);
398 #endif
399 #ifdef FBCON_HAS_CFB24
400 static struct display_switch fbcon_aty128_24;
401 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
402 int c, int yy, int xx);
403 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
404 const unsigned short *s, int count,
405 int yy, int xx);
406 #endif
407 #ifdef FBCON_HAS_CFB32
408 static struct display_switch fbcon_aty128_32;
409 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
410 int c, int yy, int xx);
411 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
412 const unsigned short *s, int count,
413 int yy, int xx);
414 #endif
415
416 static struct fb_ops aty128fb_ops = {
417 owner: THIS_MODULE,
418 fb_get_fix: aty128fb_get_fix,
419 fb_get_var: aty128fb_get_var,
420 fb_set_var: aty128fb_set_var,
421 fb_get_cmap: aty128fb_get_cmap,
422 fb_set_cmap: aty128fb_set_cmap,
423 fb_pan_display: aty128fb_pan_display,
424 fb_ioctl: aty128fb_ioctl,
425 fb_rasterimg: aty128fb_rasterimg,
426 };
427
428
429 /*
430 * Functions to read from/write to the mmio registers
431 * - endian conversions may possibly be avoided by
432 * using the other register aperture. TODO.
433 */
434 static inline u32
435 _aty_ld_le32(volatile unsigned int regindex,
436 const struct fb_info_aty128 *info)
437 {
438 u32 val;
439
440 #if defined(__powerpc__)
441 asm("lwbrx %0,%1,%2;eieio" : "=r"(val) : "b"(regindex), "r"(info->regbase));
442 #else
443 val = readl (info->regbase + regindex);
444 #endif
445
446 return val;
447 }
448
449 static inline void
450 _aty_st_le32(volatile unsigned int regindex, u32 val,
451 const struct fb_info_aty128 *info)
452 {
453 #if defined(__powerpc__)
454 asm("stwbrx %0,%1,%2;eieio" : : "r"(val), "b"(regindex),
455 "r"(info->regbase) : "memory");
456 #else
457 writel (val, info->regbase + regindex);
458 #endif
459 }
460
461 static inline u8
462 _aty_ld_8(unsigned int regindex, const struct fb_info_aty128 *info)
463 {
464 return readb (info->regbase + regindex);
465 }
466
467 static inline void
468 _aty_st_8(unsigned int regindex, u8 val, const struct fb_info_aty128 *info)
469 {
470 writeb (val, info->regbase + regindex);
471 }
472
473 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, info)
474 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, info)
475 #define aty_ld_8(regindex) _aty_ld_8(regindex, info)
476 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, info)
477
478 /*
479 * Functions to read from/write to the pll registers
480 */
481
482 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, info)
483 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, info)
484
485
486 static u32
487 _aty_ld_pll(unsigned int pll_index,
488 const struct fb_info_aty128 *info)
489 {
490 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x1F);
491 return aty_ld_le32(CLOCK_CNTL_DATA);
492 }
493
494
495 static void
496 _aty_st_pll(unsigned int pll_index, u32 val,
497 const struct fb_info_aty128 *info)
498 {
499 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x1F) | PLL_WR_EN);
500 aty_st_le32(CLOCK_CNTL_DATA, val);
501 }
502
503
504 /* return true when the PLL has completed an atomic update */
505 static int
506 aty_pll_readupdate(const struct fb_info_aty128 *info)
507 {
508 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
509 }
510
511
512 static void
513 aty_pll_wait_readupdate(const struct fb_info_aty128 *info)
514 {
515 unsigned long timeout = jiffies + HZ/100; // should be more than enough
516 int reset = 1;
517
518 while (time_before(jiffies, timeout))
519 if (aty_pll_readupdate(info)) {
520 reset = 0;
521 break;
522 }
523
524 if (reset) /* reset engine?? */
525 printk(KERN_DEBUG "aty128fb: PLL write timeout!");
526 }
527
528
529 /* tell PLL to update */
530 static void
531 aty_pll_writeupdate(const struct fb_info_aty128 *info)
532 {
533 aty_pll_wait_readupdate(info);
534
535 aty_st_pll(PPLL_REF_DIV,
536 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
537 }
538
539
540 /* write to the scratch register to test r/w functionality */
541 static int __init
542 register_test(const struct fb_info_aty128 *info)
543 {
544 u32 val;
545 int flag = 0;
546
547 val = aty_ld_le32(BIOS_0_SCRATCH);
548
549 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
550 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
551 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
552
553 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
554 flag = 1;
555 }
556
557 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
558 return flag;
559 }
560
561
562 /*
563 * Accelerator engine functions
564 */
565 static void
566 do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info)
567 {
568 int i;
569
570 for (;;) {
571 for (i = 0; i < 2000000; i++) {
572 info->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
573 if (info->fifo_slots >= entries)
574 return;
575 }
576 aty128_reset_engine(info);
577 }
578 }
579
580
581 static void
582 wait_for_idle(struct fb_info_aty128 *info)
583 {
584 int i;
585
586 do_wait_for_fifo(64, info);
587
588 for (;;) {
589 for (i = 0; i < 2000000; i++) {
590 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
591 aty128_flush_pixel_cache(info);
592 info->blitter_may_be_busy = 0;
593 return;
594 }
595 }
596 aty128_reset_engine(info);
597 }
598 }
599
600
601 static void
602 wait_for_fifo(u16 entries, struct fb_info_aty128 *info)
603 {
604 if (info->fifo_slots < entries)
605 do_wait_for_fifo(64, info);
606 info->fifo_slots -= entries;
607 }
608
609
610 static void
611 aty128_flush_pixel_cache(const struct fb_info_aty128 *info)
612 {
613 int i;
614 u32 tmp;
615
616 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
617 tmp &= ~(0x00ff);
618 tmp |= 0x00ff;
619 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
620
621 for (i = 0; i < 2000000; i++)
622 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
623 break;
624 }
625
626
627 static void
628 aty128_reset_engine(const struct fb_info_aty128 *info)
629 {
630 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
631
632 aty128_flush_pixel_cache(info);
633
634 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
635 mclk_cntl = aty_ld_pll(MCLK_CNTL);
636
637 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
638
639 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
640 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
641 aty_ld_le32(GEN_RESET_CNTL);
642 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
643 aty_ld_le32(GEN_RESET_CNTL);
644
645 aty_st_pll(MCLK_CNTL, mclk_cntl);
646 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
647 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
648
649 /* use old pio mode */
650 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
651
652 DBG("engine reset");
653 }
654
655
656 static void
657 aty128_init_engine(const struct aty128fb_par *par,
658 struct fb_info_aty128 *info)
659 {
660 u32 pitch_value;
661
662 wait_for_idle(info);
663
664 /* 3D scaler not spoken here */
665 wait_for_fifo(1, info);
666 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
667
668 aty128_reset_engine(info);
669
670 pitch_value = par->crtc.pitch;
671 if (par->crtc.bpp == 24) {
672 pitch_value = pitch_value * 3;
673 }
674
675 wait_for_fifo(4, info);
676 /* setup engine offset registers */
677 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
678
679 /* setup engine pitch registers */
680 aty_st_le32(DEFAULT_PITCH, pitch_value);
681
682 /* set the default scissor register to max dimensions */
683 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
684
685 /* set the drawing controls registers */
686 aty_st_le32(DP_GUI_MASTER_CNTL,
687 GMC_SRC_PITCH_OFFSET_DEFAULT |
688 GMC_DST_PITCH_OFFSET_DEFAULT |
689 GMC_SRC_CLIP_DEFAULT |
690 GMC_DST_CLIP_DEFAULT |
691 GMC_BRUSH_SOLIDCOLOR |
692 (bpp_to_depth(par->crtc.bpp) << 8) |
693 GMC_SRC_DSTCOLOR |
694 GMC_BYTE_ORDER_MSB_TO_LSB |
695 GMC_DP_CONVERSION_TEMP_6500 |
696 ROP3_PATCOPY |
697 GMC_DP_SRC_RECT |
698 GMC_3D_FCN_EN_CLR |
699 GMC_DST_CLR_CMP_FCN_CLEAR |
700 GMC_AUX_CLIP_CLEAR |
701 GMC_WRITE_MASK_SET);
702
703 wait_for_fifo(8, info);
704 /* clear the line drawing registers */
705 aty_st_le32(DST_BRES_ERR, 0);
706 aty_st_le32(DST_BRES_INC, 0);
707 aty_st_le32(DST_BRES_DEC, 0);
708
709 /* set brush color registers */
710 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
711 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
712
713 /* set source color registers */
714 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
715 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
716
717 /* default write mask */
718 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
719
720 /* Wait for all the writes to be completed before returning */
721 wait_for_idle(info);
722 }
723
724
725 /* convert bpp values to their register representation */
726 static u32
727 bpp_to_depth(u32 bpp)
728 {
729 if (bpp <= 8)
730 return DST_8BPP;
731 else if (bpp <= 16)
732 return DST_15BPP;
733 else if (bpp <= 24)
734 return DST_24BPP;
735 else if (bpp <= 32)
736 return DST_32BPP;
737
738 return -EINVAL;
739 }
740
741
742 /*
743 * CRTC programming
744 */
745
746 /* Program the CRTC registers */
747 static void
748 aty128_set_crtc(const struct aty128_crtc *crtc,
749 const struct fb_info_aty128 *info)
750 {
751 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
752 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
753 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
754 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
755 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
756 aty_st_le32(CRTC_PITCH, crtc->pitch);
757 aty_st_le32(CRTC_OFFSET, crtc->offset);
758 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
759 /* Disable ATOMIC updating. Is this the right place?
760 * -- BenH: Breaks on my G4
761 */
762 #if 0
763 aty_st_le32(PPLL_CNTL, aty_ld_le32(PPLL_CNTL) & ~(0x00030000));
764 #endif
765 }
766
767
768 static int
769 aty128_var_to_crtc(const struct fb_var_screeninfo *var,
770 struct aty128_crtc *crtc,
771 const struct fb_info_aty128 *info)
772 {
773 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
774 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
775 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
776 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
777 u32 depth, bytpp;
778 u8 hsync_strt_pix[5] = { 0, 0x12, 9, 6, 5 };
779 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
780
781 /* input */
782 xres = var->xres;
783 yres = var->yres;
784 vxres = var->xres_virtual;
785 vyres = var->yres_virtual;
786 xoffset = var->xoffset;
787 yoffset = var->yoffset;
788 bpp = var->bits_per_pixel;
789 left = var->left_margin;
790 right = var->right_margin;
791 upper = var->upper_margin;
792 lower = var->lower_margin;
793 hslen = var->hsync_len;
794 vslen = var->vsync_len;
795 sync = var->sync;
796 vmode = var->vmode;
797
798 /* check for mode eligibility
799 * accept only non interlaced modes */
800 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
801 return -EINVAL;
802
803 /* convert (and round up) and validate */
804 xres = (xres + 7) & ~7;
805 xoffset = (xoffset + 7) & ~7;
806
807 if (vxres < xres + xoffset)
808 vxres = xres + xoffset;
809
810 if (vyres < yres + yoffset)
811 vyres = yres + yoffset;
812
813 /* convert bpp into ATI register depth */
814 depth = bpp_to_depth(bpp);
815
816 /* make sure we didn't get an invalid depth */
817 if (depth == -EINVAL) {
818 printk(KERN_ERR "aty128fb: Invalid depth\n");
819 return -EINVAL;
820 }
821
822 /* convert depth to bpp */
823 bytpp = mode_bytpp[depth];
824
825 /* make sure there is enough video ram for the mode */
826 if ((u32)(vxres * vyres * bytpp) > info->vram_size) {
827 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
828 return -EINVAL;
829 }
830
831 h_disp = (xres >> 3) - 1;
832 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
833
834 v_disp = yres - 1;
835 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
836
837 /* check to make sure h_total and v_total are in range */
838 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
839 printk(KERN_ERR "aty128fb: invalid width ranges\n");
840 return -EINVAL;
841 }
842
843 h_sync_wid = (hslen + 7) >> 3;
844 if (h_sync_wid == 0)
845 h_sync_wid = 1;
846 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
847 h_sync_wid = 0x3f;
848
849 h_sync_strt = h_disp + (right >> 3);
850
851 v_sync_wid = vslen;
852 if (v_sync_wid == 0)
853 v_sync_wid = 1;
854 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
855 v_sync_wid = 0x1f;
856
857 v_sync_strt = v_disp + lower;
858
859 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
860 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
861
862 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
863
864 crtc->gen_cntl = 0x3000000L | c_sync | (depth << 8);
865
866 crtc->h_total = h_total | (h_disp << 16);
867 crtc->v_total = v_total | (v_disp << 16);
868
869 crtc->h_sync_strt_wid = hsync_strt_pix[bytpp] | (h_sync_strt << 3) |
870 (h_sync_wid << 16) | (h_sync_pol << 23);
871 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
872 (v_sync_pol << 23);
873
874 crtc->pitch = vxres >> 3;
875
876 crtc->offset = 0;
877 crtc->offset_cntl = 0;
878
879 crtc->vxres = vxres;
880 crtc->vyres = vyres;
881 crtc->xoffset = xoffset;
882 crtc->yoffset = yoffset;
883 crtc->bpp = bpp;
884
885 return 0;
886 }
887
888
889 static int
890 aty128_bpp_to_var(int pix_width, struct fb_var_screeninfo *var)
891 {
892
893 /* fill in pixel info */
894 switch (pix_width) {
895 case CRTC_PIX_WIDTH_8BPP:
896 var->bits_per_pixel = 8;
897 var->red.offset = 0;
898 var->red.length = 8;
899 var->green.offset = 0;
900 var->green.length = 8;
901 var->blue.offset = 0;
902 var->blue.length = 8;
903 var->transp.offset = 0;
904 var->transp.length = 0;
905 break;
906 case CRTC_PIX_WIDTH_15BPP:
907 case CRTC_PIX_WIDTH_16BPP:
908 var->bits_per_pixel = 16;
909 var->red.offset = 10;
910 var->red.length = 5;
911 var->green.offset = 5;
912 var->green.length = 5;
913 var->blue.offset = 0;
914 var->blue.length = 5;
915 var->transp.offset = 0;
916 var->transp.length = 0;
917 break;
918 case CRTC_PIX_WIDTH_24BPP:
919 var->bits_per_pixel = 24;
920 var->red.offset = 16;
921 var->red.length = 8;
922 var->green.offset = 8;
923 var->green.length = 8;
924 var->blue.offset = 0;
925 var->blue.length = 8;
926 var->transp.offset = 0;
927 var->transp.length = 0;
928 break;
929 case CRTC_PIX_WIDTH_32BPP:
930 var->bits_per_pixel = 32;
931 var->red.offset = 16;
932 var->red.length = 8;
933 var->green.offset = 8;
934 var->green.length = 8;
935 var->blue.offset = 0;
936 var->blue.length = 8;
937 var->transp.offset = 24;
938 var->transp.length = 8;
939 break;
940 default:
941 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
942 return -EINVAL;
943 }
944
945 return 0;
946 }
947
948
949 static int
950 aty128_crtc_to_var(const struct aty128_crtc *crtc,
951 struct fb_var_screeninfo *var)
952 {
953 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
954 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
955 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
956 u32 pix_width;
957
958 /* fun with masking */
959 h_total = crtc->h_total & 0x1ff;
960 h_disp = (crtc->h_total >> 16) & 0xff;
961 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
962 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
963 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
964 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
965 v_total = crtc->v_total & 0x7ff;
966 v_disp = (crtc->v_total >> 16) & 0x7ff;
967 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
968 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
969 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
970 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
971 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
972
973 /* do conversions */
974 xres = (h_disp + 1) << 3;
975 yres = v_disp + 1;
976 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
977 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
978 hslen = h_sync_wid << 3;
979 upper = v_total - v_sync_strt - v_sync_wid;
980 lower = v_sync_strt - v_disp;
981 vslen = v_sync_wid;
982 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
983 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
984 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
985
986 aty128_bpp_to_var(pix_width, var);
987
988 var->xres = xres;
989 var->yres = yres;
990 var->xres_virtual = crtc->vxres;
991 var->yres_virtual = crtc->vyres;
992 var->xoffset = crtc->xoffset;
993 var->yoffset = crtc->yoffset;
994 var->left_margin = left;
995 var->right_margin = right;
996 var->upper_margin = upper;
997 var->lower_margin = lower;
998 var->hsync_len = hslen;
999 var->vsync_len = vslen;
1000 var->sync = sync;
1001 var->vmode = FB_VMODE_NONINTERLACED;
1002
1003 return 0;
1004 }
1005
1006 static void
1007 aty128_set_pll(struct aty128_pll *pll, const struct fb_info_aty128 *info)
1008 {
1009 u32 div3;
1010
1011 unsigned char post_conv[] = /* register values for post dividers */
1012 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1013
1014 /* select PPLL_DIV_3 */
1015 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1016
1017 /* reset PLL */
1018 aty_st_pll(PPLL_CNTL,
1019 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1020
1021 /* write the reference divider */
1022 aty_pll_wait_readupdate(info);
1023 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider & 0x3ff);
1024 aty_pll_writeupdate(info);
1025
1026 div3 = aty_ld_pll(PPLL_DIV_3);
1027 div3 &= ~PPLL_FB3_DIV_MASK;
1028 div3 |= pll->feedback_divider;
1029 div3 &= ~PPLL_POST3_DIV_MASK;
1030 div3 |= post_conv[pll->post_divider] << 16;
1031
1032 /* write feedback and post dividers */
1033 aty_pll_wait_readupdate(info);
1034 aty_st_pll(PPLL_DIV_3, div3);
1035 aty_pll_writeupdate(info);
1036
1037 aty_pll_wait_readupdate(info);
1038 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1039 aty_pll_writeupdate(info);
1040
1041 /* clear the reset, just in case */
1042 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1043 }
1044
1045
1046 static int
1047 aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1048 const struct fb_info_aty128 *info)
1049 {
1050 const struct aty128_constants c = info->constants;
1051 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1052 u32 output_freq;
1053 u32 vclk; /* in .01 MHz */
1054 int i;
1055 u32 n, d;
1056
1057 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1058
1059 /* adjust pixel clock if necessary */
1060 if (vclk > c.ppll_max)
1061 vclk = c.ppll_max;
1062 if (vclk * 12 < c.ppll_min)
1063 vclk = c.ppll_min/12;
1064
1065 /* now, find an acceptable divider */
1066 for (i = 0; i < sizeof(post_dividers); i++) {
1067 output_freq = post_dividers[i] * vclk;
1068 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max)
1069 break;
1070 }
1071
1072 /* calculate feedback divider */
1073 n = c.ref_divider * output_freq;
1074 d = c.dotclock;
1075
1076 pll->post_divider = post_dividers[i];
1077 pll->feedback_divider = round_div(n, d);
1078 pll->vclk = vclk;
1079
1080 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1081 "vclk_per: %d\n", pll->post_divider,
1082 pll->feedback_divider, vclk, output_freq,
1083 c.ref_divider, period_in_ps);
1084
1085 return 0;
1086 }
1087
1088
1089 static int
1090 aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var,
1091 const struct fb_info_aty128 *info)
1092 {
1093 var->pixclock = 100000000 / pll->vclk;
1094
1095 return 0;
1096 }
1097
1098
1099 static void
1100 aty128_set_fifo(const struct aty128_ddafifo *dsp,
1101 const struct fb_info_aty128 *info)
1102 {
1103 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1104 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1105 }
1106
1107
1108 static int
1109 aty128_ddafifo(struct aty128_ddafifo *dsp,
1110 const struct aty128_pll *pll,
1111 u32 bpp,
1112 const struct fb_info_aty128 *info)
1113 {
1114 const struct aty128_meminfo *m = info->mem;
1115 u32 xclk = info->constants.xclk;
1116 u32 fifo_width = info->constants.fifo_width;
1117 u32 fifo_depth = info->constants.fifo_depth;
1118 s32 x, b, p, ron, roff;
1119 u32 n, d;
1120
1121 /* 15bpp is really 16bpp */
1122 if (bpp == 15)
1123 bpp = 16;
1124
1125 n = xclk * fifo_width;
1126 d = pll->vclk * bpp;
1127 x = round_div(n, d);
1128
1129 ron = 4 * m->MB +
1130 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1131 2 * m->Trp +
1132 m->Twr +
1133 m->CL +
1134 m->Tr2w +
1135 x;
1136
1137 DBG("x %x\n", x);
1138
1139 b = 0;
1140 while (x) {
1141 x >>= 1;
1142 b++;
1143 }
1144 p = b + 1;
1145
1146 ron <<= (11 - p);
1147
1148 n <<= (11 - p);
1149 x = round_div(n, d);
1150 roff = x * (fifo_depth - 4);
1151
1152 if ((ron + m->Rloop) >= roff) {
1153 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1154 return -EINVAL;
1155 }
1156
1157 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1158 p, m->Rloop, x, ron, roff);
1159
1160 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1161 dsp->dda_on_off = ron << 16 | roff;
1162
1163 return 0;
1164 }
1165
1166
1167 /*
1168 * This actually sets the video mode.
1169 */
1170 static void
1171 aty128_set_par(struct aty128fb_par *par,
1172 struct fb_info_aty128 *info)
1173 {
1174 u32 config;
1175
1176 info->current_par = *par;
1177
1178 if (info->blitter_may_be_busy)
1179 wait_for_idle(info);
1180
1181 /* clear all registers that may interfere with mode setting */
1182 aty_st_le32(OVR_CLR, 0);
1183 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1184 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1185 aty_st_le32(OV0_SCALE_CNTL, 0);
1186 aty_st_le32(MPP_TB_CONFIG, 0);
1187 aty_st_le32(MPP_GP_CONFIG, 0);
1188 aty_st_le32(SUBPIC_CNTL, 0);
1189 aty_st_le32(VIPH_CONTROL, 0);
1190 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1191 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1192 aty_st_le32(CAP0_TRIG_CNTL, 0);
1193 aty_st_le32(CAP1_TRIG_CNTL, 0);
1194
1195 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1196
1197 aty128_set_crtc(&par->crtc, info);
1198 aty128_set_pll(&par->pll, info);
1199 aty128_set_fifo(&par->fifo_reg, info);
1200
1201 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1202
1203 #if defined(__BIG_ENDIAN)
1204 if (par->crtc.bpp >= 24)
1205 config |= 2; /* make aperture do 32 byte swapping */
1206 else if (par->crtc.bpp > 8)
1207 config |= 1; /* make aperture do 16 byte swapping */
1208 #endif
1209
1210 aty_st_le32(CONFIG_CNTL, config);
1211 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1212
1213 if (par->accel_flags & FB_ACCELF_TEXT)
1214 aty128_init_engine(par, info);
1215
1216 #ifdef CONFIG_FB_COMPAT_XPMAC
1217 if (!console_fb_info || console_fb_info == &info->fb_info) {
1218 struct fb_var_screeninfo var;
1219 int cmode, vmode;
1220
1221 display_info.height = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1222 display_info.width = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1223 display_info.depth = par->crtc.bpp;
1224 display_info.pitch = (par->crtc.vxres * par->crtc.bpp) >> 3;
1225 aty128_encode_var(&var, par, info);
1226 if (mac_var_to_vmode(&var, &vmode, &cmode))
1227 display_info.mode = 0;
1228 else
1229 display_info.mode = vmode;
1230 strcpy(display_info.name, aty128fb_name);
1231 display_info.fb_address = info->frame_buffer_phys;
1232 display_info.cmap_adr_address = 0;
1233 display_info.cmap_data_address = 0;
1234 display_info.disp_reg_address = info->regbase_phys;
1235 }
1236 #endif /* CONFIG_FB_COMPAT_XPMAC */
1237 }
1238
1239 /*
1240 * encode/decode the User Defined Part of the Display
1241 */
1242
1243 static int
1244 aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par,
1245 const struct fb_info_aty128 *info)
1246 {
1247 int err;
1248
1249 if ((err = aty128_var_to_crtc(var, &par->crtc, info)))
1250 return err;
1251
1252 if ((err = aty128_var_to_pll(var->pixclock, &par->pll, info)))
1253 return err;
1254
1255 if ((err = aty128_ddafifo(&par->fifo_reg, &par->pll, par->crtc.bpp, info)))
1256 return err;
1257
1258 if (var->accel_flags & FB_ACCELF_TEXT)
1259 par->accel_flags = FB_ACCELF_TEXT;
1260 else
1261 par->accel_flags = 0;
1262
1263 return 0;
1264 }
1265
1266
1267 static int
1268 aty128_encode_var(struct fb_var_screeninfo *var,
1269 const struct aty128fb_par *par,
1270 const struct fb_info_aty128 *info)
1271 {
1272 int err;
1273
1274 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1275 return err;
1276
1277 if ((err = aty128_pll_to_var(&par->pll, var, info)))
1278 return err;
1279
1280 var->red.msb_right = 0;
1281 var->green.msb_right = 0;
1282 var->blue.msb_right = 0;
1283 var->transp.msb_right = 0;
1284
1285 var->nonstd = 0;
1286 var->activate = 0;
1287
1288 var->height = -1;
1289 var->width = -1;
1290 var->accel_flags = par->accel_flags;
1291
1292 return 0;
1293 }
1294
1295
1296 /*
1297 * Get the User Defined Part of the Display
1298 */
1299
1300 static int
1301 aty128fb_get_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb)
1302 {
1303 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1304
1305 if (con == -1)
1306 aty128_encode_var(var, &info->default_par, info);
1307 else
1308 *var = fb_display[con].var;
1309 return 0;
1310 }
1311
1312
1313 /*
1314 * Set the User Defined Part of the Display
1315 */
1316
1317 static int
1318 aty128fb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb)
1319 {
1320 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1321 struct aty128fb_par par;
1322 struct display *display;
1323 int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel;
1324 int accel, err;
1325
1326 display = (con >= 0) ? &fb_display[con] : fb->disp;
1327
1328 /* basic (in)sanity checks */
1329 if (!var->xres)
1330 var->xres = 1;
1331 if (!var->yres)
1332 var->yres = 1;
1333 if (var->xres > var->xres_virtual)
1334 var->xres_virtual = var->xres;
1335 if (var->yres > var->yres_virtual)
1336 var->yres_virtual = var->yres;
1337
1338 switch (var->bits_per_pixel) {
1339 case 0 ... 8:
1340 var->bits_per_pixel = 8;
1341 break;
1342 case 9 ... 16:
1343 var->bits_per_pixel = 16;
1344 break;
1345 case 17 ... 24:
1346 var->bits_per_pixel = 24;
1347 break;
1348 case 25 ... 32:
1349 var->bits_per_pixel = 32;
1350 break;
1351 default:
1352 return -EINVAL;
1353 }
1354
1355 if ((err = aty128_decode_var(var, &par, info)))
1356 return err;
1357
1358 aty128_encode_var(var, &par, info);
1359
1360 if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_NOW)
1361 return 0;
1362
1363 oldxres = display->var.xres;
1364 oldyres = display->var.yres;
1365 oldvxres = display->var.xres_virtual;
1366 oldvyres = display->var.yres_virtual;
1367 oldbpp = display->var.bits_per_pixel;
1368 oldaccel = display->var.accel_flags;
1369 display->var = *var;
1370 if (oldxres != var->xres || oldyres != var->yres ||
1371 oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
1372 oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {
1373
1374 struct fb_fix_screeninfo fix;
1375
1376 aty128_encode_fix(&fix, &par, info);
1377 display->screen_base = (char *)info->frame_buffer;
1378 display->visual = fix.visual;
1379 display->type = fix.type;
1380 display->type_aux = fix.type_aux;
1381 display->ypanstep = fix.ypanstep;
1382 display->ywrapstep = fix.ywrapstep;
1383 display->line_length = fix.line_length;
1384 display->can_soft_blank = 1;
1385 display->inverse = 0;
1386
1387 accel = var->accel_flags & FB_ACCELF_TEXT;
1388 aty128_set_disp(display, info, par.crtc.bpp, accel);
1389
1390 if (accel)
1391 display->scrollmode = SCROLL_YNOMOVE;
1392 else
1393 display->scrollmode = SCROLL_YREDRAW;
1394
1395 if (info->fb_info.changevar)
1396 (*info->fb_info.changevar)(con);
1397 }
1398
1399 if (!info->fb_info.display_fg || info->fb_info.display_fg->vc_num == con)
1400 aty128_set_par(&par, info);
1401
1402 if (oldbpp != var->bits_per_pixel) {
1403 if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
1404 return err;
1405 do_install_cmap(con, &info->fb_info);
1406 }
1407
1408 return 0;
1409 }
1410
1411
1412 static void
1413 aty128_set_disp(struct display *disp,
1414 struct fb_info_aty128 *info, int bpp, int accel)
1415 {
1416 switch (bpp) {
1417 #ifdef FBCON_HAS_CFB8
1418 case 8:
1419 info->dispsw = accel ? fbcon_aty128_8 : fbcon_cfb8;
1420 disp->dispsw = &info->dispsw;
1421 break;
1422 #endif
1423 #ifdef FBCON_HAS_CFB16
1424 case 15:
1425 case 16:
1426 info->dispsw = accel ? fbcon_aty128_16 : fbcon_cfb16;
1427 disp->dispsw = &info->dispsw;
1428 disp->dispsw_data = info->fbcon_cmap.cfb16;
1429 break;
1430 #endif
1431 #ifdef FBCON_HAS_CFB24
1432 case 24:
1433 info->dispsw = accel ? fbcon_aty128_24 : fbcon_cfb24;
1434 disp->dispsw = &info->dispsw;
1435 disp->dispsw_data = info->fbcon_cmap.cfb24;
1436 break;
1437 #endif
1438 #ifdef FBCON_HAS_CFB32
1439 case 32:
1440 info->dispsw = accel ? fbcon_aty128_32 : fbcon_cfb32;
1441 disp->dispsw = &info->dispsw;
1442 disp->dispsw_data = info->fbcon_cmap.cfb32;
1443 break;
1444 #endif
1445 default:
1446 disp->dispsw = &fbcon_dummy;
1447 }
1448 }
1449
1450
1451 static void
1452 aty128_encode_fix(struct fb_fix_screeninfo *fix,
1453 struct aty128fb_par *par,
1454 const struct fb_info_aty128 *info)
1455 {
1456 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1457
1458 strcpy(fix->id, aty128fb_name);
1459
1460 fix->smem_start = (unsigned long)info->frame_buffer_phys;
1461 fix->mmio_start = (unsigned long)info->regbase_phys;
1462
1463 fix->smem_len = info->vram_size;
1464 fix->mmio_len = 0x1fff;
1465
1466 fix->type = FB_TYPE_PACKED_PIXELS;
1467 fix->type_aux = 0;
1468 fix->line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1469 fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR
1470 : FB_VISUAL_DIRECTCOLOR;
1471 fix->ywrapstep = 0;
1472 fix->xpanstep = 8;
1473 fix->ypanstep = 1;
1474
1475 fix->accel = FB_ACCEL_ATI_RAGE128;
1476
1477 return;
1478 }
1479
1480
1481 /*
1482 * Get the Fixed Part of the Display
1483 */
1484 static int
1485 aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *fb)
1486 {
1487 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1488 struct aty128fb_par par;
1489
1490 if (con == -1)
1491 par = info->default_par;
1492 else
1493 aty128_decode_var(&fb_display[con].var, &par, info);
1494
1495 aty128_encode_fix(fix, &par, info);
1496
1497 return 0;
1498 }
1499
1500
1501 /*
1502 * Pan or Wrap the Display
1503 *
1504 * Not supported (yet!)
1505 */
1506 static int
1507 aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
1508 struct fb_info *fb)
1509 {
1510 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1511 struct aty128fb_par *par = &info->current_par;
1512 u32 xoffset, yoffset;
1513 u32 offset;
1514 u32 xres, yres;
1515
1516 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1517 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1518
1519 xoffset = (var->xoffset +7) & ~7;
1520 yoffset = var->yoffset;
1521
1522 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1523 return -EINVAL;
1524
1525 par->crtc.xoffset = xoffset;
1526 par->crtc.yoffset = yoffset;
1527
1528 offset = ((yoffset * par->crtc.vxres + xoffset) * par->crtc.bpp) >> 6;
1529
1530 aty_st_le32(CRTC_OFFSET, offset);
1531
1532 return 0;
1533 }
1534
1535
1536 /*
1537 * Get the Colormap
1538 */
1539
1540 static int
1541 aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
1542 struct fb_info *info)
1543 {
1544 #if 1
1545 fb_copy_cmap(&info->cmap, cmap, kspc ? 0 : 2);
1546 #else
1547 struct fb_info_aty128 fb = (struct fb_info_aty128 *)info;
1548
1549 if (con == fb->currcon) /* current console? */
1550 return fb_get_cmap(cmap, kspc, aty128_getcolreg, info);
1551 else if (fb_display[con].cmap.len) /* non default colormap? */
1552 fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
1553 else {
1554 int size = (fb_display[con].var.bits_per_pixel <= 8) ? 256 : 32;
1555 fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
1556 }
1557 #endif
1558
1559 return 0;
1560 }
1561
1562 /*
1563 * Set the Colormap
1564 */
1565
1566 static int
1567 aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
1568 struct fb_info *info)
1569 {
1570 int err;
1571 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1572 struct display *disp;
1573
1574 if (con >= 0)
1575 disp = &fb_display[con];
1576 else
1577 disp = info->disp;
1578
1579 if (!disp->cmap.len) { /* no colormap allocated? */
1580 int size = (disp->var.bits_per_pixel <= 8) ? 256 : 32;
1581 if ((err = fb_alloc_cmap(&disp->cmap, size, 0)))
1582 return err;
1583 }
1584
1585 if (con == fb->currcon) /* current console? */
1586 return fb_set_cmap(cmap, kspc, aty128_setcolreg, info);
1587 else
1588 fb_copy_cmap(cmap, &disp->cmap, kspc ? 0 : 1);
1589
1590 return 0;
1591 }
1592
1593 /*
1594 * Frame Buffer Specific ioctls
1595 */
1596
1597 static int
1598 aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1599 u_long arg, int con, struct fb_info *info)
1600 {
1601 return -EINVAL;
1602 }
1603
1604
1605 static int
1606 aty128fb_rasterimg(struct fb_info *info, int start)
1607 {
1608 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1609
1610 if (fb->blitter_may_be_busy)
1611 wait_for_idle(fb);
1612
1613 return 0;
1614 }
1615
1616
1617 #ifndef MODULE
1618 int __init
1619 aty128fb_setup(char *options)
1620 {
1621 char *this_opt;
1622
1623 if (!options || !*options)
1624 return 0;
1625
1626 for (this_opt = strtok(options, ","); this_opt;
1627 this_opt = strtok(NULL, ",")) {
1628 if (!strncmp(this_opt, "font:", 5)) {
1629 char *p;
1630 int i;
1631
1632 p = this_opt +5;
1633 for (i = 0; i < sizeof(fontname) - 1; i++)
1634 if (!*p || *p == ' ' || *p == ',')
1635 break;
1636 memcpy(fontname, this_opt + 5, i);
1637 fontname[i] = 0;
1638 } else if (!strncmp(this_opt, "noaccel", 7)) {
1639 noaccel = 1;
1640 }
1641 #ifdef CONFIG_MTRR
1642 else if(!strncmp(this_opt, "nomtrr", 6)) {
1643 mtrr = 0;
1644 }
1645 #endif
1646 #ifdef CONFIG_PPC
1647 /* vmode and cmode depreciated */
1648 else if (!strncmp(this_opt, "vmode:", 6)) {
1649 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1650 if (vmode > 0 && vmode <= VMODE_MAX)
1651 default_vmode = vmode;
1652 } else if (!strncmp(this_opt, "cmode:", 6)) {
1653 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1654 switch (cmode) {
1655 case 0:
1656 case 8:
1657 default_cmode = CMODE_8;
1658 break;
1659 case 15:
1660 case 16:
1661 default_cmode = CMODE_16;
1662 break;
1663 case 24:
1664 case 32:
1665 default_cmode = CMODE_32;
1666 break;
1667 }
1668 }
1669 #endif /* CONFIG_PPC */
1670 else
1671 mode_option = this_opt;
1672 }
1673 return 0;
1674 }
1675 #endif /* !MODULE */
1676
1677
1678 /*
1679 * Initialisation
1680 */
1681
1682 static int __init
1683 aty128_init(struct fb_info_aty128 *info, const char *name)
1684 {
1685 struct fb_var_screeninfo var;
1686 u32 dac;
1687 int j, k;
1688 u8 chip_rev;
1689 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
1690 char *video_card = "Rage128";
1691
1692 if (!info->vram_size) /* may have already been probed */
1693 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1694
1695 /* Get the chip revision */
1696 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1697
1698 /* put a name with the face */
1699 while (aci->name && info->pdev->device != aci->device) { aci++; }
1700 video_card = (char *)aci->name;
1701 info->chip_gen = aci->chip_gen;
1702
1703 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1704
1705 if (info->vram_size % (1024 * 1024) == 0)
1706 printk("%dM %s\n", info->vram_size / (1024*1024), info->mem->name);
1707 else
1708 printk("%dk %s\n", info->vram_size / 1024, info->mem->name);
1709
1710 /* fill in info */
1711 strcpy(info->fb_info.modename, aty128fb_name);
1712 info->fb_info.node = -1;
1713 info->fb_info.fbops = &aty128fb_ops;
1714 info->fb_info.disp = &info->disp;
1715 strcpy(info->fb_info.fontname, fontname);
1716 info->fb_info.changevar = NULL;
1717 info->fb_info.switch_con = &aty128fbcon_switch;
1718 info->fb_info.updatevar = NULL;
1719 info->fb_info.blank = &aty128fbcon_blank;
1720 info->fb_info.flags = FBINFO_FLAG_DEFAULT;
1721
1722 #ifdef MODULE
1723 var = default_var;
1724 #else
1725 memset(&var, 0, sizeof(var));
1726 #ifdef CONFIG_PPC
1727 if (_machine == _MACH_Pmac) {
1728 if (mode_option) {
1729 if (!mac_find_mode(&var, &info->fb_info, mode_option, 8))
1730 var = default_var;
1731 } else {
1732 #ifdef CONFIG_NVRAM
1733 if (default_vmode == VMODE_NVRAM)
1734 default_vmode = nvram_read_byte(NV_VMODE);
1735
1736 if (default_cmode == CMODE_NVRAM)
1737 default_cmode = nvram_read_byte(NV_CMODE);
1738 #endif
1739 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1740 default_vmode = VMODE_640_480_60;
1741
1742 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
1743 default_cmode = CMODE_8;
1744
1745 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1746 var = default_var;
1747 }
1748 } else
1749 #endif /* CONFIG_PPC */
1750 {
1751 if (fb_find_mode(&var, &info->fb_info, mode_option, NULL, 0,
1752 &defaultmode, 8) == 0)
1753 var = default_var;
1754 }
1755 #endif /* MODULE */
1756
1757 if (noaccel)
1758 var.accel_flags &= ~FB_ACCELF_TEXT;
1759 else
1760 var.accel_flags |= FB_ACCELF_TEXT;
1761
1762 if (aty128_decode_var(&var, &info->default_par, info)) {
1763 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1764 return 0;
1765 }
1766
1767 /* load up the palette with default colors */
1768 for (j = 0; j < 16; j++) {
1769 k = color_table[j];
1770 info->palette[j].red = default_red[k];
1771 info->palette[j].green = default_grn[k];
1772 info->palette[j].blue = default_blu[k];
1773 }
1774
1775 /* setup the DAC the way we like it */
1776 dac = aty_ld_le32(DAC_CNTL);
1777 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1778 dac |= DAC_MASK;
1779 aty_st_le32(DAC_CNTL, dac);
1780
1781 /* turn off bus mastering, just in case */
1782 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1783
1784 aty128fb_set_var(&var, -1, &info->fb_info);
1785 aty128_init_engine(&info->default_par, info);
1786
1787 board_list = aty128_board_list_add(board_list, info);
1788
1789 if (register_framebuffer(&info->fb_info) < 0)
1790 return 0;
1791
1792 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
1793 GET_FB_IDX(info->fb_info.node), aty128fb_name, name);
1794
1795 return 1; /* success! */
1796 }
1797
1798
1799 /* add a new card to the list ++ajoshi */
1800 static struct
1801 fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128 *board_list,
1802 struct fb_info_aty128 *new_node)
1803 {
1804 struct fb_info_aty128 *i_p = board_list;
1805
1806 new_node->next = NULL;
1807 if(board_list == NULL)
1808 return new_node;
1809 while(i_p->next != NULL)
1810 i_p = i_p->next;
1811 i_p->next = new_node;
1812
1813 return board_list;
1814 }
1815
1816
1817 int __init
1818 aty128fb_init(void)
1819 {
1820 #ifdef CONFIG_PCI
1821 struct pci_dev *pdev = NULL;
1822 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
1823
1824 while (aci->name != NULL) {
1825 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev);
1826 while (pdev != NULL) {
1827 if (aty128_pci_register(pdev, aci) == 0)
1828 return 0;
1829 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev);
1830 }
1831 aci++;
1832 }
1833 #endif
1834
1835 return 0;
1836 }
1837
1838
1839 #ifdef CONFIG_PCI
1840 /* register a card ++ajoshi */
1841 static int __init
1842 aty128_pci_register(struct pci_dev *pdev,
1843 const struct aty128_chip_info *aci)
1844 {
1845 struct fb_info_aty128 *info = NULL;
1846 u32 fb_addr, reg_addr, io_addr = 0;
1847 int err;
1848
1849 fb_addr = pci_resource_start(pdev, 0);
1850 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
1851 "aty128fb FB")) {
1852 printk(KERN_ERR "aty128fb: cannot reserve frame buffer memory\n");
1853 goto err_free_fb;
1854 }
1855
1856 reg_addr = pci_resource_start(pdev, 2);
1857 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
1858 "aty128fb MMIO")) {
1859 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
1860 goto err_free_mmio;
1861 }
1862
1863 /* We have the resources. Now virtualize them */
1864 info = kmalloc(sizeof(struct fb_info_aty128), GFP_ATOMIC);
1865 if(!info) {
1866 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
1867 goto err_unmap_out;
1868 }
1869 memset(info, 0, sizeof(struct fb_info_aty128));
1870
1871 /* Copy PCI device info into info->pdev */
1872 info->pdev = pdev;
1873
1874 info->currcon = -1;
1875
1876 /* Virtualize mmio region */
1877 info->regbase_phys = reg_addr;
1878 info->regbase = ioremap(reg_addr, 0x1FFF);
1879
1880 if (!info->regbase)
1881 goto err_free_info;
1882
1883 /* Store io_base */
1884 info->io_base = io_addr;
1885
1886 /* Grab memory size from the card */
1887 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1888
1889 /* Virtualize the framebuffer */
1890 info->frame_buffer_phys = fb_addr;
1891 info->frame_buffer = (u32)ioremap(fb_addr, info->vram_size);
1892
1893 if (!info->frame_buffer) {
1894 iounmap((void *)info->regbase);
1895 goto err_free_info;
1896 }
1897
1898 /* Enable device in PCI config */
1899 err = pci_enable_device(pdev);
1900 if (err) {
1901 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n", err);
1902 goto err_out;
1903 }
1904
1905 /* If we can't test scratch registers, something is seriously wrong */
1906 if (!register_test(info)) {
1907 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
1908 goto err_out;
1909 }
1910
1911 #if !defined(CONFIG_PPC) && !defined(__sparc__)
1912 if (!aty128find_ROM(info))
1913 printk(KERN_INFO "aty128fb: Rage128 BIOS not located. Guessing...\n");
1914 else
1915 aty128_get_pllinfo(info);
1916 #endif
1917 aty128_timings(info);
1918
1919 if (!aty128_init(info, "PCI"))
1920 goto err_out;
1921
1922 #ifdef CONFIG_MTRR
1923 if (mtrr) {
1924 info->mtrr.vram = mtrr_add(info->frame_buffer_phys, info->vram_size,
1925 MTRR_TYPE_WRCOMB, 1);
1926 info->mtrr.vram_valid = 1;
1927 /* let there be speed */
1928 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
1929 }
1930 #endif /* CONFIG_MTRR */
1931
1932 return 0;
1933
1934 err_out:
1935 iounmap((void *)info->frame_buffer);
1936 iounmap((void *)info->regbase);
1937 err_free_info:
1938 kfree(info);
1939 err_unmap_out:
1940 release_mem_region(pci_resource_start(pdev, 2),
1941 pci_resource_len(pdev, 2));
1942 err_free_mmio:
1943 release_mem_region(pci_resource_start(pdev, 0),
1944 pci_resource_len(pdev, 0));
1945 err_free_fb:
1946 release_mem_region(pci_resource_start(pdev, 1),
1947 pci_resource_len(pdev, 1));
1948 return -ENODEV;
1949 }
1950 #endif /* CONFIG_PCI */
1951
1952
1953 /* PPC and Sparc cannot read video ROM */
1954 #if !defined(CONFIG_PPC) && !defined(__sparc__)
1955 static int __init
1956 aty128find_ROM(struct fb_info_aty128 *info)
1957 {
1958 int flag = 0;
1959 u32 segstart;
1960 char *rom_base;
1961 char *rom;
1962 int stage;
1963 int i;
1964 char aty_rom_sig[] = "761295520"; /* ATI ROM Signature */
1965 char R128_sig[] = "R128"; /* Rage128 ROM identifier */
1966
1967 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
1968 stage = 1;
1969
1970 rom_base = (char *) ioremap(segstart, 0x1000);
1971
1972 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
1973 stage = 2;
1974
1975 if (stage != 2) {
1976 iounmap(rom_base);
1977 continue;
1978 }
1979 rom = rom_base;
1980
1981 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
1982 if (aty_rom_sig[0] == *rom) {
1983 if (strncmp(aty_rom_sig, rom, strlen(aty_rom_sig)) == 0) {
1984 stage = 3;
1985 }
1986 }
1987 rom++;
1988 }
1989 if (stage != 3) {
1990 iounmap(rom_base);
1991 continue;
1992 }
1993 rom = rom_base;
1994
1995 /* ATI signature found. Let's see if it's a Rage128 */
1996 for (i = 0; (i < 512) && (stage != 4); i++) {
1997 if (R128_sig[0] == *rom) {
1998 if (strncmp(R128_sig, rom, strlen(R128_sig)) == 0) {
1999 stage = 4;
2000 }
2001 }
2002 rom++;
2003 }
2004 if (stage != 4) {
2005 iounmap(rom_base);
2006 continue;
2007 }
2008
2009 bios_seg = rom_base;
2010 printk(KERN_INFO "aty128fb: Rage128 BIOS located at segment %4.4X\n",
2011 (unsigned int)rom_base);
2012 flag = 1;
2013 break;
2014 }
2015 return (flag);
2016 }
2017
2018
2019 static void __init
2020 aty128_get_pllinfo(struct fb_info_aty128 *info)
2021 {
2022 void *bios_header;
2023 void *header_ptr;
2024 u16 bios_header_offset, pll_info_offset;
2025 PLL_BLOCK pll;
2026
2027 bios_header = bios_seg + 0x48L;
2028 header_ptr = bios_header;
2029
2030 bios_header_offset = readw(header_ptr);
2031 bios_header = bios_seg + bios_header_offset;
2032 bios_header += 0x30;
2033
2034 header_ptr = bios_header;
2035 pll_info_offset = readw(header_ptr);
2036 header_ptr = bios_seg + pll_info_offset;
2037
2038 memcpy_fromio(&pll, header_ptr, 50);
2039
2040 info->constants.ppll_max = pll.PCLK_max_freq;
2041 info->constants.ppll_min = pll.PCLK_min_freq;
2042 info->constants.xclk = (u32)pll.XCLK;
2043 info->constants.ref_divider = (u32)pll.PCLK_ref_divider;
2044 info->constants.dotclock = (u32)pll.PCLK_ref_freq;
2045
2046 /* free up to be un-used resources. bios_seg is mapped by
2047 * aty128find_ROM() and used by aty128_get_pllinfo()
2048 *
2049 * TODO: make more elegant. doesn't need to be global */
2050 if (bios_seg)
2051 iounmap(bios_seg);
2052
2053 DBG("ppll_max %d ppll_min %d xclk %d "
2054 "ref_divider %d dotclock %d\n",
2055 info->constants.ppll_max, info->constants.ppll_min,
2056 info->constants.xclk, info->constants.ref_divider,
2057 info->constants.dotclock);
2058
2059 return;
2060 }
2061 #endif /* !CONFIG_PPC */
2062
2063
2064 /* fill in known card constants if pll_block is not available */
2065 static void __init
2066 aty128_timings(struct fb_info_aty128 *info)
2067 {
2068 #ifdef CONFIG_PPC
2069 /* instead of a table lookup, assume OF has properly
2070 * setup the PLL registers and use their values
2071 * to set the XCLK values and reference divider values */
2072
2073 u32 x_mpll_ref_fb_div;
2074 u32 xclk_cntl;
2075 u32 Nx, M;
2076 unsigned PostDivSet[] =
2077 { 0, 1, 2, 4, 8, 3, 6, 12 };
2078 #endif
2079
2080 if (!info->constants.dotclock)
2081 info->constants.dotclock = 2950;
2082
2083 #ifdef CONFIG_PPC
2084 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
2085 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
2086 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
2087 M = x_mpll_ref_fb_div & 0x0000ff;
2088
2089 info->constants.xclk = round_div((2 * Nx *
2090 info->constants.dotclock), (M * PostDivSet[xclk_cntl]));
2091
2092 info->constants.ref_divider =
2093 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
2094 #endif
2095
2096 if (!info->constants.ref_divider) {
2097 info->constants.ref_divider = 0x3b;
2098
2099 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
2100 aty_pll_writeupdate(info);
2101 }
2102 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider);
2103 aty_pll_writeupdate(info);
2104
2105 /* from documentation */
2106 if (!info->constants.ppll_min)
2107 info->constants.ppll_min = 12500;
2108 if (!info->constants.ppll_max)
2109 info->constants.ppll_max = 25000; /* 23000 on some cards? */
2110 if (!info->constants.xclk)
2111 info->constants.xclk = 0x1d4d; /* same as mclk */
2112
2113 info->constants.fifo_width = 128;
2114 info->constants.fifo_depth = 32;
2115
2116 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
2117 case 0:
2118 info->mem = &sdr_128;
2119 break;
2120 case 1:
2121 info->mem = &sdr_sgram;
2122 break;
2123 case 2:
2124 info->mem = &ddr_sgram;
2125 break;
2126 default:
2127 info->mem = &sdr_sgram;
2128 }
2129 }
2130
2131
2132 static int
2133 aty128fbcon_switch(int con, struct fb_info *fb)
2134 {
2135 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2136 struct aty128fb_par par;
2137
2138 /* Do we have to save the colormap? */
2139 if (fb_display[info->currcon].cmap.len)
2140 fb_get_cmap(&fb_display[info->currcon].cmap, 1,
2141 aty128_getcolreg, fb);
2142
2143 /* set the current console */
2144 info->currcon = con;
2145
2146 aty128_decode_var(&fb_display[con].var, &par, info);
2147 aty128_set_par(&par, info);
2148
2149 aty128_set_disp(&fb_display[con], info, par.crtc.bpp,
2150 par.accel_flags & FB_ACCELF_TEXT);
2151
2152 do_install_cmap(con, fb);
2153
2154 return 1;
2155 }
2156
2157
2158 /*
2159 * Blank the display.
2160 */
2161 static void
2162 aty128fbcon_blank(int blank, struct fb_info *fb)
2163 {
2164 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2165 u8 state = 0;
2166
2167 if (blank & VESA_VSYNC_SUSPEND)
2168 state |= 2;
2169 if (blank & VESA_HSYNC_SUSPEND)
2170 state |= 1;
2171 if (blank & VESA_POWERDOWN)
2172 state |= 4;
2173
2174 aty_st_8(CRTC_EXT_CNTL+1, state);
2175 }
2176
2177
2178 /*
2179 * Read a single color register and split it into
2180 * colors/transparent. Return != 0 for invalid regno.
2181 */
2182 static int
2183 aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
2184 u_int *transp, struct fb_info *fb)
2185 {
2186 struct fb_info_aty128 *info = (struct fb_info_aty128 *) fb;
2187
2188 if (regno > 255)
2189 return 1;
2190
2191 *red = (info->palette[regno].red<<8) | info->palette[regno].red;
2192 *green = (info->palette[regno].green<<8) | info->palette[regno].green;
2193 *blue = (info->palette[regno].blue<<8) | info->palette[regno].blue;
2194 *transp = 0;
2195
2196 return 0;
2197 }
2198
2199 /*
2200 * Set a single color register. The values supplied are already
2201 * rounded down to the hardware's capabilities (according to the
2202 * entries in the var structure). Return != 0 for invalid regno.
2203 */
2204 static int
2205 aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2206 u_int transp, struct fb_info *fb)
2207 {
2208 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2209 u32 col;
2210
2211 if (regno > 255)
2212 return 1;
2213
2214 red >>= 8;
2215 green >>= 8;
2216 blue >>= 8;
2217 info->palette[regno].red = red;
2218 info->palette[regno].green = green;
2219 info->palette[regno].blue = blue;
2220
2221 /* Note: For now, on M3, we set palette on both heads, which may
2222 * be useless. Can someone with a M3 check this ? */
2223
2224 /* initialize gamma ramp for hi-color+ */
2225
2226 if ((info->current_par.crtc.bpp > 8) && (regno == 0)) {
2227 int i;
2228
2229 if (info->chip_gen == rage_M3)
2230 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~PALETTE_ACCESS_CNTL);
2231
2232 for (i=16; i<256; i++) {
2233 aty_st_8(PALETTE_INDEX, i);
2234 col = (i << 16) | (i << 8) | i;
2235 aty_st_le32(PALETTE_DATA, col);
2236 }
2237
2238 if (info->chip_gen == rage_M3) {
2239 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | PALETTE_ACCESS_CNTL);
2240
2241 for (i=16; i<256; i++) {
2242 aty_st_8(PALETTE_INDEX, i);
2243 col = (i << 16) | (i << 8) | i;
2244 aty_st_le32(PALETTE_DATA, col);
2245 }
2246 }
2247 }
2248
2249 /* initialize palette */
2250
2251 if (info->chip_gen == rage_M3)
2252 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~PALETTE_ACCESS_CNTL);
2253
2254 if (info->current_par.crtc.bpp == 16)
2255 aty_st_8(PALETTE_INDEX, (regno << 3));
2256 else
2257 aty_st_8(PALETTE_INDEX, regno);
2258 col = (red << 16) | (green << 8) | blue;
2259 aty_st_le32(PALETTE_DATA, col);
2260 if (info->chip_gen == rage_M3) {
2261 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | PALETTE_ACCESS_CNTL);
2262 if (info->current_par.crtc.bpp == 16)
2263 aty_st_8(PALETTE_INDEX, (regno << 3));
2264 else
2265 aty_st_8(PALETTE_INDEX, regno);
2266 aty_st_le32(PALETTE_DATA, col);
2267 }
2268
2269 if (regno < 16)
2270 switch (info->current_par.crtc.bpp) {
2271 #ifdef FBCON_HAS_CFB16
2272 case 9 ... 16:
2273 info->fbcon_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
2274 regno;
2275 break;
2276 #endif
2277 #ifdef FBCON_HAS_CFB24
2278 case 17 ... 24:
2279 info->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) |
2280 regno;
2281 break;
2282 #endif
2283 #ifdef FBCON_HAS_CFB32
2284 case 25 ... 32: {
2285 u32 i;
2286
2287 i = (regno << 8) | regno;
2288 info->fbcon_cmap.cfb32[regno] = (i << 16) | i;
2289 break;
2290 }
2291 #endif
2292 }
2293 return 0;
2294 }
2295
2296
2297 static void
2298 do_install_cmap(int con, struct fb_info *info)
2299 {
2300 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
2301
2302 if (con != fb->currcon)
2303 return;
2304
2305 if (fb_display[con].cmap.len)
2306 fb_set_cmap(&fb_display[con].cmap, 1, aty128_setcolreg, info);
2307 else {
2308 int size = (fb_display[con].var.bits_per_pixel <= 8) ? 256 : 16;
2309 fb_set_cmap(fb_default_cmap(size), 1, aty128_setcolreg, info);
2310 }
2311 }
2312
2313
2314 /*
2315 * Accelerated functions
2316 */
2317
2318 static inline void
2319 aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2320 u_int width, u_int height,
2321 struct fb_info_aty128 *info)
2322 {
2323 u32 save_dp_datatype, save_dp_cntl, bppval;
2324
2325 if (!width || !height)
2326 return;
2327
2328 bppval = bpp_to_depth(info->current_par.crtc.bpp);
2329 if (bppval == DST_24BPP) {
2330 srcx *= 3;
2331 dstx *= 3;
2332 width *= 3;
2333 } else if (bppval == -EINVAL) {
2334 printk("aty128fb: invalid depth\n");
2335 return;
2336 }
2337
2338 wait_for_fifo(2, info);
2339 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2340 save_dp_cntl = aty_ld_le32(DP_CNTL);
2341
2342 wait_for_fifo(6, info);
2343 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2344 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2345 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2346 aty_st_le32(DP_DATATYPE, save_dp_datatype | bppval | SRC_DSTCOLOR);
2347
2348 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2349 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2350
2351 info->blitter_may_be_busy = 1;
2352
2353 wait_for_fifo(2, info);
2354 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2355 aty_st_le32(DP_CNTL, save_dp_cntl);
2356 }
2357
2358
2359 /*
2360 * Text mode accelerated functions
2361 */
2362
2363 static void
2364 fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2365 int height, int width)
2366 {
2367 sx *= fontwidth(p);
2368 sy *= fontheight(p);
2369 dx *= fontwidth(p);
2370 dy *= fontheight(p);
2371 width *= fontwidth(p);
2372 height *= fontheight(p);
2373
2374 aty128_rectcopy(sx, sy, dx, dy, width, height,
2375 (struct fb_info_aty128 *)p->fb_info);
2376 }
2377
2378
2379 #ifdef FBCON_HAS_CFB8
2380 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
2381 int c, int yy, int xx)
2382 {
2383 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2384
2385 if (fb->blitter_may_be_busy)
2386 wait_for_idle(fb);
2387
2388 fbcon_cfb8_putc(conp, p, c, yy, xx);
2389 }
2390
2391
2392 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
2393 const unsigned short *s, int count,
2394 int yy, int xx)
2395 {
2396 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2397
2398 if (fb->blitter_may_be_busy)
2399 wait_for_idle(fb);
2400
2401 fbcon_cfb8_putcs(conp, p, s, count, yy, xx);
2402 }
2403
2404
2405 static void fbcon_aty8_clear_margins(struct vc_data *conp,
2406 struct display *p, int bottom_only)
2407 {
2408 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2409
2410 if (fb->blitter_may_be_busy)
2411 wait_for_idle(fb);
2412
2413 fbcon_cfb8_clear_margins(conp, p, bottom_only);
2414 }
2415
2416 static struct display_switch fbcon_aty128_8 = {
2417 fbcon_cfb8_setup, fbcon_aty128_bmove, fbcon_cfb8_clear,
2418 fbcon_aty8_putc, fbcon_aty8_putcs, fbcon_cfb8_revc, NULL, NULL,
2419 fbcon_aty8_clear_margins,
2420 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2421 };
2422 #endif
2423 #ifdef FBCON_HAS_CFB16
2424 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
2425 int c, int yy, int xx)
2426 {
2427 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2428
2429 if (fb->blitter_may_be_busy)
2430 wait_for_idle(fb);
2431
2432 fbcon_cfb16_putc(conp, p, c, yy, xx);
2433 }
2434
2435
2436 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
2437 const unsigned short *s, int count,
2438 int yy, int xx)
2439 {
2440 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2441
2442 if (fb->blitter_may_be_busy)
2443 wait_for_idle(fb);
2444
2445 fbcon_cfb16_putcs(conp, p, s, count, yy, xx);
2446 }
2447
2448
2449 static void fbcon_aty16_clear_margins(struct vc_data *conp,
2450 struct display *p, int bottom_only)
2451 {
2452 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2453
2454 if (fb->blitter_may_be_busy)
2455 wait_for_idle(fb);
2456
2457 fbcon_cfb16_clear_margins(conp, p, bottom_only);
2458 }
2459
2460 static struct display_switch fbcon_aty128_16 = {
2461 fbcon_cfb16_setup, fbcon_aty128_bmove, fbcon_cfb16_clear,
2462 fbcon_aty16_putc, fbcon_aty16_putcs, fbcon_cfb16_revc, NULL, NULL,
2463 fbcon_aty16_clear_margins,
2464 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2465 };
2466 #endif
2467 #ifdef FBCON_HAS_CFB24
2468 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
2469 int c, int yy, int xx)
2470 {
2471 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2472
2473 if (fb->blitter_may_be_busy)
2474 wait_for_idle(fb);
2475
2476 fbcon_cfb24_putc(conp, p, c, yy, xx);
2477 }
2478
2479
2480 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
2481 const unsigned short *s, int count,
2482 int yy, int xx)
2483 {
2484 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2485
2486 if (fb->blitter_may_be_busy)
2487 wait_for_idle(fb);
2488
2489 fbcon_cfb24_putcs(conp, p, s, count, yy, xx);
2490 }
2491
2492
2493 static void fbcon_aty24_clear_margins(struct vc_data *conp,
2494 struct display *p, int bottom_only)
2495 {
2496 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2497
2498 if (fb->blitter_may_be_busy)
2499 wait_for_idle(fb);
2500
2501 fbcon_cfb24_clear_margins(conp, p, bottom_only);
2502 }
2503
2504 static struct display_switch fbcon_aty128_24 = {
2505 fbcon_cfb24_setup, fbcon_aty128_bmove, fbcon_cfb24_clear,
2506 fbcon_aty24_putc, fbcon_aty24_putcs, fbcon_cfb24_revc, NULL, NULL,
2507 fbcon_aty24_clear_margins,
2508 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2509 };
2510 #endif
2511 #ifdef FBCON_HAS_CFB32
2512 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
2513 int c, int yy, int xx)
2514 {
2515 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2516
2517 if (fb->blitter_may_be_busy)
2518 wait_for_idle(fb);
2519
2520 fbcon_cfb32_putc(conp, p, c, yy, xx);
2521 }
2522
2523
2524 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
2525 const unsigned short *s, int count,
2526 int yy, int xx)
2527 {
2528 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2529
2530 if (fb->blitter_may_be_busy)
2531 wait_for_idle(fb);
2532
2533 fbcon_cfb32_putcs(conp, p, s, count, yy, xx);
2534 }
2535
2536
2537 static void fbcon_aty32_clear_margins(struct vc_data *conp,
2538 struct display *p, int bottom_only)
2539 {
2540 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2541
2542 if (fb->blitter_may_be_busy)
2543 wait_for_idle(fb);
2544
2545 fbcon_cfb32_clear_margins(conp, p, bottom_only);
2546 }
2547
2548 static struct display_switch fbcon_aty128_32 = {
2549 fbcon_cfb32_setup, fbcon_aty128_bmove, fbcon_cfb32_clear,
2550 fbcon_aty32_putc, fbcon_aty32_putcs, fbcon_cfb32_revc, NULL, NULL,
2551 fbcon_aty32_clear_margins,
2552 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2553 };
2554 #endif
2555
2556 #ifdef MODULE
2557 MODULE_AUTHOR("(c)1999-2000 Brad Douglas <brad@neruo.com>");
2558 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2559
2560 int __init
2561 init_module(void)
2562 {
2563 aty128fb_init();
2564 return 0;
2565 }
2566
2567 void __exit
2568 cleanup_module(void)
2569 {
2570 struct fb_info_aty128 *info = board_list;
2571
2572 while (board_list) {
2573 info = board_list;
2574 board_list = board_list->next;
2575
2576 unregister_framebuffer(&info->fb_info);
2577 #ifdef CONFIG_MTRR
2578 if (info->mtrr.vram_valid)
2579 mtrr_del(info->mtrr.vram, info->frame_buffer_phys,
2580 info->vram_size);
2581 #endif /* CONFIG_MTRR */
2582 iounmap(info->regbase);
2583 iounmap(&info->frame_buffer);
2584
2585 release_mem_region(pci_resource_start(info->pdev, 0),
2586 pci_resource_len(info->pdev, 0));
2587 release_mem_region(pci_resource_start(info->pdev, 1),
2588 pci_resource_len(info->pdev, 1));
2589 release_mem_region(pci_resource_start(info->pdev, 2),
2590 pci_resource_len(info->pdev, 2));
2591
2592 kfree(info);
2593 }
2594 }
2595 #endif /* MODULE */
Mirror of the linux-mips.org kernel tree