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[linux-2.6/linux-mips.git] / drivers / scsi / gdth.h
blob946c782543a9ddf3965736c5cdabd04d669d060c
1 #ifndef _GDTH_H
2 #define _GDTH_H
3
4 /*
5 * Header file for the GDT ISA/EISA/PCI Disk Array Controller driver for Linux
6 *
7 * gdth.h Copyright (C) 1995-99 ICP vortex Computersysteme GmbH, Achim Leubner
8 * See gdth.c for further informations and
9 * below for supported controller types
10 *
11 * <achim@vortex.de>
12 *
13 * $Id: gdth.h,v 1.21 1999/03/26 09:12:24 achim Exp $
14 */
15
16 #include <linux/version.h>
17 #include <linux/types.h>
18
19 #ifndef NULL
20 #define NULL 0
21 #endif
22 #ifndef TRUE
23 #define TRUE 1
24 #endif
25 #ifndef FALSE
26 #define FALSE 0
27 #endif
28
29 /* defines, macros */
30
31 /* driver version */
32 #define GDTH_VERSION_STR "1.14"
33 #define GDTH_VERSION 1
34 #define GDTH_SUBVERSION 14
35
36 /* protocol version */
37 #define PROTOCOL_VERSION 1
38
39 /* controller classes */
40 #define GDT_ISA 0x01 /* ISA controller */
41 #define GDT_EISA 0x02 /* EISA controller */
42 #define GDT_PCI 0x03 /* PCI controller */
43 #define GDT_PCINEW 0x04 /* new PCI controller */
44 #define GDT_PCIMPR 0x05 /* PCI MPR controller */
45 /* GDT_EISA, controller subtypes EISA */
46 #define GDT3_ID 0x0130941c /* GDT3000/3020 */
47 #define GDT3A_ID 0x0230941c /* GDT3000A/3020A/3050A */
48 #define GDT3B_ID 0x0330941c /* GDT3000B/3010A */
49 /* GDT_ISA */
50 #define GDT2_ID 0x0120941c /* GDT2000/2020 */
51
52 /* vendor ID, device IDs (PCI) */
53 /* these defines should already exist in <linux/pci.h> */
54 #ifndef PCI_VENDOR_ID_VORTEX
55 #define PCI_VENDOR_ID_VORTEX 0x1119 /* PCI controller vendor ID */
56 #endif
57
58 #ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
59 /* GDT_PCI */
60 #define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */
61 #define PCI_DEVICE_ID_VORTEX_GDT6000B 1 /* GDT6000B/6010 */
62 /* GDT_PCINEW */
63 #define PCI_DEVICE_ID_VORTEX_GDT6x10 2 /* GDT6110/6510 */
64 #define PCI_DEVICE_ID_VORTEX_GDT6x20 3 /* GDT6120/6520 */
65 #define PCI_DEVICE_ID_VORTEX_GDT6530 4 /* GDT6530 */
66 #define PCI_DEVICE_ID_VORTEX_GDT6550 5 /* GDT6550 */
67 /* GDT_PCINEW, wide/ultra SCSI controllers */
68 #define PCI_DEVICE_ID_VORTEX_GDT6x17 6 /* GDT6117/6517 */
69 #define PCI_DEVICE_ID_VORTEX_GDT6x27 7 /* GDT6127/6527 */
70 #define PCI_DEVICE_ID_VORTEX_GDT6537 8 /* GDT6537 */
71 #define PCI_DEVICE_ID_VORTEX_GDT6557 9 /* GDT6557/6557-ECC */
72 /* GDT_PCINEW, wide SCSI controllers */
73 #define PCI_DEVICE_ID_VORTEX_GDT6x15 10 /* GDT6115/6515 */
74 #define PCI_DEVICE_ID_VORTEX_GDT6x25 11 /* GDT6125/6525 */
75 #define PCI_DEVICE_ID_VORTEX_GDT6535 12 /* GDT6535 */
76 #define PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */
77 #endif
78
79 #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP
80 /* GDT_MPR, RP series, wide/ultra SCSI */
81 #define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */
82 #define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */
83 #define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */
84 #define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */
85 /* GDT_MPR, RP series, narrow/ultra SCSI */
86 #define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */
87 #define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */
88 #endif
89 #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RD
90 /* GDT_MPR, RD series, wide/ultra SCSI */
91 #define PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */
92 #define PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */
93 #define PCI_DEVICE_ID_VORTEX_GDT6537RD 0x112 /* GDT6537RD */
94 #define PCI_DEVICE_ID_VORTEX_GDT6557RD 0x113 /* GDT6557RD */
95 /* GDT_MPR, RD series, narrow/ultra SCSI */
96 #define PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */
97 #define PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */
98 /* GDT_MPR, RD series, wide/ultra2 SCSI */
99 #define PCI_DEVICE_ID_VORTEX_GDT6x18RD 0x118 /* GDT6118RD/GDT6518RD/
100 GDT6618RD */
101 #define PCI_DEVICE_ID_VORTEX_GDT6x28RD 0x119 /* GDT6128RD/GDT6528RD/
102 GDT6628RD */
103 #define PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */
104 #define PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */
105 /* GDT_MPR, RN series (64-bit PCI), wide/ultra2 SCSI */
106 #define PCI_DEVICE_ID_VORTEX_GDT7x18RN 0x168 /* GDT7118RN/GDT7518RN/
107 GDT7618RN */
108 #define PCI_DEVICE_ID_VORTEX_GDT7x28RN 0x169 /* GDT7128RN/GDT7528RN/
109 GDT7628RN */
110 #define PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */
111 #define PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */
112 #endif
113
114 #ifndef PCI_DEVICE_ID_VORTEX_GDT6x19RD
115 /* GDT_MPR, RD series, Fibre Channel */
116 #define PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */
117 #define PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */
118 /* GDT_MPR, RN series (64-bit PCI), Fibre Channel */
119 #define PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */
120 #define PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */
121 #endif
122
123 #ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP
124 /* GDT_MPR, last device ID */
125 #define PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff
126 #endif
127
128 /* limits */
129 #define GDTH_SCRATCH PAGE_SIZE /* 4KB scratch buffer */
130 #define GDTH_SCRATCH_ORD 0 /* order 0 means 1 page */
131 #define GDTH_MAXCMDS 124
132 #define GDTH_MAXC_P_L 16 /* max. cmds per lun */
133 #define GDTH_MAX_RAW 2 /* max. cmds per raw device */
134 #define MAXOFFSETS 128
135 #define MAXHA 16
136 #define MAXID 127
137 #define MAXLUN 8
138 #define MAXBUS 6
139 #define MAX_HDRIVES 35 /* max. host drive count */
140 #define MAX_EVENTS 100 /* event buffer count */
141 #define MAX_RES_ARGS 40 /* device reservation,
142 must be a multiple of 4 */
143 #define MAXCYLS 1024
144 #define HEADS 64
145 #define SECS 32 /* mapping 64*32 */
146 #define MEDHEADS 127
147 #define MEDSECS 63 /* mapping 127*63 */
148 #define BIGHEADS 255
149 #define BIGSECS 63 /* mapping 255*63 */
150
151 /* special command ptr. */
152 #define UNUSED_CMND ((Scsi_Cmnd *)-1)
153 #define INTERNAL_CMND ((Scsi_Cmnd *)-2)
154 #define SCREEN_CMND ((Scsi_Cmnd *)-3)
155 #define SPECIAL_SCP(p) (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND)
156
157 /* controller services */
158 #define SCSIRAWSERVICE 3
159 #define CACHESERVICE 9
160 #define SCREENSERVICE 11
161
162 /* screenservice defines */
163 #define MSG_INV_HANDLE -1 /* special message handle */
164 #define MSGLEN 16 /* size of message text */
165 #define MSG_SIZE 34 /* size of message structure */
166 #define MSG_REQUEST 0 /* async. event: message */
167
168 /* cacheservice defines */
169 #define SECTOR_SIZE 0x200 /* always 512 bytes per sec. */
170
171 /* DPMEM constants */
172 #define DPMEM_MAGIC 0xC0FFEE11
173 #define IC_HEADER_BYTES 48
174 #define IC_QUEUE_BYTES 4
175 #define DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS
176
177 /* cache/raw service commands */
178 #define GDT_INIT 0 /* service initialization */
179 #define GDT_READ 1 /* read command */
180 #define GDT_WRITE 2 /* write command */
181 #define GDT_INFO 3 /* information about devices */
182 #define GDT_FLUSH 4 /* flush dirty cache buffers */
183 #define GDT_IOCTL 5 /* ioctl command */
184 #define GDT_DEVTYPE 9 /* additional information */
185 #define GDT_MOUNT 10 /* mount cache device */
186 #define GDT_UNMOUNT 11 /* unmount cache device */
187 #define GDT_SET_FEAT 12 /* set feat. (scatter/gather) */
188 #define GDT_GET_FEAT 13 /* get features */
189 #define GDT_WRITE_THR 16 /* write through */
190 #define GDT_READ_THR 17 /* read through */
191 #define GDT_EXT_INFO 18 /* extended info */
192 #define GDT_RESET 19 /* controller reset */
193
194 /* additional raw service commands */
195 #define GDT_RESERVE 14 /* reserve dev. to raw serv. */
196 #define GDT_RELEASE 15 /* release device */
197 #define GDT_RESERVE_ALL 16 /* reserve all devices */
198 #define GDT_RELEASE_ALL 17 /* release all devices */
199 #define GDT_RESET_BUS 18 /* reset bus */
200 #define GDT_SCAN_START 19 /* start device scan */
201 #define GDT_SCAN_END 20 /* stop device scan */
202
203 /* IOCTL command defines */
204 #define SCSI_DR_INFO 0x00 /* SCSI drive info */
205 #define SCSI_CHAN_CNT 0x05 /* SCSI channel count */
206 #define SCSI_DR_LIST 0x06 /* SCSI drive list */
207 #define SCSI_DEF_CNT 0x15 /* grown/primary defects */
208 #define DSK_STATISTICS 0x4b /* SCSI disk statistics */
209 #define IOCHAN_DESC 0x5d /* description of IO channel */
210 #define IOCHAN_RAW_DESC 0x5e /* description of raw IO channel */
211 #define L_CTRL_PATTERN 0x20000000L /* SCSI IOCTL mask */
212 #define ARRAY_INFO 0x12 /* array drive info */
213 #define ARRAY_DRV_LIST 0x0f /* array drive list */
214 #define LA_CTRL_PATTERN 0x10000000L /* array IOCTL mask */
215 #define CACHE_DRV_CNT 0x01 /* cache drive count */
216 #define CACHE_DRV_LIST 0x02 /* cache drive list */
217 #define CACHE_INFO 0x04 /* cache info */
218 #define CACHE_CONFIG 0x05 /* cache configuration */
219 #define CACHE_DRV_INFO 0x07 /* cache drive info */
220 #define BOARD_FEATURES 0x15 /* controller features */
221 #define BOARD_INFO 0x28 /* controller info */
222 #define HOST_GET 0x10001L /* get host drive list */
223 #define IO_CHANNEL 0x00020000L /* default IO channel */
224 #define INVALID_CHANNEL 0x0000ffffL /* invalid channel */
225
226 /* IOCTLs */
227 #define GDTIOCTL_MASK ('J'<<8)
228 #define GDTIOCTL_GENERAL (GDTIOCTL_MASK | 0) /* general IOCTL */
229 #define GDTIOCTL_DRVERS (GDTIOCTL_MASK | 1) /* get driver version */
230 #define GDTIOCTL_CTRTYPE (GDTIOCTL_MASK | 2) /* get controller type */
231 #define GDTIOCTL_CTRCNT (GDTIOCTL_MASK | 5) /* get controller count */
232 #define GDTIOCTL_LOCKDRV (GDTIOCTL_MASK | 6) /* lock host drive */
233 #define GDTIOCTL_LOCKCHN (GDTIOCTL_MASK | 7) /* lock channel */
234 #define GDTIOCTL_EVENT (GDTIOCTL_MASK | 8) /* read controller events */
235
236 /* service errors */
237 #define S_OK 1 /* no error */
238 #define S_BSY 7 /* controller busy */
239 #define S_RAW_SCSI 12 /* raw serv.: target error */
240 #define S_RAW_ILL 0xff /* raw serv.: illegal */
241
242 /* timeout values */
243 #define INIT_RETRIES 100000 /* 100000 * 1ms = 100s */
244 #define INIT_TIMEOUT 100000 /* 100000 * 1ms = 100s */
245 #define POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */
246
247 /* priorities */
248 #define DEFAULT_PRI 0x20
249 #define IOCTL_PRI 0x10
250 #define HIGH_PRI 0x08
251
252 /* data directions */
253 #define DATA_IN 0x01000000L /* data from target */
254 #define DATA_OUT 0x00000000L /* data to target */
255
256 /* BMIC registers (EISA controllers) */
257 #define ID0REG 0x0c80 /* board ID */
258 #define EINTENABREG 0x0c89 /* interrupt enable */
259 #define SEMA0REG 0x0c8a /* command semaphore */
260 #define SEMA1REG 0x0c8b /* status semaphore */
261 #define LDOORREG 0x0c8d /* local doorbell */
262 #define EDENABREG 0x0c8e /* EISA system doorbell enab. */
263 #define EDOORREG 0x0c8f /* EISA system doorbell */
264 #define MAILBOXREG 0x0c90 /* mailbox reg. (16 bytes) */
265 #define EISAREG 0x0cc0 /* EISA configuration */
266
267 /* other defines */
268 #define LINUX_OS 8 /* used for cache optim. */
269 #define SCATTER_GATHER 1 /* s/g feature */
270 #define GDTH_MAXSG 32 /* max. s/g elements */
271 #define SECS32 0x1f /* round capacity */
272 #define BIOS_ID_OFFS 0x10 /* offset contr-ID in ISABIOS */
273 #define LOCALBOARD 0 /* board node always 0 */
274 #define ASYNCINDEX 0 /* cmd index async. event */
275 #define SPEZINDEX 1 /* cmd index unknown service */
276 #define GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */
277
278
279 /* typedefs */
280 typedef u32 ulong32;
281 #define PACKED __attribute__((packed))
282
283 /* screenservice message */
284 typedef struct {
285 ulong32 msg_handle; /* message handle */
286 ulong32 msg_len; /* size of message */
287 ulong32 msg_alen; /* answer length */
288 unchar msg_answer; /* answer flag */
289 unchar msg_ext; /* more messages */
290 unchar msg_reserved[2];
291 char msg_text[MSGLEN+2]; /* the message text */
292 } PACKED gdth_msg_str;
293
294 /* IOCTL data structures */
295 /* SCSI drive info */
296 typedef struct {
297 unchar vendor[8]; /* vendor string */
298 unchar product[16]; /* product string */
299 unchar revision[4]; /* revision */
300 ulong32 sy_rate; /* current rate for sync. tr. */
301 ulong32 sy_max_rate; /* max. rate for sync. tr. */
302 ulong32 no_ldrive; /* belongs to this logical drv.*/
303 ulong32 blkcnt; /* number of blocks */
304 ushort blksize; /* size of block in bytes */
305 unchar available; /* flag: access is available */
306 unchar init; /* medium is initialized */
307 unchar devtype; /* SCSI devicetype */
308 unchar rm_medium; /* medium is removable */
309 unchar wp_medium; /* medium is write protected */
310 unchar ansi; /* SCSI I/II or III? */
311 unchar protocol; /* same as ansi */
312 unchar sync; /* flag: sync. transfer enab. */
313 unchar disc; /* flag: disconnect enabled */
314 unchar queueing; /* flag: command queing enab. */
315 unchar cached; /* flag: caching enabled */
316 unchar target_id; /* target ID of device */
317 unchar lun; /* LUN id of device */
318 unchar orphan; /* flag: drive fragment */
319 ulong32 last_error; /* sense key or drive state */
320 ulong32 last_result; /* result of last command */
321 ulong32 check_errors; /* err. in last surface check */
322 unchar percent; /* progress for surface check */
323 unchar last_check; /* IOCTRL operation */
324 unchar res[2];
325 ulong32 flags; /* from 1.19/2.19: raw reserv.*/
326 unchar multi_bus; /* multi bus dev? (fibre ch.) */
327 unchar mb_status; /* status: available? */
328 unchar res2[2];
329 unchar mb_alt_status; /* status on second bus */
330 unchar mb_alt_bid; /* number of second bus */
331 unchar mb_alt_tid; /* target id on second bus */
332 unchar res3;
333 unchar fc_flag; /* from 1.22/2.22: info valid?*/
334 unchar res4;
335 ushort fc_frame_size; /* frame size (bytes) */
336 char wwn[8]; /* world wide name */
337 } PACKED gdth_diskinfo_str;
338
339 /* get SCSI channel count */
340 typedef struct {
341 ulong32 channel_no; /* number of channel */
342 ulong32 drive_cnt; /* drive count */
343 unchar siop_id; /* SCSI processor ID */
344 unchar siop_state; /* SCSI processor state */
345 } PACKED gdth_getch_str;
346
347 /* get SCSI drive numbers */
348 typedef struct {
349 ulong32 sc_no; /* SCSI channel */
350 ulong32 sc_cnt; /* sc_list[] elements */
351 ulong32 sc_list[MAXID]; /* minor device numbers */
352 } PACKED gdth_drlist_str;
353
354 /* get grown/primary defect count */
355 typedef struct {
356 unchar sddc_type; /* 0x08: grown, 0x10: prim. */
357 unchar sddc_format; /* list entry format */
358 unchar sddc_len; /* list entry length */
359 unchar sddc_res;
360 ulong32 sddc_cnt; /* entry count */
361 } PACKED gdth_defcnt_str;
362
363 /* disk statistics */
364 typedef struct {
365 ulong32 bid; /* SCSI channel */
366 ulong32 first; /* first SCSI disk */
367 ulong32 entries; /* number of elements */
368 ulong32 count; /* (R) number of init. el. */
369 ulong32 mon_time; /* time stamp */
370 struct {
371 unchar tid; /* target ID */
372 unchar lun; /* LUN */
373 unchar res[2];
374 ulong32 blk_size; /* block size in bytes */
375 ulong32 rd_count; /* bytes read */
376 ulong32 wr_count; /* bytes written */
377 ulong32 rd_blk_count; /* blocks read */
378 ulong32 wr_blk_count; /* blocks written */
379 ulong32 retries; /* retries */
380 ulong32 reassigns; /* reassigns */
381 } PACKED list[1];
382 } PACKED gdth_dskstat_str;
383
384 /* IO channel header */
385 typedef struct {
386 ulong32 version; /* version (-1UL: newest) */
387 unchar list_entries; /* list entry count */
388 unchar first_chan; /* first channel number */
389 unchar last_chan; /* last channel number */
390 unchar chan_count; /* (R) channel count */
391 ulong32 list_offset; /* offset of list[0] */
392 } PACKED gdth_iochan_header;
393
394 /* get IO channel description */
395 typedef struct {
396 gdth_iochan_header hdr;
397 struct {
398 ulong32 address; /* channel address */
399 unchar type; /* type (SCSI, FCAL) */
400 unchar local_no; /* local number */
401 ushort features; /* channel features */
402 } PACKED list[MAXBUS];
403 } PACKED gdth_iochan_str;
404
405 /* get raw IO channel description */
406 typedef struct {
407 gdth_iochan_header hdr;
408 struct {
409 unchar proc_id; /* processor id */
410 unchar proc_defect; /* defect ? */
411 unchar reserved[2];
412 } PACKED list[MAXBUS];
413 } PACKED gdth_raw_iochan_str;
414
415 /* array drive component */
416 typedef struct {
417 ulong32 al_controller; /* controller ID */
418 unchar al_cache_drive; /* cache drive number */
419 unchar al_status; /* cache drive state */
420 unchar al_res[2];
421 } PACKED gdth_arraycomp_str;
422
423 /* array drive information */
424 typedef struct {
425 unchar ai_type; /* array type (RAID0,4,5) */
426 unchar ai_cache_drive_cnt; /* active cachedrives */
427 unchar ai_state; /* array drive state */
428 unchar ai_master_cd; /* master cachedrive */
429 ulong32 ai_master_controller; /* ID of master controller */
430 ulong32 ai_size; /* user capacity [sectors] */
431 ulong32 ai_striping_size; /* striping size [sectors] */
432 ulong32 ai_secsize; /* sector size [bytes] */
433 ulong32 ai_err_info; /* failed cache drive */
434 unchar ai_name[8]; /* name of the array drive */
435 unchar ai_controller_cnt; /* number of controllers */
436 unchar ai_removable; /* flag: removable */
437 unchar ai_write_protected; /* flag: write protected */
438 unchar ai_devtype; /* type: always direct access */
439 gdth_arraycomp_str ai_drives[35]; /* drive components: */
440 unchar ai_drive_entries; /* number of drive components */
441 unchar ai_protected; /* protection flag */
442 unchar ai_verify_state; /* state of a parity verify */
443 unchar ai_ext_state; /* extended array drive state */
444 unchar ai_expand_state; /* array expand state (>=2.18)*/
445 unchar ai_reserved[3];
446 } PACKED gdth_arrayinf_str;
447
448 /* get array drive list */
449 typedef struct {
450 ulong32 controller_no; /* controller no. */
451 unchar cd_handle; /* master cachedrive */
452 unchar is_arrayd; /* Flag: is array drive? */
453 unchar is_master; /* Flag: is array master? */
454 unchar is_parity; /* Flag: is parity drive? */
455 unchar is_hotfix; /* Flag: is hotfix drive? */
456 unchar res[3];
457 } PACKED gdth_arraylist_str;
458
459 /* cache info/config IOCTL */
460 typedef struct {
461 ulong32 version; /* firmware version */
462 ushort state; /* cache state (on/off) */
463 ushort strategy; /* cache strategy */
464 ushort write_back; /* write back state (on/off) */
465 ushort block_size; /* cache block size */
466 } PACKED gdth_cpar_str;
467
468 typedef struct {
469 ulong32 csize; /* cache size */
470 ulong32 read_cnt; /* read/write counter */
471 ulong32 write_cnt;
472 ulong32 tr_hits; /* hits */
473 ulong32 sec_hits;
474 ulong32 sec_miss; /* misses */
475 } PACKED gdth_cstat_str;
476
477 typedef struct {
478 gdth_cpar_str cpar;
479 gdth_cstat_str cstat;
480 } PACKED gdth_cinfo_str;
481
482 /* cache drive info */
483 typedef struct {
484 unchar cd_name[8]; /* cache drive name */
485 ulong32 cd_devtype; /* SCSI devicetype */
486 ulong32 cd_ldcnt; /* number of log. drives */
487 ulong32 cd_last_error; /* last error */
488 unchar cd_initialized; /* drive is initialized */
489 unchar cd_removable; /* media is removable */
490 unchar cd_write_protected; /* write protected */
491 unchar cd_flags; /* Pool Hot Fix? */
492 ulong32 ld_blkcnt; /* number of blocks */
493 ulong32 ld_blksize; /* blocksize */
494 ulong32 ld_dcnt; /* number of disks */
495 ulong32 ld_slave; /* log. drive index */
496 ulong32 ld_dtype; /* type of logical drive */
497 ulong32 ld_last_error; /* last error */
498 unchar ld_name[8]; /* log. drive name */
499 unchar ld_error; /* error */
500 } PACKED gdth_cdrinfo_str;
501
502 /* board features */
503 typedef struct {
504 unchar chaining; /* Chaining supported */
505 unchar striping; /* Striping (RAID-0) supp. */
506 unchar mirroring; /* Mirroring (RAID-1) supp. */
507 unchar raid; /* RAID-4/5/10 supported */
508 } PACKED gdth_bfeat_str;
509
510 /* board info IOCTL */
511 typedef struct {
512 ulong32 ser_no; /* serial no. */
513 unchar oem_id[2]; /* OEM ID */
514 ushort ep_flags; /* eprom flags */
515 ulong32 proc_id; /* processor ID */
516 ulong32 memsize; /* memory size (bytes) */
517 unchar mem_banks; /* memory banks */
518 unchar chan_type; /* channel type */
519 unchar chan_count; /* channel count */
520 unchar rdongle_pres; /* dongle present? */
521 ulong32 epr_fw_ver; /* (eprom) firmware version */
522 ulong32 upd_fw_ver; /* (update) firmware version */
523 ulong32 upd_revision; /* update revision */
524 char type_string[16]; /* controller name */
525 char raid_string[16]; /* RAID firmware name */
526 unchar update_pres; /* update present? */
527 unchar xor_pres; /* XOR engine present? */
528 unchar prom_type; /* ROM type (eprom/flash) */
529 unchar prom_count; /* number of ROM devices */
530 ulong32 dup_pres; /* duplexing module present? */
531 ulong32 chan_pres; /* number of expansion chn. */
532 ulong32 mem_pres; /* memory expansion inst. ? */
533 unchar ft_bus_system; /* fault bus supported? */
534 unchar subtype_valid; /* board_subtype valid? */
535 unchar board_subtype; /* subtype/hardware level */
536 unchar ramparity_pres; /* RAM parity check hardware? */
537 } PACKED gdth_binfo_str;
538
539 /* get host drive info */
540 typedef struct {
541 char name[8]; /* host drive name */
542 ulong32 size; /* size (sectors) */
543 unchar host_drive; /* host drive number */
544 unchar log_drive; /* log. drive (master) */
545 unchar reserved;
546 unchar rw_attribs; /* r/w attribs */
547 ulong32 start_sec; /* start sector */
548 } PACKED gdth_hentry_str;
549
550 typedef struct {
551 ulong32 entries; /* entry count */
552 ulong32 offset; /* offset of entries */
553 unchar secs_p_head; /* sectors/head */
554 unchar heads_p_cyl; /* heads/cylinder */
555 unchar reserved;
556 unchar clust_drvtype; /* cluster drive type */
557 ulong32 location; /* controller number */
558 gdth_hentry_str entry[MAX_HDRIVES]; /* entries */
559 } PACKED gdth_hget_str;
560
561 /* scatter/gather element */
562 typedef struct {
563 ulong32 sg_ptr; /* address */
564 ulong32 sg_len; /* length */
565 } PACKED gdth_sg_str;
566
567 /* command structure */
568 typedef struct {
569 ulong32 BoardNode; /* board node (always 0) */
570 ulong32 CommandIndex; /* command number */
571 ushort OpCode; /* the command (READ,..) */
572 union {
573 struct {
574 ushort DeviceNo; /* number of cache drive */
575 ulong32 BlockNo; /* block number */
576 ulong32 BlockCnt; /* block count */
577 ulong32 DestAddr; /* dest. addr. (if s/g: -1) */
578 ulong32 sg_canz; /* s/g element count */
579 gdth_sg_str sg_lst[GDTH_MAXSG]; /* s/g list */
580 } PACKED cache; /* cache service cmd. str. */
581 struct {
582 ushort param_size; /* size of p_param buffer */
583 ulong32 subfunc; /* IOCTL function */
584 ulong32 channel; /* device */
585 ulong32 p_param; /* buffer */
586 } PACKED ioctl; /* IOCTL command structure */
587 struct {
588 ushort reserved;
589 ulong32 msg_handle; /* message handle */
590 ulong32 msg_addr; /* message buffer address */
591 } PACKED screen; /* screen service cmd. str. */
592 struct {
593 ushort reserved;
594 ulong32 direction; /* data direction */
595 ulong32 mdisc_time; /* disc. time (0: no timeout)*/
596 ulong32 mcon_time; /* connect time(0: no to.) */
597 ulong32 sdata; /* dest. addr. (if s/g: -1) */
598 ulong32 sdlen; /* data length (bytes) */
599 ulong32 clen; /* SCSI cmd. length(6,10,12) */
600 unchar cmd[12]; /* SCSI command */
601 unchar target; /* target ID */
602 unchar lun; /* LUN */
603 unchar bus; /* SCSI bus number */
604 unchar priority; /* only 0 used */
605 ulong32 sense_len; /* sense data length */
606 ulong32 sense_data; /* sense data addr. */
607 struct raw *link_p; /* linked cmds (not supp.) */
608 ulong32 sg_ranz; /* s/g element count */
609 gdth_sg_str sg_lst[GDTH_MAXSG]; /* s/g list */
610 } PACKED raw; /* raw service cmd. struct. */
611 } u;
612 /* additional variables */
613 unchar Service; /* controller service */
614 ushort Status; /* command result */
615 ulong32 Info; /* additional information */
616 Scsi_Cmnd *RequestBuffer; /* request buffer */
617 } PACKED gdth_cmd_str;
618
619 /* controller event structure */
620 #define ES_ASYNC 1
621 #define ES_DRIVER 2
622 #define ES_TEST 3
623 #define ES_SYNC 4
624 typedef struct {
625 ushort size; /* size of structure */
626 union {
627 char stream[16];
628 struct {
629 ushort ionode;
630 ushort service;
631 ulong32 index;
632 } PACKED driver;
633 struct {
634 ushort ionode;
635 ushort service;
636 ushort status;
637 ulong32 info;
638 unchar scsi_coord[3];
639 } PACKED async;
640 struct {
641 ushort ionode;
642 ushort service;
643 ushort status;
644 ulong32 info;
645 ushort hostdrive;
646 unchar scsi_coord[3];
647 unchar sense_key;
648 } PACKED sync;
649 struct {
650 ulong32 l1, l2, l3, l4;
651 } PACKED test;
652 } eu;
653 } PACKED gdth_evt_data;
654
655 typedef struct {
656 ulong32 first_stamp;
657 ulong32 last_stamp;
658 ushort same_count;
659 ushort event_source;
660 ushort event_idx;
661 unchar application;
662 unchar reserved;
663 gdth_evt_data event_data;
664 } PACKED gdth_evt_str;
665
666
667 /* DPRAM structures */
668
669 /* interface area ISA/PCI */
670 typedef struct {
671 unchar S_Cmd_Indx; /* special command */
672 unchar volatile S_Status; /* status special command */
673 ushort reserved1;
674 ulong32 S_Info[4]; /* add. info special command */
675 unchar volatile Sema0; /* command semaphore */
676 unchar reserved2[3];
677 unchar Cmd_Index; /* command number */
678 unchar reserved3[3];
679 ushort volatile Status; /* command status */
680 ushort Service; /* service(for async.events) */
681 ulong32 Info[2]; /* additional info */
682 struct {
683 ushort offset; /* command offs. in the DPRAM*/
684 ushort serv_id; /* service */
685 } PACKED comm_queue[MAXOFFSETS]; /* command queue */
686 ulong32 bios_reserved[2];
687 unchar gdt_dpr_cmd[1]; /* commands */
688 } PACKED gdt_dpr_if;
689
690 /* SRAM structure PCI controllers */
691 typedef struct {
692 ulong32 magic; /* controller ID from BIOS */
693 ushort need_deinit; /* switch betw. BIOS/driver */
694 unchar switch_support; /* see need_deinit */
695 unchar padding[9];
696 unchar os_used[16]; /* OS code per service */
697 unchar unused[28];
698 unchar fw_magic; /* contr. ID from firmware */
699 } PACKED gdt_pci_sram;
700
701 /* SRAM structure EISA controllers (but NOT GDT3000/3020) */
702 typedef struct {
703 unchar os_used[16]; /* OS code per service */
704 ushort need_deinit; /* switch betw. BIOS/driver */
705 unchar switch_support; /* see need_deinit */
706 unchar padding;
707 } PACKED gdt_eisa_sram;
708
709
710 /* DPRAM ISA controllers */
711 typedef struct {
712 union {
713 struct {
714 unchar bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */
715 ulong32 magic; /* controller (EISA) ID */
716 ushort need_deinit; /* switch betw. BIOS/driver */
717 unchar switch_support; /* see need_deinit */
718 unchar padding[9];
719 unchar os_used[16]; /* OS code per service */
720 } PACKED dp_sram;
721 unchar bios_area[0x4000]; /* 16KB reserved for BIOS */
722 } bu;
723 union {
724 gdt_dpr_if ic; /* interface area */
725 unchar if_area[0x3000]; /* 12KB for interface */
726 } u;
727 struct {
728 unchar memlock; /* write protection DPRAM */
729 unchar event; /* release event */
730 unchar irqen; /* board interrupts enable */
731 unchar irqdel; /* acknowledge board int. */
732 unchar volatile Sema1; /* status semaphore */
733 unchar rq; /* IRQ/DRQ configuration */
734 } PACKED io;
735 } PACKED gdt2_dpram_str;
736
737 /* DPRAM PCI controllers */
738 typedef struct {
739 union {
740 gdt_dpr_if ic; /* interface area */
741 unchar if_area[0xff0-sizeof(gdt_pci_sram)];
742 } u;
743 gdt_pci_sram gdt6sr; /* SRAM structure */
744 struct {
745 unchar unused0[1];
746 unchar volatile Sema1; /* command semaphore */
747 unchar unused1[3];
748 unchar irqen; /* board interrupts enable */
749 unchar unused2[2];
750 unchar event; /* release event */
751 unchar unused3[3];
752 unchar irqdel; /* acknowledge board int. */
753 unchar unused4[3];
754 } PACKED io;
755 } PACKED gdt6_dpram_str;
756
757 /* PLX register structure (new PCI controllers) */
758 typedef struct {
759 unchar cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/
760 unchar unused1[0x3f];
761 unchar volatile sema0_reg; /* command semaphore */
762 unchar volatile sema1_reg; /* status semaphore */
763 unchar unused2[2];
764 ushort volatile status; /* command status */
765 ushort service; /* service */
766 ulong32 info[2]; /* additional info */
767 unchar unused3[0x10];
768 unchar ldoor_reg; /* PCI to local doorbell */
769 unchar unused4[3];
770 unchar volatile edoor_reg; /* local to PCI doorbell */
771 unchar unused5[3];
772 unchar control0; /* control0 register(unused) */
773 unchar control1; /* board interrupts enable */
774 unchar unused6[0x16];
775 } PACKED gdt6c_plx_regs;
776
777 /* DPRAM new PCI controllers */
778 typedef struct {
779 union {
780 gdt_dpr_if ic; /* interface area */
781 unchar if_area[0x4000-sizeof(gdt_pci_sram)];
782 } u;
783 gdt_pci_sram gdt6sr; /* SRAM structure */
784 } PACKED gdt6c_dpram_str;
785
786 /* i960 register structure (PCI MPR controllers) */
787 typedef struct {
788 unchar unused1[16];
789 unchar volatile sema0_reg; /* command semaphore */
790 unchar unused2;
791 unchar volatile sema1_reg; /* status semaphore */
792 unchar unused3;
793 ushort volatile status; /* command status */
794 ushort service; /* service */
795 ulong32 info[2]; /* additional info */
796 unchar ldoor_reg; /* PCI to local doorbell */
797 unchar unused4[11];
798 unchar volatile edoor_reg; /* local to PCI doorbell */
799 unchar unused5[7];
800 unchar edoor_en_reg; /* board interrupts enable */
801 unchar unused6[27];
802 ulong32 unused7[1004]; /* size: 4 KB */
803 } PACKED gdt6m_i960_regs;
804
805 /* DPRAM PCI MPR controllers */
806 typedef struct {
807 gdt6m_i960_regs i960r; /* 4KB i960 registers */
808 union {
809 gdt_dpr_if ic; /* interface area */
810 unchar if_area[0x3000-sizeof(gdt_pci_sram)];
811 } u;
812 gdt_pci_sram gdt6sr; /* SRAM structure */
813 } PACKED gdt6m_dpram_str;
814
815
816 /* PCI resources */
817 typedef struct {
818 struct pci_dev *pdev;
819 ushort device_id; /* device ID (0,..,9) */
820 unchar bus; /* PCI bus */
821 unchar device_fn; /* PCI device/function no. */
822 ulong dpmem; /* DPRAM address */
823 ulong io; /* IO address */
824 ulong io_mm; /* IO address mem. mapped */
825 unchar irq; /* IRQ */
826 } gdth_pci_str;
827
828
829 /* controller information structure */
830 typedef struct {
831 ushort type; /* controller class */
832 ushort raw_feat; /* feat. raw service (s/g,..) */
833 ulong32 stype; /* controller subtype */
834 ushort cache_feat; /* feat. cache serv. (s/g,..) */
835 ushort bmic; /* BMIC address (EISA) */
836 void *brd; /* DPRAM address */
837 ulong32 brd_phys; /* slot number/BIOS address */
838 gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */
839 gdth_cmd_str *pccb; /* address command structure */
840 char *pscratch; /* scratch (DMA) buffer */
841 unchar scratch_busy; /* in use? */
842 unchar scan_mode; /* current scan mode */
843 unchar irq; /* IRQ */
844 unchar drq; /* DRQ (ISA controllers) */
845 ushort status; /* command status */
846 ulong32 info;
847 ulong32 info2; /* additional info */
848 Scsi_Cmnd *req_first; /* top of request queue */
849 struct {
850 unchar present; /* Flag: host drive present? */
851 unchar is_logdrv; /* Flag: logical drive (master)? */
852 unchar is_arraydrv; /* Flag: array drive? */
853 unchar is_master; /* Flag: array drive master? */
854 unchar is_parity; /* Flag: parity drive? */
855 unchar is_hotfix; /* Flag: hotfix drive? */
856 unchar master_no; /* number of master drive */
857 unchar lock; /* drive locked? (hot plug) */
858 unchar heads; /* mapping */
859 unchar secs;
860 ushort devtype; /* further information */
861 ulong32 size; /* capacity */
862 unchar ldr_no; /* log. drive no. */
863 unchar rw_attribs; /* r/w attributes */
864 ulong32 start_sec; /* start sector */
865 } hdr[MAX_HDRIVES]; /* host drives */
866 struct {
867 unchar lock; /* channel locked? (hot plug) */
868 unchar pdev_cnt; /* physical device count */
869 unchar local_no; /* local channel number */
870 unchar io_cnt[MAXID]; /* current IO count */
871 ulong32 address; /* channel address */
872 ulong32 id_list[MAXID]; /* IDs of the phys. devices */
873 } raw[MAXBUS]; /* SCSI channels */
874 struct {
875 Scsi_Cmnd *cmnd; /* pending request */
876 ushort service; /* service */
877 } cmd_tab[GDTH_MAXCMDS]; /* table of pend. requests */
878 unchar bus_cnt; /* SCSI bus count */
879 unchar tid_cnt; /* Target ID count */
880 unchar bus_id[MAXBUS]; /* IOP IDs */
881 unchar virt_bus; /* number of virtual bus */
882 unchar more_proc; /* more /proc info supported */
883 ushort cmd_cnt; /* command count in DPRAM */
884 ushort cmd_len; /* length of actual command */
885 ushort cmd_offs_dpmem; /* actual offset in DPRAM */
886 ushort ic_all_size; /* sizeof DPRAM interf. area */
887 gdth_cpar_str cpar; /* controller cache par. */
888 gdth_bfeat_str bfeat; /* controller features */
889 gdth_binfo_str binfo; /* controller info */
890 spinlock_t smp_lock;
891 } gdth_ha_str;
892
893 /* structure for scsi_register(), SCSI bus != 0 */
894 typedef struct {
895 ushort hanum;
896 ushort busnum;
897 } gdth_num_str;
898
899 /* structure for scsi_register() */
900 typedef struct {
901 gdth_num_str numext; /* must be the first element */
902 gdth_ha_str haext;
903 gdth_cmd_str cmdext;
904 } gdth_ext_str;
905
906
907 /* INQUIRY data format */
908 typedef struct {
909 unchar type_qual;
910 unchar modif_rmb;
911 unchar version;
912 unchar resp_aenc;
913 unchar add_length;
914 unchar reserved1;
915 unchar reserved2;
916 unchar misc;
917 unchar vendor[8];
918 unchar product[16];
919 unchar revision[4];
920 } PACKED gdth_inq_data;
921
922 /* READ_CAPACITY data format */
923 typedef struct {
924 ulong32 last_block_no;
925 ulong32 block_length;
926 } PACKED gdth_rdcap_data;
927
928 /* REQUEST_SENSE data format */
929 typedef struct {
930 unchar errorcode;
931 unchar segno;
932 unchar key;
933 ulong32 info;
934 unchar add_length;
935 ulong32 cmd_info;
936 unchar adsc;
937 unchar adsq;
938 unchar fruc;
939 unchar key_spec[3];
940 } PACKED gdth_sense_data;
941
942 /* MODE_SENSE data format */
943 typedef struct {
944 struct {
945 unchar data_length;
946 unchar med_type;
947 unchar dev_par;
948 unchar bd_length;
949 } PACKED hd;
950 struct {
951 unchar dens_code;
952 unchar block_count[3];
953 unchar reserved;
954 unchar block_length[3];
955 } PACKED bd;
956 } PACKED gdth_modep_data;
957
958 /* stack frame */
959 typedef struct {
960 ulong b[10]; /* 32/64 bit compiler ! */
961 } PACKED gdth_stackframe;
962
963
964 /* function prototyping */
965
966 int gdth_detect(Scsi_Host_Template *);
967 int gdth_release(struct Scsi_Host *);
968 int gdth_command(Scsi_Cmnd *);
969 int gdth_queuecommand(Scsi_Cmnd *,void (*done)(Scsi_Cmnd *));
970 int gdth_abort(Scsi_Cmnd *);
971 int gdth_reset(Scsi_Cmnd *, unsigned int reset_flags);
972 const char *gdth_info(struct Scsi_Host *);
973
974 int gdth_bios_param(Disk *,kdev_t,int *);
975 int gdth_proc_info(char *,char **,off_t,int,int,int);
976 int gdth_eh_abort(Scsi_Cmnd *scp);
977 int gdth_eh_device_reset(Scsi_Cmnd *scp);
978 int gdth_eh_bus_reset(Scsi_Cmnd *scp);
979 int gdth_eh_host_reset(Scsi_Cmnd *scp);
980 #define GDTH { proc_name: "gdth", \
981 proc_info: gdth_proc_info, \
982 name: "GDT SCSI Disk Array Controller",\
983 detect: gdth_detect, \
984 release: gdth_release, \
985 info: gdth_info, \
986 command: gdth_command, \
987 queuecommand: gdth_queuecommand, \
988 eh_abort_handler: gdth_eh_abort, \
989 eh_device_reset_handler: gdth_eh_device_reset, \
990 eh_bus_reset_handler: gdth_eh_bus_reset, \
991 eh_host_reset_handler: gdth_eh_host_reset, \
992 abort: gdth_abort, \
993 reset: gdth_reset, \
994 bios_param: gdth_bios_param, \
995 can_queue: GDTH_MAXCMDS, \
996 this_id: -1, \
997 sg_tablesize: GDTH_MAXSG, \
998 cmd_per_lun: GDTH_MAXC_P_L, \
999 present: 0, \
1000 unchecked_isa_dma: 1, \
1001 use_clustering: ENABLE_CLUSTERING, \
1002 use_new_eh_code: 1 /* use new error code */ }
1003 #endif
1004
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