drivers/ieee1394/pcilynx.h

   1 #include <linux/config.h>
   2
   3 #define PCILYNX_DRIVER_NAME      "pcilynx"
   4 #define PCILYNX_MAJOR            177
   5
   6 #define PCILYNX_MINOR_AUX_START  0
   7 #define PCILYNX_MINOR_ROM_START  16
   8 #define PCILYNX_MINOR_RAM_START  32
   9
  10 #define PCILYNX_MAX_REGISTER     0xfff
  11 #define PCILYNX_MAX_MEMORY       0xffff
  12
  13 #define PCI_DEVICE_ID_TI_PCILYNX 0x8000
  14 #define MAX_PCILYNX_CARDS        4
  15 #define LOCALRAM_SIZE            4096
  16
  17 #define NUM_ISORCV_PCL           4
  18 #define MAX_ISORCV_SIZE          2048
  19 #define ISORCV_PER_PAGE          (PAGE_SIZE / MAX_ISORCV_SIZE)
  20 #define ISORCV_PAGES             (NUM_ISORCV_PCL / ISORCV_PER_PAGE)
  21
  22 /* only iso rcv and localbus use these definitions so far */
  23 #define CHANNEL_LOCALBUS         0
  24 #define CHANNEL_ASYNC_RCV        1
  25 #define CHANNEL_ISO_RCV          2
  26 #define CHANNEL_ASYNC_SEND       3
  27
  28 typedef int pcl_t;
  29
  30 struct ti_lynx {
  31         int id; /* sequential card number */
  32
  33         spinlock_t lock;
  34
  35         struct pci_dev *dev;
  36
  37         struct {
  38                 unsigned reg_1394a:1;
  39                 u32 vendor;
  40                 u32 product;
  41         } phyic;
  42
  43         enum { clear, have_intr, have_aux_buf, have_pcl_mem,
  44                have_1394_buffers, have_iomappings } state;
  45
  46         /* remapped memory spaces */
  47         void *registers;
  48         void *local_rom;
  49         void *local_ram;
  50         void *aux_port;
  51
  52
  53 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
  54         atomic_t aux_intr_seen;
  55         wait_queue_head_t aux_intr_wait;
  56
  57         void *mem_dma_buffer;
  58         dma_addr_t mem_dma_buffer_dma;
  59         struct semaphore mem_dma_mutex;
  60         wait_queue_head_t mem_dma_intr_wait;
  61 #endif
  62
  63         /*
  64          * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for
  65          * LOCALRAM_SIZE * 8 PCLs (each sized 128 bytes);
  66          * the following is an allocation bitmap
  67          */
  68         u8 pcl_bmap[LOCALRAM_SIZE / 1024];
  69
  70 #ifndef CONFIG_IEEE1394_PCILYNX_LOCALRAM
  71         /* point to PCLs memory area if needed */
  72         void *pcl_mem;
  73         dma_addr_t pcl_mem_dma;
  74 #endif
  75
  76         /* PCLs for local mem / aux transfers */
  77         pcl_t dmem_pcl;
  78
  79         /* IEEE-1394 part follows */
  80         struct hpsb_host *host;
  81
  82         int phyid, isroot;
  83
  84         spinlock_t phy_reg_lock;
  85
  86         pcl_t rcv_pcl_start, rcv_pcl;
  87         void *rcv_page;
  88         dma_addr_t rcv_page_dma;
  89         int rcv_active;
  90
  91         struct {
  92                 pcl_t pcl_start, pcl;
  93                 struct hpsb_packet *queue;
  94                 spinlock_t queue_lock;
  95                 dma_addr_t header_dma, data_dma;
  96         } async;
  97
  98         struct {
  99                 pcl_t pcl[NUM_ISORCV_PCL];
 100                 u32 stat[NUM_ISORCV_PCL];
 101                 void *page[ISORCV_PAGES];
 102                 dma_addr_t page_dma[ISORCV_PAGES];
 103                 pcl_t pcl_start;
 104                 int chan_count;
 105                 int next, last, used, running;
 106                 struct tq_struct tq;
 107                 spinlock_t lock;
 108         } iso_rcv;
 109 };
 110
 111 /* the per-file data structure for mem space access */
 112 struct memdata {
 113         struct ti_lynx *lynx;
 114         int cid;
 115         atomic_t aux_intr_last_seen;
 116         enum { rom, aux, ram } type;
 117 };
 118
 119
 120
 121 /*
 122  * Register read and write helper functions.
 123  */
 124 inline static void reg_write(const struct ti_lynx *lynx, int offset, u32 data)
 125 {
 126         writel(data, lynx->registers + offset);
 127 }
 128
 129 inline static u32 reg_read(const struct ti_lynx *lynx, int offset)
 130 {
 131         return readl(lynx->registers + offset);
 132 }
 133
 134 inline static void reg_set_bits(const struct ti_lynx *lynx, int offset,
 135                                 u32 mask)
 136 {
 137         reg_write(lynx, offset, (reg_read(lynx, offset) | mask));
 138 }
 139
 140 inline static void reg_clear_bits(const struct ti_lynx *lynx, int offset,
 141                                   u32 mask)
 142 {
 143         reg_write(lynx, offset, (reg_read(lynx, offset) & ~mask));
 144 }
 145
 146
 147
 148 /* chip register definitions follow */
 149
 150 #define MISC_CONTROL                      0x40
 151 #define MISC_CONTROL_SWRESET              (1<<0)
 152
 153 #define PCI_INT_STATUS                    0x48
 154 #define PCI_INT_ENABLE                    0x4c
 155 /* status and enable have identical bit numbers */
 156 #define PCI_INT_INT_PEND                  (1<<31)
 157 #define PCI_INT_FORCED_INT                (1<<30)
 158 #define PCI_INT_SLV_ADR_PERR              (1<<28)
 159 #define PCI_INT_SLV_DAT_PERR              (1<<27)
 160 #define PCI_INT_MST_DAT_PERR              (1<<26)
 161 #define PCI_INT_MST_DEV_TIMEOUT           (1<<25)
 162 #define PCI_INT_INTERNAL_SLV_TIMEOUT      (1<<23)
 163 #define PCI_INT_AUX_TIMEOUT               (1<<18)
 164 #define PCI_INT_AUX_INT                   (1<<17)
 165 #define PCI_INT_1394                      (1<<16)
 166 #define PCI_INT_DMA4_PCL                  (1<<9)
 167 #define PCI_INT_DMA4_HLT                  (1<<8)
 168 #define PCI_INT_DMA3_PCL                  (1<<7)
 169 #define PCI_INT_DMA3_HLT                  (1<<6)
 170 #define PCI_INT_DMA2_PCL                  (1<<5)
 171 #define PCI_INT_DMA2_HLT                  (1<<4)
 172 #define PCI_INT_DMA1_PCL                  (1<<3)
 173 #define PCI_INT_DMA1_HLT                  (1<<2)
 174 #define PCI_INT_DMA0_PCL                  (1<<1)
 175 #define PCI_INT_DMA0_HLT                  (1<<0)
 176 /* all DMA interrupts combined: */
 177 #define PCI_INT_DMA_ALL                   0x3ff
 178
 179 #define PCI_INT_DMA_HLT(chan)             (1 << (chan * 2))
 180 #define PCI_INT_DMA_PCL(chan)             (1 << (chan * 2 + 1))
 181
 182 #define LBUS_ADDR                         0xb4
 183 #define LBUS_ADDR_SEL_RAM                 (0x0<<16)
 184 #define LBUS_ADDR_SEL_ROM                 (0x1<<16)
 185 #define LBUS_ADDR_SEL_AUX                 (0x2<<16)
 186 #define LBUS_ADDR_SEL_ZV                  (0x3<<16)
 187
 188 #define GPIO_CTRL_A                       0xb8
 189 #define GPIO_CTRL_B                       0xbc
 190 #define GPIO_DATA_BASE                    0xc0
 191
 192 #define DMA_BREG(base, chan)              (base + chan * 0x20)
 193 #define DMA_SREG(base, chan)              (base + chan * 0x10)
 194
 195 #define DMA0_PREV_PCL                     0x100
 196 #define DMA1_PREV_PCL                     0x120
 197 #define DMA2_PREV_PCL                     0x140
 198 #define DMA3_PREV_PCL                     0x160
 199 #define DMA4_PREV_PCL                     0x180
 200 #define DMA_PREV_PCL(chan)                (DMA_BREG(DMA0_PREV_PCL, chan))
 201
 202 #define DMA0_CURRENT_PCL                  0x104
 203 #define DMA1_CURRENT_PCL                  0x124
 204 #define DMA2_CURRENT_PCL                  0x144
 205 #define DMA3_CURRENT_PCL                  0x164
 206 #define DMA4_CURRENT_PCL                  0x184
 207 #define DMA_CURRENT_PCL(chan)             (DMA_BREG(DMA0_CURRENT_PCL, chan))
 208
 209 #define DMA0_CHAN_STAT                    0x10c
 210 #define DMA1_CHAN_STAT                    0x12c
 211 #define DMA2_CHAN_STAT                    0x14c
 212 #define DMA3_CHAN_STAT                    0x16c
 213 #define DMA4_CHAN_STAT                    0x18c
 214 #define DMA_CHAN_STAT(chan)               (DMA_BREG(DMA0_CHAN_STAT, chan))
 215 /* CHAN_STATUS registers share bits */
 216 #define DMA_CHAN_STAT_SELFID              (1<<31)
 217 #define DMA_CHAN_STAT_ISOPKT              (1<<30)
 218 #define DMA_CHAN_STAT_PCIERR              (1<<29)
 219 #define DMA_CHAN_STAT_PKTERR              (1<<28)
 220 #define DMA_CHAN_STAT_PKTCMPL             (1<<27)
 221 #define DMA_CHAN_STAT_SPECIALACK          (1<<14)
 222
 223
 224 #define DMA0_CHAN_CTRL                    0x110
 225 #define DMA1_CHAN_CTRL                    0x130
 226 #define DMA2_CHAN_CTRL                    0x150
 227 #define DMA3_CHAN_CTRL                    0x170
 228 #define DMA4_CHAN_CTRL                    0x190
 229 #define DMA_CHAN_CTRL(chan)               (DMA_BREG(DMA0_CHAN_CTRL, chan))
 230 /* CHAN_CTRL registers share bits */
 231 #define DMA_CHAN_CTRL_ENABLE              (1<<31)
 232 #define DMA_CHAN_CTRL_BUSY                (1<<30)
 233 #define DMA_CHAN_CTRL_LINK                (1<<29)
 234
 235 #define DMA0_READY                        0x114
 236 #define DMA1_READY                        0x134
 237 #define DMA2_READY                        0x154
 238 #define DMA3_READY                        0x174
 239 #define DMA4_READY                        0x194
 240 #define DMA_READY(chan)                   (DMA_BREG(DMA0_READY, chan))
 241
 242 #define DMA_GLOBAL_REGISTER               0x908
 243
 244 #define FIFO_SIZES                        0xa00
 245
 246 #define FIFO_CONTROL                      0xa10
 247 #define GRF_FLUSH                         (1<<4)
 248 #define ITF_FLUSH                         (1<<3)
 249 #define ATF_FLUSH                         (1<<2)
 250
 251 #define FIFO_XMIT_THRESHOLD               0xa14
 252
 253 #define DMA0_WORD0_CMP_VALUE              0xb00
 254 #define DMA1_WORD0_CMP_VALUE              0xb10
 255 #define DMA2_WORD0_CMP_VALUE              0xb20
 256 #define DMA3_WORD0_CMP_VALUE              0xb30
 257 #define DMA4_WORD0_CMP_VALUE              0xb40
 258 #define DMA_WORD0_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan))
 259
 260 #define DMA0_WORD0_CMP_ENABLE             0xb04
 261 #define DMA1_WORD0_CMP_ENABLE             0xb14
 262 #define DMA2_WORD0_CMP_ENABLE             0xb24
 263 #define DMA3_WORD0_CMP_ENABLE             0xb34
 264 #define DMA4_WORD0_CMP_ENABLE             0xb44
 265 #define DMA_WORD0_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD0_CMP_ENABLE,chan))
 266
 267 #define DMA0_WORD1_CMP_VALUE              0xb08
 268 #define DMA1_WORD1_CMP_VALUE              0xb18
 269 #define DMA2_WORD1_CMP_VALUE              0xb28
 270 #define DMA3_WORD1_CMP_VALUE              0xb38
 271 #define DMA4_WORD1_CMP_VALUE              0xb48
 272 #define DMA_WORD1_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan))
 273
 274 #define DMA0_WORD1_CMP_ENABLE             0xb0c
 275 #define DMA1_WORD1_CMP_ENABLE             0xb1c
 276 #define DMA2_WORD1_CMP_ENABLE             0xb2c
 277 #define DMA3_WORD1_CMP_ENABLE             0xb3c
 278 #define DMA4_WORD1_CMP_ENABLE             0xb4c
 279 #define DMA_WORD1_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD1_CMP_ENABLE,chan))
 280 /* word 1 compare enable flags */
 281 #define DMA_WORD1_CMP_MATCH_OTHERBUS      (1<<15)
 282 #define DMA_WORD1_CMP_MATCH_BROADCAST     (1<<14)
 283 #define DMA_WORD1_CMP_MATCH_BUS_BCAST     (1<<13)
 284 #define DMA_WORD1_CMP_MATCH_NODE_BCAST    (1<<12)
 285 #define DMA_WORD1_CMP_MATCH_LOCAL         (1<<11)
 286 #define DMA_WORD1_CMP_ENABLE_SELF_ID      (1<<10)
 287 #define DMA_WORD1_CMP_ENABLE_MASTER       (1<<8)
 288
 289 #define LINK_ID                           0xf00
 290 #define LINK_ID_BUS(id)                   (id<<22)
 291 #define LINK_ID_NODE(id)                  (id<<16)
 292
 293 #define LINK_CONTROL                      0xf04
 294 #define LINK_CONTROL_BUSY                 (1<<29)
 295 #define LINK_CONTROL_TX_ISO_EN            (1<<26)
 296 #define LINK_CONTROL_RX_ISO_EN            (1<<25)
 297 #define LINK_CONTROL_TX_ASYNC_EN          (1<<24)
 298 #define LINK_CONTROL_RX_ASYNC_EN          (1<<23)
 299 #define LINK_CONTROL_RESET_TX             (1<<21)
 300 #define LINK_CONTROL_RESET_RX             (1<<20)
 301 #define LINK_CONTROL_CYCMASTER            (1<<11)
 302 #define LINK_CONTROL_CYCSOURCE            (1<<10)
 303 #define LINK_CONTROL_CYCTIMEREN           (1<<9)
 304 #define LINK_CONTROL_RCV_CMP_VALID        (1<<7)
 305 #define LINK_CONTROL_SNOOP_ENABLE         (1<<6)
 306
 307 #define CYCLE_TIMER                       0xf08
 308
 309 #define LINK_PHY                          0xf0c
 310 #define LINK_PHY_READ                     (1<<31)
 311 #define LINK_PHY_WRITE                    (1<<30)
 312 #define LINK_PHY_ADDR(addr)               (addr<<24)
 313 #define LINK_PHY_WDATA(data)              (data<<16)
 314 #define LINK_PHY_RADDR(addr)              (addr<<8)
 315
 316
 317 #define LINK_INT_STATUS                   0xf14
 318 #define LINK_INT_ENABLE                   0xf18
 319 /* status and enable have identical bit numbers */
 320 #define LINK_INT_LINK_INT                 (1<<31)
 321 #define LINK_INT_PHY_TIMEOUT              (1<<30)
 322 #define LINK_INT_PHY_REG_RCVD             (1<<29)
 323 #define LINK_INT_PHY_BUSRESET             (1<<28)
 324 #define LINK_INT_TX_RDY                   (1<<26)
 325 #define LINK_INT_RX_DATA_RDY              (1<<25)
 326 #define LINK_INT_ISO_STUCK                (1<<20)
 327 #define LINK_INT_ASYNC_STUCK              (1<<19)
 328 #define LINK_INT_SENT_REJECT              (1<<17)
 329 #define LINK_INT_HDR_ERR                  (1<<16)
 330 #define LINK_INT_TX_INVALID_TC            (1<<15)
 331 #define LINK_INT_CYC_SECOND               (1<<11)
 332 #define LINK_INT_CYC_START                (1<<10)
 333 #define LINK_INT_CYC_DONE                 (1<<9)
 334 #define LINK_INT_CYC_PENDING              (1<<8)
 335 #define LINK_INT_CYC_LOST                 (1<<7)
 336 #define LINK_INT_CYC_ARB_FAILED           (1<<6)
 337 #define LINK_INT_GRF_OVERFLOW             (1<<5)
 338 #define LINK_INT_ITF_UNDERFLOW            (1<<4)
 339 #define LINK_INT_ATF_UNDERFLOW            (1<<3)
 340 #define LINK_INT_ISOARB_FAILED            (1<<0)
 341
 342 /* PHY specifics */
 343 #define PHY_VENDORID_TI                 0x800028
 344 #define PHY_PRODUCTID_TSB41LV03         0x000000
 345
 346
 347 /* this is the physical layout of a PCL, its size is 128 bytes */
 348 struct ti_pcl {
 349         u32 next;
 350         u32 async_error_next;
 351         u32 user_data;
 352         u32 pcl_status;
 353         u32 remaining_transfer_count;
 354         u32 next_data_buffer;
 355         struct {
 356                 u32 control;
 357                 u32 pointer;
 358         } buffer[13] __attribute__ ((packed));
 359 } __attribute__ ((packed));
 360
 361 #include <linux/stddef.h>
 362 #define pcloffs(MEMBER) (offsetof(struct ti_pcl, MEMBER))
 363
 364
 365 #ifdef CONFIG_IEEE1394_PCILYNX_LOCALRAM
 366
 367 inline static void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 368                            const struct ti_pcl *pcl)
 369 {
 370         int i;
 371         u32 *in = (u32 *)pcl;
 372         u32 *out = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));
 373
 374         for (i = 0; i < 32; i++, out++, in++) {
 375                 writel(cpu_to_le32(*in), out);
 376         }
 377 }
 378
 379 inline static void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 380                            struct ti_pcl *pcl)
 381 {
 382         int i;
 383         u32 *out = (u32 *)pcl;
 384         u32 *in = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));
 385
 386         for (i = 0; i < 32; i++, out++, in++) {
 387                 *out = le32_to_cpu(readl(in));
 388         }
 389 }
 390
 391 inline static u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
 392 {
 393         return pci_resource_start(lynx->dev, 1) + pclid * sizeof(struct ti_pcl);
 394 }
 395
 396 #else /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */
 397
 398 inline static void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 399                            const struct ti_pcl *pcl)
 400 {
 401         memcpy_le32((u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
 402                     (u32 *)pcl, sizeof(struct ti_pcl));
 403 }
 404
 405 inline static void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 406                            struct ti_pcl *pcl)
 407 {
 408         memcpy_le32((u32 *)pcl,
 409                     (u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
 410                     sizeof(struct ti_pcl));
 411 }
 412
 413 inline static u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
 414 {
 415         return lynx->pcl_mem_dma + pclid * sizeof(struct ti_pcl);
 416 }
 417
 418 #endif /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */
 419
 420
 421 #if defined (CONFIG_IEEE1394_PCILYNX_LOCALRAM) || defined (__BIG_ENDIAN)
 422 typedef struct ti_pcl pcltmp_t;
 423
 424 inline static struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 425                                       pcltmp_t *tmp)
 426 {
 427         get_pcl(lynx, pclid, tmp);
 428         return tmp;
 429 }
 430
 431 inline static void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 432                               pcltmp_t *tmp)
 433 {
 434         put_pcl(lynx, pclid, tmp);
 435 }
 436
 437 #else
 438 typedef int pcltmp_t; /* just a dummy */
 439
 440 inline static struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 441                                       pcltmp_t *tmp)
 442 {
 443         return lynx->pcl_mem + pclid * sizeof(struct ti_pcl);
 444 }
 445
 446 inline static void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 447                               pcltmp_t *tmp)
 448 {
 449 }
 450 #endif
 451
 452
 453 inline static void run_sub_pcl(const struct ti_lynx *lynx, pcl_t pclid, int idx,
 454                                int dmachan)
 455 {
 456         reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20,
 457                   pcl_bus(lynx, pclid) + idx * 4);
 458         reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20,
 459                   DMA_CHAN_CTRL_ENABLE | DMA_CHAN_CTRL_LINK);
 460 }
 461
 462 inline static void run_pcl(const struct ti_lynx *lynx, pcl_t pclid, int dmachan)
 463 {
 464         run_sub_pcl(lynx, pclid, 0, dmachan);
 465 }
 466
 467 #define PCL_NEXT_INVALID (1<<0)
 468
 469 /* transfer commands */
 470 #define PCL_CMD_RCV            (0x1<<24)
 471 #define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
 472 #define PCL_CMD_XMT            (0x2<<24)
 473 #define PCL_CMD_UNFXMT         (0xc<<24)
 474 #define PCL_CMD_PCI_TO_LBUS    (0x8<<24)
 475 #define PCL_CMD_LBUS_TO_PCI    (0x9<<24)
 476
 477 /* aux commands */
 478 #define PCL_CMD_NOP            (0x0<<24)
 479 #define PCL_CMD_LOAD           (0x3<<24)
 480 #define PCL_CMD_STOREQ         (0x4<<24)
 481 #define PCL_CMD_STORED         (0xb<<24)
 482 #define PCL_CMD_STORE0         (0x5<<24)
 483 #define PCL_CMD_STORE1         (0x6<<24)
 484 #define PCL_CMD_COMPARE        (0xe<<24)
 485 #define PCL_CMD_SWAP_COMPARE   (0xf<<24)
 486 #define PCL_CMD_ADD            (0xd<<24)
 487 #define PCL_CMD_BRANCH         (0x7<<24)
 488
 489 /* BRANCH condition codes */
 490 #define PCL_COND_DMARDY_SET    (0x1<<20)
 491 #define PCL_COND_DMARDY_CLEAR  (0x2<<20)
 492
 493 #define PCL_GEN_INTR           (1<<19)
 494 #define PCL_LAST_BUFF          (1<<18)
 495 #define PCL_LAST_CMD           (PCL_LAST_BUFF)
 496 #define PCL_WAITSTAT           (1<<17)
 497 #define PCL_BIGENDIAN          (1<<16)
 498
 499
 500 #define _(x) (__constant_cpu_to_be32(x))
 501
 502 static quadlet_t lynx_csr_rom[] = {
 503 /* bus info block     offset (hex) */
 504         _(0x04040000), /* info/CRC length, CRC              400  */
 505         _(0x31333934), /* 1394 magic number                 404  */
 506         _(0xf064a000), /* misc. settings                    408  */
 507         _(0x08002850), /* vendor ID, chip ID high           40c  */
 508         _(0x0000ffff), /* chip ID low                       410  */
 509 /* root directory */
 510         _(0x00090000), /* directory length, CRC             414  */
 511         _(0x03080028), /* vendor ID (Texas Instr.)          418  */
 512         _(0x81000008), /* offset to textual ID              41c  */
 513         _(0x0c000200), /* node capabilities                 420  */
 514         _(0x8d00000e), /* offset to unique ID               424  */
 515         _(0xc7000010), /* offset to module independent info 428  */
 516         _(0x04000000), /* module hardware version           42c  */
 517         _(0x81000014), /* offset to textual ID              430  */
 518         _(0x09000000), /* node hardware version             434  */
 519         _(0x81000018), /* offset to textual ID              438  */
 520   /* module vendor ID textual */
 521         _(0x00070000), /* CRC length, CRC                   43c  */
 522         _(0x00000000), /*                                   440  */
 523         _(0x00000000), /*                                   444  */
 524         _(0x54455841), /* "Texas Instruments"               448  */
 525         _(0x5320494e), /*                                   44c  */
 526         _(0x53545255), /*                                   450  */
 527         _(0x4d454e54), /*                                   454  */
 528         _(0x53000000), /*                                   458  */
 529 /* node unique ID leaf */
 530         _(0x00020000), /* CRC length, CRC                   45c  */
 531         _(0x08002850), /* vendor ID, chip ID high           460  */
 532         _(0x0000ffff), /* chip ID low                       464  */
 533 /* module dependent info */
 534         _(0x00050000), /* CRC length, CRC                   468  */
 535         _(0x81000012), /* offset to module textual ID       46c  */
 536         _(0x81000017), /* textual descriptor                470  */
 537         _(0x39010000), /* SRAM size                         474  */
 538         _(0x3a010000), /* AUXRAM size                       478  */
 539         _(0x3b000000), /* AUX device                        47c  */
 540 /* module textual ID */
 541         _(0x00050000), /* CRC length, CRC                   480  */
 542         _(0x00000000), /*                                   484  */
 543         _(0x00000000), /*                                   488  */
 544         _(0x54534231), /* "TSB12LV21"                       48c  */
 545         _(0x324c5632), /*                                   490  */
 546         _(0x31000000), /*                                   494  */
 547 /* part number */
 548         _(0x00060000), /* CRC length, CRC                   498  */
 549         _(0x00000000), /*                                   49c  */
 550         _(0x00000000), /*                                   4a0  */
 551         _(0x39383036), /* "9806000-0001"                    4a4  */
 552         _(0x3030302d), /*                                   4a8  */
 553         _(0x30303031), /*                                   4ac  */
 554         _(0x20000001), /*                                   4b0  */
 555 /* module hardware version textual */
 556         _(0x00050000), /* CRC length, CRC                   4b4  */
 557         _(0x00000000), /*                                   4b8  */
 558         _(0x00000000), /*                                   4bc  */
 559         _(0x5453424b), /* "TSBKPCITST"                      4c0  */
 560         _(0x50434954), /*                                   4c4  */
 561         _(0x53540000), /*                                   4c8  */
 562 /* node hardware version textual */
 563         _(0x00050000), /* CRC length, CRC                   4d0  */
 564         _(0x00000000), /*                                   4d4  */
 565         _(0x00000000), /*                                   4d8  */
 566         _(0x54534232), /* "TSB21LV03"                       4dc  */
 567         _(0x314c5630), /*                                   4e0  */
 568         _(0x33000000)  /*                                   4e4  */
 569 };
 570
 571 #undef _