drivers/ieee1394/ohci1394.h

   1 /*
   2  * ohci1394.h - driver for OHCI 1394 boards
   3  * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
   4  *                        Gord Peters <GordPeters@smarttech.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #ifndef _OHCI1394_H
  22 #define _OHCI1394_H
  23
  24 #include "ieee1394_types.h"
  25
  26 #define IEEE1394_USE_BOTTOM_HALVES 0
  27
  28 #define OHCI1394_DRIVER_NAME      "ohci1394"
  29
  30 #ifndef PCI_DEVICE_ID_TI_OHCI1394_LV22
  31 #define PCI_DEVICE_ID_TI_OHCI1394_LV22 0x8009
  32 #endif
  33
  34 #ifndef PCI_DEVICE_ID_TI_OHCI1394_LV23
  35 #define PCI_DEVICE_ID_TI_OHCI1394_LV23 0x8019
  36 #endif
  37
  38 #ifndef PCI_DEVICE_ID_TI_OHCI1394_LV26
  39 #define PCI_DEVICE_ID_TI_OHCI1394_LV26 0x8020
  40 #endif
  41
  42 #ifndef PCI_DEVICE_ID_VIA_OHCI1394
  43 #define PCI_DEVICE_ID_VIA_OHCI1394 0x3044
  44 #endif
  45
  46 #ifndef PCI_VENDOR_ID_SONY
  47 #define PCI_VENDOR_ID_SONY 0x104d
  48 #endif
  49
  50 #ifndef PCI_DEVICE_ID_SONY_CXD3222
  51 #define PCI_DEVICE_ID_SONY_CXD3222 0x8039
  52 #endif
  53
  54 #ifndef PCI_DEVICE_ID_NEC_1394
  55 #define PCI_DEVICE_ID_NEC_1394 0x00cd
  56 #endif
  57
  58 #ifndef PCI_DEVICE_ID_NEC_UPD72862
  59 #define PCI_DEVICE_ID_NEC_UPD72862      0x0063
  60 #endif
  61
  62 #ifndef PCI_DEVICE_ID_NEC_UPD72870
  63 #define PCI_DEVICE_ID_NEC_UPD72870      0x00cd
  64 #endif
  65
  66 #ifndef PCI_DEVICE_ID_NEC_UPD72871
  67 #define PCI_DEVICE_ID_NEC_UPD72871      0x00ce
  68 #endif
  69
  70 #ifndef PCI_DEVICE_ID_APPLE_UNI_N_FW
  71 #define PCI_DEVICE_ID_APPLE_UNI_N_FW    0x0018
  72 #endif
  73
  74 #ifndef PCI_DEVICE_ID_ALI_OHCI1394_M5251
  75 #define PCI_DEVICE_ID_ALI_OHCI1394_M5251 0x5251
  76 #endif
  77
  78 #ifndef PCI_VENDOR_ID_LUCENT
  79 #define PCI_VENDOR_ID_LUCENT 0x11c1
  80 #endif
  81
  82 #ifndef PCI_DEVICE_ID_LUCENT_FW323
  83 #define PCI_DEVICE_ID_LUCENT_FW323 0x5811
  84 #endif
  85
  86 #define MAX_OHCI1394_CARDS        4
  87
  88 #define OHCI1394_MAX_AT_REQ_RETRIES       0x2
  89 #define OHCI1394_MAX_AT_RESP_RETRIES      0x2
  90 #define OHCI1394_MAX_PHYS_RESP_RETRIES    0x8
  91 #define OHCI1394_MAX_SELF_ID_ERRORS       16
  92
  93 #define AR_REQ_NUM_DESC                   4 /* number of AR req descriptors */
  94 #define AR_REQ_BUF_SIZE                4096 /* size of AR req buffers */
  95 #define AR_REQ_SPLIT_BUF_SIZE          4096 /* split packet buffer */
  96
  97 #define AR_RESP_NUM_DESC                  4 /* number of AR resp descriptors */
  98 #define AR_RESP_BUF_SIZE               4096 /* size of AR resp buffers */
  99 #define AR_RESP_SPLIT_BUF_SIZE         4096 /* split packet buffer */
 100
 101 #define IR_NUM_DESC                      16 /* number of IR descriptors */
 102 #define IR_BUF_SIZE                    4096 /* 6480 bytes/buffer */
 103 #define IR_SPLIT_BUF_SIZE              4096 /* split packet buffer */
 104
 105 #define AT_REQ_NUM_DESC                  32 /* number of AT req descriptors */
 106 #define AT_RESP_NUM_DESC                 32 /* number of AT resp descriptors */
 107
 108 struct dma_cmd {
 109         u32 control;
 110         u32 address;
 111         u32 branchAddress;
 112         u32 status;
 113 };
 114
 115 struct at_dma_prg {
 116         struct dma_cmd begin;
 117         quadlet_t data[4];
 118         struct dma_cmd end;
 119 };
 120
 121 /* DMA receive context */
 122 struct dma_rcv_ctx {
 123         void *ohci;
 124         int ctx;
 125         unsigned int num_desc;
 126         unsigned int buf_size;
 127         unsigned int split_buf_size;
 128
 129         /* dma block descriptors */
 130         struct dma_cmd **prg_cpu;
 131         dma_addr_t *prg_bus;
 132
 133         /* dma buffers */
 134         quadlet_t **buf_cpu;
 135         dma_addr_t *buf_bus;
 136
 137         unsigned int buf_ind;
 138         unsigned int buf_offset;
 139         quadlet_t *spb;
 140         spinlock_t lock;
 141         struct tq_struct task;
 142         int ctrlClear;
 143         int ctrlSet;
 144         int cmdPtr;
 145 };
 146
 147 /* DMA transmit context */
 148 struct dma_trm_ctx {
 149         void *ohci;
 150         int ctx;
 151         unsigned int num_desc;
 152
 153         /* dma block descriptors */
 154         struct at_dma_prg **prg_cpu;
 155         dma_addr_t *prg_bus;
 156
 157         unsigned int prg_ind;
 158         unsigned int sent_ind;
 159         int free_prgs;
 160         quadlet_t *branchAddrPtr;
 161
 162         /* list of packets inserted in the AT FIFO */
 163         struct hpsb_packet *fifo_first;
 164         struct hpsb_packet *fifo_last;
 165
 166         /* list of pending packets to be inserted in the AT FIFO */
 167         struct hpsb_packet *pending_first;
 168         struct hpsb_packet *pending_last;
 169
 170         spinlock_t lock;
 171         struct tq_struct task;
 172         int ctrlClear;
 173         int ctrlSet;
 174         int cmdPtr;
 175 };
 176
 177 /* video device template */
 178 struct video_template {
 179         void (*irq_handler) (int card, quadlet_t isoRecvEvent,
 180                              quadlet_t isoXmitEvent);
 181 };
 182
 183
 184 struct ti_ohci {
 185         int id; /* sequential card number */
 186
 187         struct pci_dev *dev;
 188
 189         u32 state;
 190
 191         /* remapped memory spaces */
 192         void *registers;
 193
 194         /* dma buffer for self-id packets */
 195         quadlet_t *selfid_buf_cpu;
 196         dma_addr_t selfid_buf_bus;
 197
 198         /* buffer for csr config rom */
 199         quadlet_t *csr_config_rom_cpu;
 200         dma_addr_t csr_config_rom_bus;
 201
 202         unsigned int max_packet_size;
 203
 204         /* async receive */
 205         struct dma_rcv_ctx *ar_resp_context;
 206         struct dma_rcv_ctx *ar_req_context;
 207
 208         /* async transmit */
 209         struct dma_trm_ctx *at_resp_context;
 210         struct dma_trm_ctx *at_req_context;
 211
 212         /* iso receive */
 213         struct dma_rcv_ctx *ir_context;
 214         u64 IR_channel_usage;
 215         spinlock_t IR_channel_lock;
 216         int nb_iso_rcv_ctx;
 217
 218         /* iso transmit */
 219         int nb_iso_xmit_ctx;
 220
 221         /* IEEE-1394 part follows */
 222         struct hpsb_host *host;
 223
 224         int phyid, isroot;
 225
 226         spinlock_t phy_reg_lock;
 227
 228         int self_id_errors;
 229         int NumBusResets;
 230
 231         /* video device */
 232         struct video_template *video_tmpl;
 233 };
 234
 235 inline static int cross_bound(unsigned long addr, unsigned int size)
 236 {
 237         int cross=0;
 238         if (size>PAGE_SIZE) {
 239                 cross = size/PAGE_SIZE;
 240                 size -= cross*PAGE_SIZE;
 241         }
 242         if ((PAGE_SIZE-addr%PAGE_SIZE)<size)
 243                 cross++;
 244         return cross;
 245 }
 246
 247 /*
 248  * Register read and write helper functions.
 249  */
 250 inline static void reg_write(const struct ti_ohci *ohci, int offset, u32 data)
 251 {
 252         writel(data, ohci->registers + offset);
 253 }
 254
 255 inline static u32 reg_read(const struct ti_ohci *ohci, int offset)
 256 {
 257         return readl(ohci->registers + offset);
 258 }
 259
 260 /* This structure is not properly initialized ... it is taken from
 261    the lynx_csr_rom written by Andreas ... Some fields in the root
 262    directory and the module dependent info needs to be modified
 263    I do not have the proper doc */
 264 quadlet_t ohci_csr_rom[] = {
 265         /* bus info block */
 266         0x04040000, /* info/CRC length, CRC */
 267         0x31333934, /* 1394 magic number */
 268         0xf07da002, /* cyc_clk_acc = 125us, max_rec = 1024 */
 269         0x00000000, /* vendor ID, chip ID high (written from card info) */
 270         0x00000000, /* chip ID low (written from card info) */
 271         /* root directory - FIXME */
 272         0x00090000, /* CRC length, CRC */
 273         0x03080028, /* vendor ID (Texas Instr.) */
 274         0x81000009, /* offset to textual ID */
 275         0x0c000200, /* node capabilities */
 276         0x8d00000e, /* offset to unique ID */
 277         0xc7000010, /* offset to module independent info */
 278         0x04000000, /* module hardware version */
 279         0x81000026, /* offset to textual ID */
 280         0x09000000, /* node hardware version */
 281         0x81000026, /* offset to textual ID */
 282         /* module vendor ID textual */
 283         0x00080000, /* CRC length, CRC */
 284         0x00000000,
 285         0x00000000,
 286         0x54455841, /* "Texas Instruments" */
 287         0x5320494e,
 288         0x53545255,
 289         0x4d454e54,
 290         0x53000000,
 291         /* node unique ID leaf */
 292         0x00020000, /* CRC length, CRC */
 293         0x08002856, /* vendor ID, chip ID high */
 294         0x0000083E, /* chip ID low */
 295         /* module dependent info - FIXME */
 296         0x00060000, /* CRC length, CRC */
 297         0xb8000006, /* ??? offset to module textual ID */
 298         0x81000004, /* ??? textual descriptor */
 299         0x00000000, /* SRAM size */
 300         0x00000000, /* AUXRAM size */
 301         0x00000000, /* AUX device */
 302         /* module textual ID */
 303         0x00050000, /* CRC length, CRC */
 304         0x00000000,
 305         0x00000000,
 306         0x54534231, /* "TSB12LV22" */
 307         0x324c5632,
 308         0x32000000,
 309         /* part number */
 310         0x00060000, /* CRC length, CRC */
 311         0x00000000,
 312         0x00000000,
 313         0x39383036, /* "9806000-0001" */
 314         0x3030342d,
 315         0x30303431,
 316         0x20000001,
 317         /* module hardware version textual */
 318         0x00050000, /* CRC length, CRC */
 319         0x00000000,
 320         0x00000000,
 321         0x5453424b, /* "TSBKOHCI403" */
 322         0x4f484349,
 323         0x34303300,
 324         /* node hardware version textual */
 325         0x00050000, /* CRC length, CRC */
 326         0x00000000,
 327         0x00000000,
 328         0x54534234, /* "TSB41LV03" */
 329         0x314c5630,
 330         0x33000000
 331 };
 332
 333
 334 /* 2 KiloBytes of register space */
 335 #define OHCI1394_REGISTER_SIZE                0x800
 336
 337 /* register map */
 338 #define OHCI1394_Version                      0x000
 339 #define OHCI1394_GUID_ROM                     0x004
 340 #define OHCI1394_ATRetries                    0x008
 341 #define OHCI1394_CSRData                      0x00C
 342 #define OHCI1394_CSRCompareData               0x010
 343 #define OHCI1394_CSRControl                   0x014
 344 #define OHCI1394_ConfigROMhdr                 0x018
 345 #define OHCI1394_BusID                        0x01C
 346 #define OHCI1394_BusOptions                   0x020
 347 #define OHCI1394_GUIDHi                       0x024
 348 #define OHCI1394_GUIDLo                       0x028
 349 #define OHCI1394_ConfigROMmap                 0x034
 350 #define OHCI1394_PostedWriteAddressLo         0x038
 351 #define OHCI1394_PostedWriteAddressHi         0x03C
 352 #define OHCI1394_VendorID                     0x040
 353 #define OHCI1394_HCControlSet                 0x050
 354 #define OHCI1394_HCControlClear               0x054
 355 #define OHCI1394_SelfIDBuffer                 0x064
 356 #define OHCI1394_SelfIDCount                  0x068
 357 #define OHCI1394_IRMultiChanMaskHiSet         0x070
 358 #define OHCI1394_IRMultiChanMaskHiClear       0x074
 359 #define OHCI1394_IRMultiChanMaskLoSet         0x078
 360 #define OHCI1394_IRMultiChanMaskLoClear       0x07C
 361 #define OHCI1394_IntEventSet                  0x080
 362 #define OHCI1394_IntEventClear                0x084
 363 #define OHCI1394_IntMaskSet                   0x088
 364 #define OHCI1394_IntMaskClear                 0x08C
 365 #define OHCI1394_IsoXmitIntEventSet           0x090
 366 #define OHCI1394_IsoXmitIntEventClear         0x094
 367 #define OHCI1394_IsoXmitIntMaskSet            0x098
 368 #define OHCI1394_IsoXmitIntMaskClear          0x09C
 369 #define OHCI1394_IsoRecvIntEventSet           0x0A0
 370 #define OHCI1394_IsoRecvIntEventClear         0x0A4
 371 #define OHCI1394_IsoRecvIntMaskSet            0x0A8
 372 #define OHCI1394_IsoRecvIntMaskClear          0x0AC
 373 #define OHCI1394_FairnessControl              0x0DC
 374 #define OHCI1394_LinkControlSet               0x0E0
 375 #define OHCI1394_LinkControlClear             0x0E4
 376 #define OHCI1394_NodeID                       0x0E8
 377 #define OHCI1394_PhyControl                   0x0EC
 378 #define OHCI1394_IsochronousCycleTimer        0x0F0
 379 #define OHCI1394_AsReqFilterHiSet             0x100
 380 #define OHCI1394_AsReqFilterHiClear           0x104
 381 #define OHCI1394_AsReqFilterLoSet             0x108
 382 #define OHCI1394_AsReqFilterLoClear           0x10C
 383 #define OHCI1394_PhyReqFilterHiSet            0x110
 384 #define OHCI1394_PhyReqFilterHiClear          0x114
 385 #define OHCI1394_PhyReqFilterLoSet            0x118
 386 #define OHCI1394_PhyReqFilterLoClear          0x11C
 387 #define OHCI1394_PhyUpperBound                0x120
 388 #define OHCI1394_AsReqTrContextControlSet     0x180
 389 #define OHCI1394_AsReqTrContextControlClear   0x184
 390 #define OHCI1394_AsReqTrCommandPtr            0x18C
 391 #define OHCI1394_AsRspTrContextControlSet     0x1A0
 392 #define OHCI1394_AsRspTrContextControlClear   0x1A4
 393 #define OHCI1394_AsRspTrCommandPtr            0x1AC
 394 #define OHCI1394_AsReqRcvContextControlSet    0x1C0
 395 #define OHCI1394_AsReqRcvContextControlClear  0x1C4
 396 #define OHCI1394_AsReqRcvCommandPtr           0x1CC
 397 #define OHCI1394_AsRspRcvContextControlSet    0x1E0
 398 #define OHCI1394_AsRspRcvContextControlClear  0x1E4
 399 #define OHCI1394_AsRspRcvCommandPtr           0x1EC
 400
 401 /* Isochronous transmit registers */
 402 /* Add (32 * n) for context n */
 403 #define OHCI1394_IsoXmitContextControlSet     0x200
 404 #define OHCI1394_IsoXmitContextControlClear   0x204
 405 #define OHCI1394_IsoXmitCommandPtr            0x20C
 406
 407 /* Isochronous receive registers */
 408 /* Add (32 * n) for context n */
 409 #define OHCI1394_IsoRcvContextControlSet      0x400
 410 #define OHCI1394_IsoRcvContextControlClear    0x404
 411 #define OHCI1394_IsoRcvCommandPtr             0x40C
 412 #define OHCI1394_IsoRcvContextMatch           0x410
 413
 414 /* Interrupts Mask/Events */
 415
 416 #define OHCI1394_reqTxComplete           0x00000001
 417 #define OHCI1394_respTxComplete          0x00000002
 418 #define OHCI1394_ARRQ                    0x00000004
 419 #define OHCI1394_ARRS                    0x00000008
 420 #define OHCI1394_RQPkt                   0x00000010
 421 #define OHCI1394_RSPkt                   0x00000020
 422 #define OHCI1394_isochTx                 0x00000040
 423 #define OHCI1394_isochRx                 0x00000080
 424 #define OHCI1394_postedWriteErr          0x00000100
 425 #define OHCI1394_lockRespErr             0x00000200
 426 #define OHCI1394_selfIDComplete          0x00010000
 427 #define OHCI1394_busReset                0x00020000
 428 #define OHCI1394_phy                     0x00080000
 429 #define OHCI1394_cycleSynch              0x00100000
 430 #define OHCI1394_cycle64Seconds          0x00200000
 431 #define OHCI1394_cycleLost               0x00400000
 432 #define OHCI1394_cycleInconsistent       0x00800000
 433 #define OHCI1394_unrecoverableError      0x01000000
 434 #define OHCI1394_cycleTooLong            0x02000000
 435 #define OHCI1394_phyRegRcvd              0x04000000
 436 #define OHCI1394_masterIntEnable         0x80000000
 437
 438 #define OUTPUT_MORE                      0x00000000
 439 #define OUTPUT_MORE_IMMEDIATE            0x02000000
 440 #define OUTPUT_LAST                      0x103c0000
 441 #define OUTPUT_LAST_IMMEDIATE            0x123c0000
 442
 443 #define DMA_SPEED_100                    0x0
 444 #define DMA_SPEED_200                    0x1
 445 #define DMA_SPEED_400                    0x2
 446
 447 void ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg);
 448 struct ti_ohci *ohci1394_get_struct(int card_num);
 449 int ohci1394_register_video(struct ti_ohci *ohci,
 450                             struct video_template *tmpl);
 451 void ohci1394_unregister_video(struct ti_ohci *ohci,
 452                                struct video_template *tmpl);
 453
 454 #endif
 455