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This is pre8 ...
[linux-2.6/linux-mips.git] / drivers / ieee1394 / ohci1394.c
blob05e1063d7595252e54986da39d68ba611c2096dc
1 /*
2 * ohci1394.c - driver for OHCI 1394 boards
3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4 * Gord Peters <GordPeters@smarttech.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 * Things known to be working:
23 * . Async Request Transmit
24 * . Async Response Receive
25 * . Async Request Receive
26 * . Async Response Transmit
27 * . Iso Receive
28 * . DMA mmap for iso receive
29 *
30 * Things not implemented:
31 * . Iso Transmit
32 * . DMA error recovery
33 *
34 * Things to be fixed:
35 * . Config ROM
36 *
37 * Known bugs:
38 * . Self-id are sometimes not received properly
39 * if card is initialized with no other nodes
40 * on the bus
41 * . Apple PowerBook detected but not working yet
42 */
43
44 /*
45 * Acknowledgments:
46 *
47 * Emilie Chung <emilie.chung@axis.com>
48 * . Tip on Async Request Filter
49 * Pascal Drolet <pascal.drolet@informission.ca>
50 * . Various tips for optimization and functionnalities
51 * Robert Ficklin <rficklin@westengineering.com>
52 * . Loop in irq_handler
53 * James Goodwin <jamesg@Filanet.com>
54 * . Various tips on initialization, self-id reception, etc.
55 * Albrecht Dress <ad@mpifr-bonn.mpg.de>
56 * . Apple PowerBook detection
57 * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de>
58 * . Reset the board properly before leaving + misc cleanups
59 */
60
61 #include <linux/config.h>
62 #include <linux/kernel.h>
63 #include <linux/slab.h>
64 #include <linux/interrupt.h>
65 #include <linux/wait.h>
66 #include <linux/errno.h>
67 #include <linux/module.h>
68 #include <linux/pci.h>
69 #include <linux/fs.h>
70 #include <linux/poll.h>
71 #include <asm/byteorder.h>
72 #include <asm/atomic.h>
73 #include <asm/io.h>
74 #include <asm/uaccess.h>
75 #include <linux/proc_fs.h>
76 #include <linux/tqueue.h>
77 #include <linux/delay.h>
78
79 #include <asm/pgtable.h>
80 #include <asm/page.h>
81 #include <linux/sched.h>
82 #include <asm/segment.h>
83 #include <linux/types.h>
84 #include <linux/wrapper.h>
85 #include <linux/vmalloc.h>
86
87 #include "ieee1394.h"
88 #include "ieee1394_types.h"
89 #include "hosts.h"
90 #include "ieee1394_core.h"
91 #include "ohci1394.h"
92
93 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
94 #define OHCI1394_DEBUG
95 #endif
96
97 #ifdef DBGMSG
98 #undef DBGMSG
99 #endif
100
101 #ifdef OHCI1394_DEBUG
102 #define DBGMSG(card, fmt, args...) \
103 printk(KERN_INFO "ohci1394_%d: " fmt "\n" , card , ## args)
104 #else
105 #define DBGMSG(card, fmt, args...)
106 #endif
107
108 /* print general (card independent) information */
109 #define PRINT_G(level, fmt, args...) \
110 printk(level "ohci1394: " fmt "\n" , ## args)
111
112 /* print card specific information */
113 #define PRINT(level, card, fmt, args...) \
114 printk(level "ohci1394_%d: " fmt "\n" , card , ## args)
115
116 #define FAIL(fmt, args...) \
117 PRINT_G(KERN_ERR, fmt , ## args); \
118 num_of_cards--; \
119 remove_card(ohci); \
120 return 1;
121
122 int supported_chips[][2] = {
123 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_OHCI1394_LV22 },
124 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_OHCI1394_LV23 },
125 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_OHCI1394_LV26 },
126 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_OHCI1394 },
127 { PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_CXD3222 },
128 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_UPD72862 },
129 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_UPD72870 },
130 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_UPD72871 },
131 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW },
132 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_ALI_OHCI1394_M5251 },
133 { PCI_VENDOR_ID_LUCENT, PCI_DEVICE_ID_LUCENT_FW323 },
134 { -1, -1 }
135 };
136
137 static struct ti_ohci cards[MAX_OHCI1394_CARDS];
138 static int num_of_cards = 0;
139
140 static int add_card(struct pci_dev *dev);
141 static void remove_card(struct ti_ohci *ohci);
142 static int init_driver(void);
143 static void dma_trm_bh(void *data);
144 static void dma_rcv_bh(void *data);
145 static void dma_trm_reset(struct dma_trm_ctx *d);
146
147 /***********************************
148 * IEEE-1394 functionality section *
149 ***********************************/
150
151 #if 0 /* not needed at this time */
152 static int get_phy_reg(struct ti_ohci *ohci, int addr)
153 {
154 int timeout=10000;
155 static quadlet_t r;
156
157 if ((addr < 1) || (addr > 15)) {
158 PRINT(KERN_ERR, ohci->id, __FUNCTION__
159 ": PHY register address %d out of range", addr);
160 return -EFAULT;
161 }
162
163 spin_lock(&ohci->phy_reg_lock);
164
165 /* initiate read request */
166 reg_write(ohci, OHCI1394_PhyControl,
167 ((addr<<8)&0x00000f00) | 0x00008000);
168
169 /* wait */
170 while (!(reg_read(ohci, OHCI1394_PhyControl)&0x80000000) && timeout)
171 timeout--;
172
173
174 if (!timeout) {
175 PRINT(KERN_ERR, ohci->id, "get_phy_reg timeout !!!\n");
176 spin_unlock(&ohci->phy_reg_lock);
177 return -EFAULT;
178 }
179 r = reg_read(ohci, OHCI1394_PhyControl);
180
181 spin_unlock(&ohci->phy_reg_lock);
182
183 return (r&0x00ff0000)>>16;
184 }
185
186 static int set_phy_reg(struct ti_ohci *ohci, int addr, unsigned char data) {
187 int timeout=10000;
188 u32 r;
189
190 if ((addr < 1) || (addr > 15)) {
191 PRINT(KERN_ERR, ohci->id, __FUNCTION__
192 ": PHY register address %d out of range", addr);
193 return -EFAULT;
194 }
195
196 r = ((addr<<8)&0x00000f00) | 0x00004000 | ((u32)data & 0x000000ff);
197
198 spin_lock(&ohci->phy_reg_lock);
199
200 reg_write(ohci, OHCI1394_PhyControl, r);
201
202 /* wait */
203 while (!(reg_read(ohci, OHCI1394_PhyControl)&0x80000000) && timeout)
204 timeout--;
205
206 spin_unlock(&ohci->phy_reg_lock);
207
208 if (!timeout) {
209 PRINT(KERN_ERR, ohci->id, "set_phy_reg timeout !!!\n");
210 return -EFAULT;
211 }
212
213 return 0;
214 }
215 #endif /* unneeded functions */
216
217 inline static int handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
218 int phyid, int isroot)
219 {
220 quadlet_t *q = ohci->selfid_buf_cpu;
221 quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
222 size_t size;
223 quadlet_t lsid;
224
225 /* Self-id handling seems much easier than for the aic5800 chip.
226 All the self-id packets, including this device own self-id,
227 should be correctly arranged in the selfid buffer at this
228 stage */
229
230 /* Check status of self-id reception */
231 if ((self_id_count&0x80000000) ||
232 ((self_id_count&0x00FF0000) != (q[0]&0x00FF0000))) {
233 PRINT(KERN_ERR, ohci->id,
234 "Error in reception of self-id packets"
235 "Self-id count: %08x q[0]: %08x",
236 self_id_count, q[0]);
237
238 /*
239 * Tip by James Goodwin <jamesg@Filanet.com>:
240 * We had an error, generate another bus reset in response.
241 * TODO. Actually read the current value in the phy before
242 * generating a bus reset (read modify write). This way
243 * we don't stomp any current gap count settings, etc.
244 */
245 if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
246 reg_write(ohci, OHCI1394_PhyControl, 0x000041ff);
247 ohci->self_id_errors++;
248 }
249 else {
250 PRINT(KERN_ERR, ohci->id,
251 "Timeout on self-id error reception");
252 }
253 return -1;
254 }
255
256 size = ((self_id_count&0x0000EFFC)>>2) - 1;
257 q++;
258
259 while (size > 0) {
260 if (q[0] == ~q[1]) {
261 PRINT(KERN_INFO, ohci->id, "selfid packet 0x%x rcvd",
262 q[0]);
263 hpsb_selfid_received(host, cpu_to_be32(q[0]));
264 if (((q[0]&0x3f000000)>>24)==phyid) {
265 lsid=q[0];
266 PRINT(KERN_INFO, ohci->id,
267 "This node self-id is 0x%08x", lsid);
268 }
269 } else {
270 PRINT(KERN_ERR, ohci->id,
271 "inconsistent selfid 0x%x/0x%x", q[0], q[1]);
272 }
273 q += 2;
274 size -= 2;
275 }
276
277 PRINT(KERN_INFO, ohci->id, "calling self-id complete");
278
279 hpsb_selfid_complete(host, phyid, isroot);
280 return 0;
281 }
282
283 static int ohci_detect(struct hpsb_host_template *tmpl)
284 {
285 struct hpsb_host *host;
286 int i;
287
288 init_driver();
289
290 for (i = 0; i < num_of_cards; i++) {
291 host = hpsb_get_host(tmpl, 0);
292 if (host == NULL) {
293 /* simply don't init more after out of mem */
294 return i;
295 }
296 host->hostdata = &cards[i];
297 cards[i].host = host;
298 }
299
300 return num_of_cards;
301 }
302
303 static int ohci_soft_reset(struct ti_ohci *ohci) {
304 int timeout=10000;
305
306 reg_write(ohci, OHCI1394_HCControlSet, 0x00010000);
307
308 while ((reg_read(ohci, OHCI1394_HCControlSet)&0x00010000) && timeout)
309 timeout--;
310 if (!timeout) {
311 PRINT(KERN_ERR, ohci->id, "soft reset timeout !!!");
312 return -EFAULT;
313 }
314 else PRINT(KERN_INFO, ohci->id, "soft reset finished");
315 return 0;
316 }
317
318 static int run_context(struct ti_ohci *ohci, int reg, char *msg)
319 {
320 u32 nodeId;
321
322 /* check that the node id is valid */
323 nodeId = reg_read(ohci, OHCI1394_NodeID);
324 if (!(nodeId&0x80000000)) {
325 PRINT(KERN_ERR, ohci->id,
326 "Running dma failed because Node ID not valid");
327 return -1;
328 }
329
330 /* check that the node number != 63 */
331 if ((nodeId&0x3f)==63) {
332 PRINT(KERN_ERR, ohci->id,
333 "Running dma failed because Node ID == 63");
334 return -1;
335 }
336
337 /* Run the dma context */
338 reg_write(ohci, reg, 0x8000);
339
340 if (msg) PRINT(KERN_INFO, ohci->id, "%s", msg);
341
342 return 0;
343 }
344
345 /* Generate the dma receive prgs and start the context */
346 static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d)
347 {
348 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
349 int i;
350
351 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
352
353 for (i=0; i<d->num_desc; i++) {
354
355 /* end of descriptor list? */
356 if ((i+1) < d->num_desc) {
357 d->prg_cpu[i]->control = (0x283C << 16) | d->buf_size;
358 d->prg_cpu[i]->branchAddress =
359 (d->prg_bus[i+1] & 0xfffffff0) | 0x1;
360 } else {
361 d->prg_cpu[i]->control = (0x283C << 16) | d->buf_size;
362 d->prg_cpu[i]->branchAddress =
363 d->prg_bus[0] & 0xfffffff0;
364 }
365
366 d->prg_cpu[i]->address = d->buf_bus[i];
367 d->prg_cpu[i]->status = d->buf_size;
368 }
369
370 d->buf_ind = 0;
371 d->buf_offset = 0;
372
373 /* Tell the controller where the first AR program is */
374 reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
375
376 /* Run AR context */
377 reg_write(ohci, d->ctrlSet, 0x00008000);
378
379 PRINT(KERN_INFO, ohci->id, "Receive DMA ctx=%d initialized", d->ctx);
380 }
381
382 /* Initialize the dma transmit context */
383 static void initialize_dma_trm_ctx(struct dma_trm_ctx *d)
384 {
385 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
386
387 /* Stop the context */
388 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
389
390 d->prg_ind = 0;
391 d->sent_ind = 0;
392 d->free_prgs = d->num_desc;
393 d->branchAddrPtr = NULL;
394 d->fifo_first = NULL;
395 d->fifo_last = NULL;
396 d->pending_first = NULL;
397 d->pending_last = NULL;
398
399 PRINT(KERN_INFO, ohci->id, "AT dma ctx=%d initialized", d->ctx);
400 }
401
402 /* Count the number of available iso contexts */
403 static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
404 {
405 int i,ctx=0;
406 u32 tmp;
407
408 reg_write(ohci, reg, 0xffffffff);
409 tmp = reg_read(ohci, reg);
410
411 DBGMSG(ohci->id,"Iso contexts reg: %08x implemented: %08x", reg, tmp);
412
413 /* Count the number of contexts */
414 for(i=0; i<32; i++) {
415 if(tmp & 1) ctx++;
416 tmp >>= 1;
417 }
418 return ctx;
419 }
420
421 /* Global initialization */
422 static int ohci_initialize(struct hpsb_host *host)
423 {
424 struct ti_ohci *ohci=host->hostdata;
425 int retval, i;
426
427 spin_lock_init(&ohci->phy_reg_lock);
428
429 /*
430 * Tip by James Goodwin <jamesg@Filanet.com>:
431 * We need to add delays after the soft reset, setting LPS, and
432 * enabling our link. This might fixes the self-id reception
433 * problem at initialization.
434 */
435
436 /* Soft reset */
437 if ((retval=ohci_soft_reset(ohci))<0) return retval;
438
439 /*
440 * Delay after soft reset to make sure everything has settled
441 * down (sanity)
442 */
443 mdelay(100);
444
445 /* Set Link Power Status (LPS) */
446 reg_write(ohci, OHCI1394_HCControlSet, 0x00080000);
447
448 /*
449 * Delay after setting LPS in order to make sure link/phy
450 * communication is established
451 */
452 mdelay(100);
453
454 /* Set the bus number */
455 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
456
457 /* Enable posted writes */
458 reg_write(ohci, OHCI1394_HCControlSet, 0x00040000);
459
460 /* Clear link control register */
461 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
462
463 /* Enable cycle timer and cycle master */
464 reg_write(ohci, OHCI1394_LinkControlSet, 0x00300000);
465
466 /* Clear interrupt registers */
467 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
468 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
469
470 /* Set up self-id dma buffer */
471 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
472
473 /* enable self-id dma */
474 reg_write(ohci, OHCI1394_LinkControlSet, 0x00000200);
475
476 /* Set the configuration ROM mapping register */
477 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
478
479 /* Set bus options */
480 reg_write(ohci, OHCI1394_BusOptions,
481 cpu_to_be32(ohci->csr_config_rom_cpu[2]));
482
483 #if 0
484 /* Write the GUID into the csr config rom */
485 ohci->csr_config_rom_cpu[3] =
486 be32_to_cpu(reg_read(ohci, OHCI1394_GUIDHi));
487 ohci->csr_config_rom_cpu[4] =
488 be32_to_cpu(reg_read(ohci, OHCI1394_GUIDLo));
489 #endif
490
491 /* Write the config ROM header */
492 reg_write(ohci, OHCI1394_ConfigROMhdr,
493 cpu_to_be32(ohci->csr_config_rom_cpu[0]));
494
495 ohci->max_packet_size =
496 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
497 PRINT(KERN_INFO, ohci->id, "max packet size = %d bytes",
498 ohci->max_packet_size);
499
500 /* Don't accept phy packets into AR request context */
501 reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
502
503 /* Initialize IR dma */
504 ohci->nb_iso_rcv_ctx =
505 get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);
506 PRINT(KERN_INFO, ohci->id, "%d iso receive contexts available",
507 ohci->nb_iso_rcv_ctx);
508 for (i=0;i<ohci->nb_iso_rcv_ctx;i++) {
509 reg_write(ohci, OHCI1394_IsoRcvContextControlClear+32*i,
510 0xffffffff);
511 reg_write(ohci, OHCI1394_IsoRcvContextMatch+32*i, 0);
512 reg_write(ohci, OHCI1394_IsoRcvCommandPtr+32*i, 0);
513 }
514
515 /* Set bufferFill, isochHeader, multichannel for IR context */
516 reg_write(ohci, OHCI1394_IsoRcvContextControlSet, 0xd0000000);
517
518 /* Set the context match register to match on all tags */
519 reg_write(ohci, OHCI1394_IsoRcvContextMatch, 0xf0000000);
520
521 /* Clear the interrupt mask */
522 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
523 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
524
525 /* Initialize IT dma */
526 ohci->nb_iso_xmit_ctx =
527 get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);
528 PRINT(KERN_INFO, ohci->id, "%d iso transmit contexts available",
529 ohci->nb_iso_xmit_ctx);
530 for (i=0;i<ohci->nb_iso_xmit_ctx;i++) {
531 reg_write(ohci, OHCI1394_IsoXmitContextControlClear+32*i,
532 0xffffffff);
533 reg_write(ohci, OHCI1394_IsoXmitCommandPtr+32*i, 0);
534 }
535
536 /* Clear the interrupt mask */
537 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
538 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
539
540 /* Clear the multi channel mask high and low registers */
541 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
542 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
543
544 /* Initialize AR dma */
545 initialize_dma_rcv_ctx(ohci->ar_req_context);
546 initialize_dma_rcv_ctx(ohci->ar_resp_context);
547
548 /* Initialize AT dma */
549 initialize_dma_trm_ctx(ohci->at_req_context);
550 initialize_dma_trm_ctx(ohci->at_resp_context);
551
552 /* Initialize IR dma */
553 initialize_dma_rcv_ctx(ohci->ir_context);
554
555 /* Set up isoRecvIntMask to generate interrupts for context 0
556 (thanks to Michael Greger for seeing that I forgot this) */
557 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 0x00000001);
558
559 /*
560 * Accept AT requests from all nodes. This probably
561 * will have to be controlled from the subsystem
562 * on a per node basis.
563 */
564 reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000);
565
566 /* Specify AT retries */
567 reg_write(ohci, OHCI1394_ATRetries,
568 OHCI1394_MAX_AT_REQ_RETRIES |
569 (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
570 (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
571
572 #ifndef __BIG_ENDIAN
573 reg_write(ohci, OHCI1394_HCControlClear, 0x40000000);
574 #else
575 reg_write(ohci, OHCI1394_HCControlSet, 0x40000000);
576 #endif
577
578 /* Enable interrupts */
579 reg_write(ohci, OHCI1394_IntMaskSet,
580 OHCI1394_masterIntEnable |
581 OHCI1394_phyRegRcvd |
582 OHCI1394_busReset |
583 OHCI1394_selfIDComplete |
584 OHCI1394_RSPkt |
585 OHCI1394_RQPkt |
586 OHCI1394_ARRS |
587 OHCI1394_ARRQ |
588 OHCI1394_respTxComplete |
589 OHCI1394_reqTxComplete |
590 OHCI1394_isochRx |
591 OHCI1394_isochTx
592 );
593
594 /* Enable link */
595 reg_write(ohci, OHCI1394_HCControlSet, 0x00020000);
596
597 return 1;
598 }
599
600 static void ohci_remove(struct hpsb_host *host)
601 {
602 struct ti_ohci *ohci;
603
604 if (host != NULL) {
605 ohci = host->hostdata;
606 remove_card(ohci);
607 }
608 }
609
610 /*
611 * Insert a packet in the AT DMA fifo and generate the DMA prg
612 * FIXME: rewrite the program in order to accept packets crossing
613 * page boundaries.
614 * check also that a single dma descriptor doesn't cross a
615 * page boundary.
616 */
617 static void insert_packet(struct ti_ohci *ohci,
618 struct dma_trm_ctx *d, struct hpsb_packet *packet)
619 {
620 u32 cycleTimer;
621 int idx = d->prg_ind;
622
623 d->prg_cpu[idx]->begin.address = 0;
624 d->prg_cpu[idx]->begin.branchAddress = 0;
625 if (d->ctx==1) {
626 /*
627 * For response packets, we need to put a timeout value in
628 * the 16 lower bits of the status... let's try 1 sec timeout
629 */
630 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
631 d->prg_cpu[idx]->begin.status =
632 (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) |
633 ((cycleTimer&0x01fff000)>>12);
634
635 DBGMSG(ohci->id, "cycleTimer: %08x timeStamp: %08x",
636 cycleTimer, d->prg_cpu[idx]->begin.status);
637 }
638 else
639 d->prg_cpu[idx]->begin.status = 0;
640
641 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
642 (packet->header[0] & 0xFFFF);
643 d->prg_cpu[idx]->data[1] = (packet->header[1] & 0xFFFF) |
644 (packet->header[0] & 0xFFFF0000);
645 d->prg_cpu[idx]->data[2] = packet->header[2];
646 d->prg_cpu[idx]->data[3] = packet->header[3];
647
648 if (packet->data_size) { /* block transmit */
649 d->prg_cpu[idx]->begin.control = OUTPUT_MORE_IMMEDIATE | 0x10;
650 d->prg_cpu[idx]->end.control = OUTPUT_LAST | packet->data_size;
651 /*
652 * FIXME: check that the packet data buffer
653 * do not cross a page boundary
654 */
655 d->prg_cpu[idx]->end.address =
656 pci_map_single(ohci->dev, packet->data,
657 packet->data_size, PCI_DMA_TODEVICE);
658 d->prg_cpu[idx]->end.branchAddress = 0;
659 d->prg_cpu[idx]->end.status = 0;
660 if (d->branchAddrPtr)
661 *(d->branchAddrPtr) = d->prg_bus[idx] | 0x3;
662 d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress);
663 }
664 else { /* quadlet transmit */
665 d->prg_cpu[idx]->begin.control =
666 OUTPUT_LAST_IMMEDIATE | packet->header_size;
667 if (d->branchAddrPtr)
668 *(d->branchAddrPtr) = d->prg_bus[idx] | 0x2;
669 d->branchAddrPtr = &(d->prg_cpu[idx]->begin.branchAddress);
670 }
671 d->free_prgs--;
672
673 /* queue the packet in the appropriate context queue */
674 if (d->fifo_last) {
675 d->fifo_last->xnext = packet;
676 d->fifo_last = packet;
677 }
678 else {
679 d->fifo_first = packet;
680 d->fifo_last = packet;
681 }
682 d->prg_ind = (d->prg_ind+1)%d->num_desc;
683 }
684
685 /*
686 * This function fills the AT FIFO with the (eventual) pending packets
687 * and runs or wake up the AT DMA prg if necessary.
688 * The function MUST be called with the d->lock held.
689 */
690 static int dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
691 {
692 int idx,z;
693
694 if (d->pending_first == NULL || d->free_prgs == 0)
695 return 0;
696
697 idx = d->prg_ind;
698 z = (d->pending_first->data_size) ? 3 : 2;
699
700 /* insert the packets into the at dma fifo */
701 while (d->free_prgs>0 && d->pending_first) {
702 insert_packet(ohci, d, d->pending_first);
703 d->pending_first = d->pending_first->xnext;
704 }
705 if (d->pending_first == NULL)
706 d->pending_last = NULL;
707 else
708 PRINT(KERN_INFO, ohci->id,
709 "AT DMA FIFO ctx=%d full... waiting",d->ctx);
710
711 /* Is the context running ? (should be unless it is
712 the first packet to be sent in this context) */
713 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
714 DBGMSG(ohci->id,"Starting AT DMA ctx=%d",d->ctx);
715 reg_write(ohci, d->cmdPtr, d->prg_bus[idx]|z);
716 run_context(ohci, d->ctrlSet, NULL);
717 }
718 else {
719 DBGMSG(ohci->id,"Waking AT DMA ctx=%d",d->ctx);
720 /* wake up the dma context if necessary */
721 if (!(reg_read(ohci, d->ctrlSet) & 0x400))
722 reg_write(ohci, d->ctrlSet, 0x1000);
723 }
724 return 1;
725 }
726
727 /*
728 * Transmission of an async packet
729 */
730 static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
731 {
732 struct ti_ohci *ohci = host->hostdata;
733 struct dma_trm_ctx *d;
734 unsigned char tcode;
735 unsigned long flags;
736
737 if (packet->data_size >= ohci->max_packet_size) {
738 PRINT(KERN_ERR, ohci->id,
739 "transmit packet size = %d too big",
740 packet->data_size);
741 return 0;
742 }
743 packet->xnext = NULL;
744
745 /* Decide wether we have a request or a response packet */
746 tcode = (packet->header[0]>>4)&0xf;
747 if (tcode & 0x02) d = ohci->at_resp_context;
748 else d = ohci->at_req_context;
749
750 spin_lock_irqsave(&d->lock,flags);
751
752 /* queue the packet for later insertion into to dma fifo */
753 if (d->pending_last) {
754 d->pending_last->xnext = packet;
755 d->pending_last = packet;
756 }
757 else {
758 d->pending_first = packet;
759 d->pending_last = packet;
760 }
761
762 dma_trm_flush(ohci, d);
763
764 spin_unlock_irqrestore(&d->lock,flags);
765
766 return 1;
767 }
768
769 static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
770 {
771 struct ti_ohci *ohci = host->hostdata;
772 int retval = 0;
773 unsigned long flags;
774
775 switch (cmd) {
776 case RESET_BUS:
777 /*
778 * FIXME: this flag might be necessary in some case
779 */
780 /* host->attempt_root = 1; */
781 PRINT(KERN_INFO, ohci->id, "resetting bus on request%s",
782 (host->attempt_root ? " and attempting to become root"
783 : ""));
784 reg_write(ohci, OHCI1394_PhyControl,
785 (host->attempt_root) ? 0x000041ff : 0x0000417f);
786 break;
787
788 case GET_CYCLE_COUNTER:
789 retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
790 break;
791
792 case SET_CYCLE_COUNTER:
793 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
794 break;
795
796 case SET_BUS_ID:
797 PRINT(KERN_ERR, ohci->id, "devctl command SET_BUS_ID err");
798 break;
799
800 case ACT_CYCLE_MASTER:
801 if (arg) {
802 /* check if we are root and other nodes are present */
803 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
804 if ((nodeId & (1<<30)) && (nodeId & 0x3f)) {
805 /*
806 * enable cycleTimer cycleMaster cycleSource
807 */
808 DBGMSG(ohci->id, "Cycle master enabled");
809 reg_write(ohci, OHCI1394_LinkControlSet,
810 0x00700000);
811 }
812 } else {
813 /* disable cycleTimer, cycleMaster, cycleSource */
814 reg_write(ohci, OHCI1394_LinkControlClear, 0x00700000);
815 }
816 break;
817
818 case CANCEL_REQUESTS:
819 DBGMSG(ohci->id, "Cancel request received");
820 dma_trm_reset(ohci->at_req_context);
821 dma_trm_reset(ohci->at_resp_context);
822 break;
823
824 case MODIFY_USAGE:
825 if (arg) {
826 MOD_INC_USE_COUNT;
827 } else {
828 MOD_DEC_USE_COUNT;
829 }
830 break;
831
832 case ISO_LISTEN_CHANNEL:
833
834 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
835
836 if (!test_and_set_bit(arg, &ohci->IR_channel_usage)) {
837 DBGMSG(ohci->id,
838 "listening enabled on channel %d", arg);
839
840 if (arg > 31) {
841 u32 setMask= 0x00000001;
842 arg-= 32;
843 while(arg--) setMask= setMask << 1;
844 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet,
845 setMask);
846 } else {
847 u32 setMask= 0x00000001;
848 while(arg--) setMask= setMask << 1;
849 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet,
850 setMask);
851 }
852
853 }
854
855 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
856 break;
857
858 case ISO_UNLISTEN_CHANNEL:
859
860 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
861
862 if (test_and_clear_bit(arg, &ohci->IR_channel_usage)) {
863 DBGMSG(ohci->id,
864 "listening disabled on iso channel %d", arg);
865
866 if (arg > 31) {
867 u32 clearMask= 0x00000001;
868 arg-= 32;
869 while(arg--) clearMask= clearMask << 1;
870 reg_write(ohci,
871 OHCI1394_IRMultiChanMaskHiClear,
872 clearMask);
873 } else {
874 u32 clearMask= 0x00000001;
875 while(arg--) clearMask= clearMask << 1;
876 reg_write(ohci,
877 OHCI1394_IRMultiChanMaskLoClear,
878 clearMask);
879 }
880
881 }
882
883 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
884 break;
885
886 default:
887 PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet\n",
888 cmd);
889 break;
890 }
891 return retval;
892 }
893
894 /***************************************
895 * IEEE-1394 functionality section END *
896 ***************************************/
897
898
899 /********************************************************
900 * Global stuff (interrupt handler, init/shutdown code) *
901 ********************************************************/
902
903 static void dma_trm_reset(struct dma_trm_ctx *d)
904 {
905 struct ti_ohci *ohci;
906 unsigned long flags;
907
908 if (d==NULL) {
909 PRINT_G(KERN_ERR, "dma_trm_reset called with NULL arg");
910 return;
911 }
912 ohci = (struct ti_ohci *)(d->ohci);
913 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
914
915 spin_lock_irqsave(&d->lock,flags);
916
917 /* is there still any packet pending in the fifo ? */
918 while(d->fifo_first) {
919 PRINT(KERN_INFO, ohci->id,
920 "AT dma reset ctx=%d, aborting transmission",
921 d->ctx);
922 hpsb_packet_sent(ohci->host, d->fifo_first, ACKX_ABORTED);
923 d->fifo_first = d->fifo_first->xnext;
924 }
925 d->fifo_first = d->fifo_last = NULL;
926
927 /* is there still any packet pending ? */
928 while(d->pending_first) {
929 PRINT(KERN_INFO, ohci->id,
930 "AT dma reset ctx=%d, aborting transmission",
931 d->ctx);
932 hpsb_packet_sent(ohci->host, d->pending_first,
933 ACKX_ABORTED);
934 d->pending_first = d->pending_first->xnext;
935 }
936 d->pending_first = d->pending_last = NULL;
937
938 d->branchAddrPtr=NULL;
939 d->sent_ind = d->prg_ind;
940 d->free_prgs = d->num_desc;
941 spin_unlock_irqrestore(&d->lock,flags);
942 }
943
944 static void ohci_irq_handler(int irq, void *dev_id,
945 struct pt_regs *regs_are_unused)
946 {
947 quadlet_t event,node_id;
948 struct ti_ohci *ohci = (struct ti_ohci *)dev_id;
949 struct hpsb_host *host = ohci->host;
950 int phyid = -1, isroot = 0;
951 int timeout = 255;
952
953 do {
954 /* read the interrupt event register */
955 event=reg_read(ohci, OHCI1394_IntEventClear);
956
957 if (!event) return;
958
959 DBGMSG(ohci->id, "IntEvent: %08x",event);
960
961 /* clear the interrupt event register */
962 reg_write(ohci, OHCI1394_IntEventClear, event);
963
964 if (event & OHCI1394_busReset) {
965 if (!host->in_bus_reset) {
966 PRINT(KERN_INFO, ohci->id, "Bus reset");
967
968 /* Wait for the AT fifo to be flushed */
969 dma_trm_reset(ohci->at_req_context);
970 dma_trm_reset(ohci->at_resp_context);
971
972 /* Subsystem call */
973 hpsb_bus_reset(ohci->host);
974
975 ohci->NumBusResets++;
976 }
977 }
978 /*
979 * Problem: How can I ensure that the AT bottom half will be
980 * executed before the AR bottom half (both events may have
981 * occured within a single irq event)
982 * Quick hack: just launch it within the IRQ handler
983 */
984 if (event & OHCI1394_reqTxComplete) {
985 struct dma_trm_ctx *d = ohci->at_req_context;
986 DBGMSG(ohci->id, "Got reqTxComplete interrupt "
987 "status=0x%08X", reg_read(ohci, d->ctrlSet));
988 if (reg_read(ohci, d->ctrlSet) & 0x800)
989 ohci1394_stop_context(ohci, d->ctrlClear,
990 "reqTxComplete");
991 else
992 dma_trm_bh((void *)d);
993 }
994 if (event & OHCI1394_respTxComplete) {
995 struct dma_trm_ctx *d = ohci->at_resp_context;
996 DBGMSG(ohci->id, "Got respTxComplete interrupt "
997 "status=0x%08X", reg_read(ohci, d->ctrlSet));
998 if (reg_read(ohci, d->ctrlSet) & 0x800)
999 ohci1394_stop_context(ohci, d->ctrlClear,
1000 "respTxComplete");
1001 else
1002 dma_trm_bh((void *)d);
1003 }
1004 if (event & OHCI1394_RQPkt) {
1005 struct dma_rcv_ctx *d = ohci->ar_req_context;
1006 DBGMSG(ohci->id, "Got RQPkt interrupt status=0x%08X",
1007 reg_read(ohci, d->ctrlSet));
1008 if (reg_read(ohci, d->ctrlSet) & 0x800)
1009 ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt");
1010 else {
1011 #if IEEE1394_USE_BOTTOM_HALVES
1012 queue_task(&d->task, &tq_immediate);
1013 mark_bh(IMMEDIATE_BH);
1014 #else
1015 dma_rcv_bh((void *)d);
1016 #endif
1017 }
1018 }
1019 if (event & OHCI1394_RSPkt) {
1020 struct dma_rcv_ctx *d = ohci->ar_resp_context;
1021 DBGMSG(ohci->id, "Got RSPkt interrupt status=0x%08X",
1022 reg_read(ohci, d->ctrlSet));
1023 if (reg_read(ohci, d->ctrlSet) & 0x800)
1024 ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt");
1025 else {
1026 #if IEEE1394_USE_BOTTOM_HALVES
1027 queue_task(&d->task, &tq_immediate);
1028 mark_bh(IMMEDIATE_BH);
1029 #else
1030 dma_rcv_bh((void *)d);
1031 #endif
1032 }
1033 }
1034 if (event & OHCI1394_isochRx) {
1035 quadlet_t isoRecvIntEvent;
1036 struct dma_rcv_ctx *d = ohci->ir_context;
1037 isoRecvIntEvent =
1038 reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
1039 reg_write(ohci, OHCI1394_IsoRecvIntEventClear,
1040 isoRecvIntEvent);
1041 DBGMSG(ohci->id, "Got isochRx interrupt "
1042 "status=0x%08X isoRecvIntEvent=%08x",
1043 reg_read(ohci, d->ctrlSet), isoRecvIntEvent);
1044 if (isoRecvIntEvent & 0x1) {
1045 if (reg_read(ohci, d->ctrlSet) & 0x800)
1046 ohci1394_stop_context(ohci, d->ctrlClear,
1047 "isochRx");
1048 else {
1049 #if IEEE1394_USE_BOTTOM_HALVES
1050 queue_task(&d->task, &tq_immediate);
1051 mark_bh(IMMEDIATE_BH);
1052 #else
1053 dma_rcv_bh((void *)d);
1054 #endif
1055 }
1056 }
1057 if (ohci->video_tmpl)
1058 ohci->video_tmpl->irq_handler(ohci->id,
1059 isoRecvIntEvent,
1060 0);
1061 }
1062 if (event & OHCI1394_isochTx) {
1063 quadlet_t isoXmitIntEvent;
1064 isoXmitIntEvent =
1065 reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
1066 reg_write(ohci, OHCI1394_IsoXmitIntEventClear,
1067 isoXmitIntEvent);
1068 DBGMSG(ohci->id, "Got isochTx interrupt");
1069 if (ohci->video_tmpl)
1070 ohci->video_tmpl->irq_handler(ohci->id, 0,
1071 isoXmitIntEvent);
1072 }
1073 if (event & OHCI1394_selfIDComplete) {
1074 if (host->in_bus_reset) {
1075 node_id = reg_read(ohci, OHCI1394_NodeID);
1076 if (node_id & 0x80000000) { /* NodeID valid */
1077 phyid = node_id & 0x0000003f;
1078 isroot = (node_id & 0x40000000) != 0;
1079
1080 PRINT(KERN_INFO, ohci->id,
1081 "SelfID process finished "
1082 "(phyid %d, %s)", phyid,
1083 (isroot ? "root" : "not root"));
1084
1085 handle_selfid(ohci, host,
1086 phyid, isroot);
1087 }
1088 else
1089 PRINT(KERN_ERR, ohci->id,
1090 "SelfID process finished but "
1091 "NodeID not valid: %08X",
1092 node_id);
1093
1094 /* Accept Physical requests from all nodes. */
1095 reg_write(ohci,OHCI1394_AsReqFilterHiSet,
1096 0xffffffff);
1097 reg_write(ohci,OHCI1394_AsReqFilterLoSet,
1098 0xffffffff);
1099 /*
1100 * Tip by James Goodwin <jamesg@Filanet.com>
1101 * Turn on phys dma reception. We should
1102 * probably manage the filtering somehow,
1103 * instead of blindly turning it on.
1104 */
1105 reg_write(ohci,OHCI1394_PhyReqFilterHiSet,
1106 0xffffffff);
1107 reg_write(ohci,OHCI1394_PhyReqFilterLoSet,
1108 0xffffffff);
1109 reg_write(ohci,OHCI1394_PhyUpperBound,
1110 0xffff0000);
1111 }
1112 else PRINT(KERN_ERR, ohci->id,
1113 "self-id received outside of bus reset"
1114 "sequence");
1115 }
1116 if (event & OHCI1394_phyRegRcvd) {
1117 #if 1
1118 if (host->in_bus_reset) {
1119 PRINT(KERN_INFO, ohci->id, "PhyControl: %08X",
1120 reg_read(ohci, OHCI1394_PhyControl));
1121 }
1122 else PRINT(KERN_ERR, ohci->id,
1123 "phy reg received outside of bus reset"
1124 "sequence");
1125 #endif
1126 }
1127 } while (--timeout);
1128
1129 PRINT(KERN_ERR, ohci->id, "irq_handler timeout event=0x%08x", event);
1130 }
1131
1132 /* Put the buffer back into the dma context */
1133 static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx)
1134 {
1135 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1136 DBGMSG(ohci->id, "Inserting dma buf ctx=%d idx=%d", d->ctx, idx);
1137
1138 d->prg_cpu[idx]->status = d->buf_size;
1139 d->prg_cpu[idx]->branchAddress &= 0xfffffff0;
1140 idx = (idx + d->num_desc - 1 ) % d->num_desc;
1141 d->prg_cpu[idx]->branchAddress |= 0x1;
1142
1143 /* wake up the dma context if necessary */
1144 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
1145 PRINT(KERN_INFO, ohci->id,
1146 "Waking dma cxt=%d ... processing is probably too slow",
1147 d->ctx);
1148 reg_write(ohci, d->ctrlSet, 0x1000);
1149 }
1150 }
1151
1152 static int block_length(struct dma_rcv_ctx *d, int idx,
1153 quadlet_t *buf_ptr, int offset)
1154 {
1155 int length=0;
1156
1157 /* Where is the data length ? */
1158 if (offset+12>=d->buf_size)
1159 length = (d->buf_cpu[(idx+1)%d->num_desc]
1160 [3-(d->buf_size-offset)/4]>>16);
1161 else
1162 length = (buf_ptr[3]>>16);
1163 if (length % 4) length += 4 - (length % 4);
1164 return length;
1165 }
1166
1167 const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0,
1168 -1, 0, -1, 0, -1, -1, 16, -1};
1169
1170 /*
1171 * Determine the length of a packet in the buffer
1172 * Optimization suggested by Pascal Drolet <pascal.drolet@informission.ca>
1173 */
1174 static int packet_length(struct dma_rcv_ctx *d, int idx, quadlet_t *buf_ptr,
1175 int offset)
1176 {
1177 unsigned char tcode;
1178 int length = -1;
1179
1180 /* Let's see what kind of packet is in there */
1181 tcode = (buf_ptr[0] >> 4) & 0xf;
1182
1183 if (d->ctx < 2) { /* Async Receive Response/Request */
1184 length = TCODE_SIZE[tcode];
1185 if (length == 0)
1186 length = block_length(d, idx, buf_ptr, offset) + 20;
1187 }
1188 else if (d->ctx==2) { /* Iso receive */
1189 /* Assumption: buffer fill mode with header/trailer */
1190 length = (buf_ptr[0]>>16);
1191 if (length % 4) length += 4 - (length % 4);
1192 length+=8;
1193 }
1194 return length;
1195 }
1196
1197 /* Bottom half that processes dma receive buffers */
1198 static void dma_rcv_bh(void *data)
1199 {
1200 struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data;
1201 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1202 unsigned int split_left, idx, offset, rescount;
1203 unsigned char tcode;
1204 int length, bytes_left, ack;
1205 quadlet_t *buf_ptr;
1206 char *split_ptr;
1207 char msg[256];
1208
1209 spin_lock(&d->lock);
1210
1211 idx = d->buf_ind;
1212 offset = d->buf_offset;
1213 buf_ptr = d->buf_cpu[idx] + offset/4;
1214
1215 rescount = d->prg_cpu[idx]->status&0xffff;
1216 bytes_left = d->buf_size - rescount - offset;
1217
1218 while (bytes_left>0) {
1219 tcode = (buf_ptr[0]>>4)&0xf;
1220 length = packet_length(d, idx, buf_ptr, offset);
1221
1222 if (length<4) { /* something is wrong */
1223 sprintf(msg,"unexpected tcode 0x%X in AR ctx=%d",
1224 tcode, d->ctx);
1225 ohci1394_stop_context(ohci, d->ctrlClear, msg);
1226 spin_unlock(&d->lock);
1227 return;
1228 }
1229
1230 if ((offset+length)>d->buf_size) { /* Split packet */
1231 if (length>d->split_buf_size) {
1232 ohci1394_stop_context(ohci, d->ctrlClear,
1233 "split packet size exceeded");
1234 d->buf_ind = idx;
1235 d->buf_offset = offset;
1236 spin_unlock(&d->lock);
1237 return;
1238 }
1239 if (d->prg_cpu[(idx+1)%d->num_desc]->status
1240 ==d->buf_size) {
1241 /* other part of packet not written yet */
1242 /* this should never happen I think */
1243 /* anyway we'll get it on the next call */
1244 PRINT(KERN_INFO, ohci->id,
1245 "Got only half a packet !!!");
1246 d->buf_ind = idx;
1247 d->buf_offset = offset;
1248 spin_unlock(&d->lock);
1249 return;
1250 }
1251 split_left = length;
1252 split_ptr = (char *)d->spb;
1253 memcpy(split_ptr,buf_ptr,d->buf_size-offset);
1254 split_left -= d->buf_size-offset;
1255 split_ptr += d->buf_size-offset;
1256 insert_dma_buffer(d, idx);
1257 idx = (idx+1) % d->num_desc;
1258 buf_ptr = d->buf_cpu[idx];
1259 offset=0;
1260 while (split_left >= d->buf_size) {
1261 memcpy(split_ptr,buf_ptr,d->buf_size);
1262 split_ptr += d->buf_size;
1263 split_left -= d->buf_size;
1264 insert_dma_buffer(d, idx);
1265 idx = (idx+1) % d->num_desc;
1266 buf_ptr = d->buf_cpu[idx];
1267 }
1268 if (split_left>0) {
1269 memcpy(split_ptr, buf_ptr, split_left);
1270 offset = split_left;
1271 buf_ptr += offset/4;
1272 }
1273
1274 /*
1275 * We get one phy packet for each bus reset.
1276 * we know that from now on the bus topology may
1277 * have changed. Just ignore it for the moment
1278 */
1279 if (tcode != 0xE) {
1280 DBGMSG(ohci->id, "Split packet received from"
1281 " node %d ack=0x%02X spd=%d tcode=0x%X"
1282 " length=%d data=0x%08x ctx=%d",
1283 (d->spb[1]>>16)&0x3f,
1284 (d->spb[length/4-1]>>16)&0x1f,
1285 (d->spb[length/4-1]>>21)&0x3,
1286 tcode, length, d->spb[3], d->ctx);
1287
1288 ack = (((d->spb[length/4-1]>>16)&0x1f)
1289 == 0x11) ? 1 : 0;
1290
1291 hpsb_packet_received(ohci->host, d->spb,
1292 length, ack);
1293 }
1294 else
1295 PRINT(KERN_INFO, ohci->id,
1296 "Got phy packet ctx=%d ... discarded",
1297 d->ctx);
1298 }
1299 else {
1300 /*
1301 * We get one phy packet for each bus reset.
1302 * we know that from now on the bus topology may
1303 * have changed. Just ignore it for the moment
1304 */
1305 if (tcode != 0xE) {
1306 DBGMSG(ohci->id, "Packet received from node"
1307 " %d ack=0x%02X spd=%d tcode=0x%X"
1308 " length=%d data=0x%08x ctx=%d",
1309 (buf_ptr[1]>>16)&0x3f,
1310 (buf_ptr[length/4-1]>>16)&0x1f,
1311 (buf_ptr[length/4-1]>>21)&0x3,
1312 tcode, length, buf_ptr[3], d->ctx);
1313
1314 ack = (((buf_ptr[length/4-1]>>16)&0x1f)
1315 == 0x11) ? 1 : 0;
1316
1317 hpsb_packet_received(ohci->host, buf_ptr,
1318 length, ack);
1319 }
1320 else
1321 PRINT(KERN_INFO, ohci->id,
1322 "Got phy packet ctx=%d ... discarded",
1323 d->ctx);
1324 offset += length;
1325 buf_ptr += length/4;
1326 if (offset==d->buf_size) {
1327 insert_dma_buffer(d, idx);
1328 idx = (idx+1) % d->num_desc;
1329 buf_ptr = d->buf_cpu[idx];
1330 offset=0;
1331 }
1332 }
1333 rescount = d->prg_cpu[idx]->status & 0xffff;
1334 bytes_left = d->buf_size - rescount - offset;
1335
1336 }
1337
1338 d->buf_ind = idx;
1339 d->buf_offset = offset;
1340
1341 spin_unlock(&d->lock);
1342 }
1343
1344 /* Bottom half that processes sent packets */
1345 static void dma_trm_bh(void *data)
1346 {
1347 struct dma_trm_ctx *d = (struct dma_trm_ctx*)data;
1348 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1349 struct hpsb_packet *packet;
1350 unsigned long flags;
1351 u32 ack;
1352
1353 spin_lock_irqsave(&d->lock, flags);
1354
1355 if (d->fifo_first==NULL) {
1356 #if 0
1357 ohci1394_stop_context(ohci, d->ctrlClear,
1358 "Packet sent ack received but queue is empty");
1359 #endif
1360 spin_unlock_irqrestore(&d->lock, flags);
1361 return;
1362 }
1363
1364 while (d->fifo_first) {
1365 packet = d->fifo_first;
1366 if (packet->data_size)
1367 ack = d->prg_cpu[d->sent_ind]->end.status>>16;
1368 else
1369 ack = d->prg_cpu[d->sent_ind]->begin.status>>16;
1370
1371 if (ack==0)
1372 /* this packet hasn't been sent yet*/
1373 break;
1374
1375 DBGMSG(ohci->id,
1376 "Packet sent to node %d ack=0x%X spd=%d ctx=%d",
1377 (packet->header[0]>>16)&0x3f, ack&0x1f, (ack>>5)&0x3,
1378 d->ctx);
1379 hpsb_packet_sent(ohci->host, packet, ack&0xf);
1380
1381 if (packet->data_size)
1382 pci_unmap_single(ohci->dev,
1383 d->prg_cpu[d->sent_ind]->end.address,
1384 packet->data_size, PCI_DMA_TODEVICE);
1385
1386 d->sent_ind = (d->sent_ind+1)%d->num_desc;
1387 d->free_prgs++;
1388 d->fifo_first = d->fifo_first->xnext;
1389 }
1390 if (d->fifo_first==NULL) d->fifo_last=NULL;
1391
1392 dma_trm_flush(ohci, d);
1393
1394 spin_unlock_irqrestore(&d->lock, flags);
1395 }
1396
1397 static int free_dma_rcv_ctx(struct dma_rcv_ctx **d)
1398 {
1399 int i;
1400 struct ti_ohci *ohci;
1401
1402 if (*d==NULL) return -1;
1403
1404 ohci = (struct ti_ohci *)(*d)->ohci;
1405
1406 DBGMSG(ohci->id, "Freeing dma_rcv_ctx %d",(*d)->ctx);
1407
1408 ohci1394_stop_context(ohci, (*d)->ctrlClear, NULL);
1409
1410 if ((*d)->buf_cpu) {
1411 for (i=0; i<(*d)->num_desc; i++)
1412 if ((*d)->buf_cpu[i] && (*d)->buf_bus[i])
1413 pci_free_consistent(
1414 ohci->dev, (*d)->buf_size,
1415 (*d)->buf_cpu[i], (*d)->buf_bus[i]);
1416 kfree((*d)->buf_cpu);
1417 kfree((*d)->buf_bus);
1418 }
1419 if ((*d)->prg_cpu) {
1420 for (i=0; i<(*d)->num_desc; i++)
1421 if ((*d)->prg_cpu[i] && (*d)->prg_bus[i])
1422 pci_free_consistent(
1423 ohci->dev, sizeof(struct dma_cmd),
1424 (*d)->prg_cpu[i], (*d)->prg_bus[i]);
1425 kfree((*d)->prg_cpu);
1426 kfree((*d)->prg_bus);
1427 }
1428 if ((*d)->spb) kfree((*d)->spb);
1429
1430 kfree(*d);
1431 *d = NULL;
1432
1433 return 0;
1434 }
1435
1436 static struct dma_rcv_ctx *
1437 alloc_dma_rcv_ctx(struct ti_ohci *ohci, int ctx, int num_desc,
1438 int buf_size, int split_buf_size,
1439 int ctrlSet, int ctrlClear, int cmdPtr)
1440 {
1441 struct dma_rcv_ctx *d=NULL;
1442 int i;
1443
1444 d = (struct dma_rcv_ctx *)kmalloc(sizeof(struct dma_rcv_ctx),
1445 GFP_KERNEL);
1446
1447 if (d==NULL) {
1448 PRINT(KERN_ERR, ohci->id, "failed to allocate dma_rcv_ctx");
1449 return NULL;
1450 }
1451
1452 d->ohci = (void *)ohci;
1453 d->ctx = ctx;
1454
1455 d->num_desc = num_desc;
1456 d->buf_size = buf_size;
1457 d->split_buf_size = split_buf_size;
1458 d->ctrlSet = ctrlSet;
1459 d->ctrlClear = ctrlClear;
1460 d->cmdPtr = cmdPtr;
1461
1462 d->buf_cpu = NULL;
1463 d->buf_bus = NULL;
1464 d->prg_cpu = NULL;
1465 d->prg_bus = NULL;
1466 d->spb = NULL;
1467
1468 d->buf_cpu = kmalloc(d->num_desc * sizeof(quadlet_t*), GFP_KERNEL);
1469 d->buf_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1470
1471 if (d->buf_cpu == NULL || d->buf_bus == NULL) {
1472 PRINT(KERN_ERR, ohci->id, "failed to allocate dma buffer");
1473 free_dma_rcv_ctx(&d);
1474 return NULL;
1475 }
1476 memset(d->buf_cpu, 0, d->num_desc * sizeof(quadlet_t*));
1477 memset(d->buf_bus, 0, d->num_desc * sizeof(dma_addr_t));
1478
1479 d->prg_cpu = kmalloc(d->num_desc * sizeof(struct dma_cmd*),
1480 GFP_KERNEL);
1481 d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1482
1483 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
1484 PRINT(KERN_ERR, ohci->id, "failed to allocate dma prg");
1485 free_dma_rcv_ctx(&d);
1486 return NULL;
1487 }
1488 memset(d->prg_cpu, 0, d->num_desc * sizeof(struct dma_cmd*));
1489 memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
1490
1491 d->spb = kmalloc(d->split_buf_size, GFP_KERNEL);
1492
1493 if (d->spb == NULL) {
1494 PRINT(KERN_ERR, ohci->id, "failed to allocate split buffer");
1495 free_dma_rcv_ctx(&d);
1496 return NULL;
1497 }
1498
1499 for (i=0; i<d->num_desc; i++) {
1500 d->buf_cpu[i] = pci_alloc_consistent(ohci->dev,
1501 d->buf_size,
1502 d->buf_bus+i);
1503
1504 if (d->buf_cpu[i] != NULL) {
1505 memset(d->buf_cpu[i], 0, d->buf_size);
1506 } else {
1507 PRINT(KERN_ERR, ohci->id,
1508 "failed to allocate dma buffer");
1509 free_dma_rcv_ctx(&d);
1510 return NULL;
1511 }
1512
1513
1514 d->prg_cpu[i] = pci_alloc_consistent(ohci->dev,
1515 sizeof(struct dma_cmd),
1516 d->prg_bus+i);
1517
1518 if (d->prg_cpu[i] != NULL) {
1519 memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd));
1520 } else {
1521 PRINT(KERN_ERR, ohci->id,
1522 "failed to allocate dma prg");
1523 free_dma_rcv_ctx(&d);
1524 return NULL;
1525 }
1526 }
1527
1528 spin_lock_init(&d->lock);
1529
1530 /* initialize bottom handler */
1531 d->task.sync = 0;
1532 d->task.next = NULL;
1533 d->task.routine = dma_rcv_bh;
1534 d->task.data = (void*)d;
1535
1536 return d;
1537 }
1538
1539 static int free_dma_trm_ctx(struct dma_trm_ctx **d)
1540 {
1541 struct ti_ohci *ohci;
1542 int i;
1543
1544 if (*d==NULL) return -1;
1545
1546 ohci = (struct ti_ohci *)(*d)->ohci;
1547
1548 DBGMSG(ohci->id, "Freeing dma_trm_ctx %d",(*d)->ctx);
1549
1550 ohci1394_stop_context(ohci, (*d)->ctrlClear, NULL);
1551
1552 if ((*d)->prg_cpu) {
1553 for (i=0; i<(*d)->num_desc; i++)
1554 if ((*d)->prg_cpu[i] && (*d)->prg_bus[i])
1555 pci_free_consistent(
1556 ohci->dev, sizeof(struct at_dma_prg),
1557 (*d)->prg_cpu[i], (*d)->prg_bus[i]);
1558 kfree((*d)->prg_cpu);
1559 kfree((*d)->prg_bus);
1560 }
1561
1562 kfree(*d);
1563 *d = NULL;
1564 return 0;
1565 }
1566
1567 static struct dma_trm_ctx *
1568 alloc_dma_trm_ctx(struct ti_ohci *ohci, int ctx, int num_desc,
1569 int ctrlSet, int ctrlClear, int cmdPtr)
1570 {
1571 struct dma_trm_ctx *d=NULL;
1572 int i;
1573
1574 d = (struct dma_trm_ctx *)kmalloc(sizeof(struct dma_trm_ctx),
1575 GFP_KERNEL);
1576
1577 if (d==NULL) {
1578 PRINT(KERN_ERR, ohci->id, "failed to allocate dma_trm_ctx");
1579 return NULL;
1580 }
1581
1582 d->ohci = (void *)ohci;
1583 d->ctx = ctx;
1584 d->num_desc = num_desc;
1585 d->ctrlSet = ctrlSet;
1586 d->ctrlClear = ctrlClear;
1587 d->cmdPtr = cmdPtr;
1588 d->prg_cpu = NULL;
1589 d->prg_bus = NULL;
1590
1591 d->prg_cpu = kmalloc(d->num_desc * sizeof(struct at_dma_prg*),
1592 GFP_KERNEL);
1593 d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1594
1595 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
1596 PRINT(KERN_ERR, ohci->id, "failed to allocate at dma prg");
1597 free_dma_trm_ctx(&d);
1598 return NULL;
1599 }
1600 memset(d->prg_cpu, 0, d->num_desc * sizeof(struct at_dma_prg*));
1601 memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
1602
1603 for (i=0; i<d->num_desc; i++) {
1604 d->prg_cpu[i] = pci_alloc_consistent(ohci->dev,
1605 sizeof(struct at_dma_prg),
1606 d->prg_bus+i);
1607
1608 if (d->prg_cpu[i] != NULL) {
1609 memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg));
1610 } else {
1611 PRINT(KERN_ERR, ohci->id,
1612 "failed to allocate at dma prg");
1613 free_dma_trm_ctx(&d);
1614 return NULL;
1615 }
1616 }
1617
1618 spin_lock_init(&d->lock);
1619
1620 /* initialize bottom handler */
1621 d->task.routine = dma_trm_bh;
1622 d->task.data = (void*)d;
1623
1624 return d;
1625 }
1626
1627 static u32 ohci_crc16(unsigned *data, int length)
1628 {
1629 int check=0, i;
1630 int shift, sum, next=0;
1631
1632 for (i = length; i; i--) {
1633 for (next = check, shift = 28; shift >= 0; shift -= 4 ) {
1634 sum = ((next >> 12) ^ (*data >> shift)) & 0xf;
1635 next = (next << 4) ^ (sum << 12) ^ (sum << 5) ^ (sum);
1636 }
1637 check = next & 0xffff;
1638 data++;
1639 }
1640
1641 return check;
1642 }
1643
1644 static void ohci_init_config_rom(struct ti_ohci *ohci)
1645 {
1646 int i;
1647
1648 ohci_csr_rom[3] = reg_read(ohci, OHCI1394_GUIDHi);
1649 ohci_csr_rom[4] = reg_read(ohci, OHCI1394_GUIDLo);
1650
1651 ohci_csr_rom[0] = 0x04040000 | ohci_crc16(ohci_csr_rom+1, 4);
1652
1653 for (i=0;i<sizeof(ohci_csr_rom)/4;i++)
1654 ohci->csr_config_rom_cpu[i] = cpu_to_be32(ohci_csr_rom[i]);
1655 }
1656
1657 static int add_card(struct pci_dev *dev)
1658 {
1659 struct ti_ohci *ohci; /* shortcut to currently handled device */
1660
1661 if (num_of_cards == MAX_OHCI1394_CARDS) {
1662 PRINT_G(KERN_WARNING, "cannot handle more than %d cards. "
1663 "Adjust MAX_OHCI1394_CARDS in ti_ohci1394.h.",
1664 MAX_OHCI1394_CARDS);
1665 return 1;
1666 }
1667
1668 if (pci_enable_device(dev)) {
1669 PRINT_G(KERN_NOTICE, "failed to enable OHCI hardware %d",
1670 num_of_cards);
1671 return 1;
1672 }
1673 pci_set_master(dev);
1674
1675 ohci = &cards[num_of_cards++];
1676
1677 ohci->id = num_of_cards-1;
1678 ohci->dev = dev;
1679
1680 ohci->state = 0;
1681
1682 /* csr_config rom allocation */
1683 ohci->csr_config_rom_cpu =
1684 pci_alloc_consistent(ohci->dev, sizeof(ohci_csr_rom),
1685 &ohci->csr_config_rom_bus);
1686 if (ohci->csr_config_rom_cpu == NULL) {
1687 FAIL("failed to allocate buffer config rom");
1688 }
1689
1690 DBGMSG(ohci->id, "The 1st byte at offset 0x404 is: 0x%02x",
1691 *((char *)ohci->csr_config_rom_cpu+4));
1692
1693 /*
1694 * self-id dma buffer allocation
1695 * FIXME: some early chips may need 8KB alignment for the
1696 * selfid buffer
1697 */
1698 ohci->selfid_buf_cpu =
1699 pci_alloc_consistent(ohci->dev, 2048, &ohci->selfid_buf_bus);
1700 if (ohci->selfid_buf_cpu == NULL) {
1701 FAIL("failed to allocate DMA buffer for self-id packets");
1702 }
1703 if ((unsigned long)ohci->selfid_buf_cpu & 0xfff)
1704 PRINT(KERN_INFO, ohci->id, "Selfid buffer %p not aligned on "
1705 "8Kb boundary", ohci->selfid_buf_cpu);
1706
1707 ohci->ar_req_context =
1708 alloc_dma_rcv_ctx(ohci, 0, AR_REQ_NUM_DESC,
1709 AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE,
1710 OHCI1394_AsReqRcvContextControlSet,
1711 OHCI1394_AsReqRcvContextControlClear,
1712 OHCI1394_AsReqRcvCommandPtr);
1713
1714 if (ohci->ar_req_context == NULL) return 1;
1715
1716 ohci->ar_resp_context =
1717 alloc_dma_rcv_ctx(ohci, 1, AR_RESP_NUM_DESC,
1718 AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE,
1719 OHCI1394_AsRspRcvContextControlSet,
1720 OHCI1394_AsRspRcvContextControlClear,
1721 OHCI1394_AsRspRcvCommandPtr);
1722
1723 if (ohci->ar_resp_context == NULL) {
1724 FAIL("failed to allocate AR Resp context");
1725 }
1726
1727 ohci->at_req_context =
1728 alloc_dma_trm_ctx(ohci, 0, AT_REQ_NUM_DESC,
1729 OHCI1394_AsReqTrContextControlSet,
1730 OHCI1394_AsReqTrContextControlClear,
1731 OHCI1394_AsReqTrCommandPtr);
1732
1733 if (ohci->at_req_context == NULL) {
1734 FAIL("failed to allocate AT Req context");
1735 }
1736
1737 ohci->at_resp_context =
1738 alloc_dma_trm_ctx(ohci, 1, AT_RESP_NUM_DESC,
1739 OHCI1394_AsRspTrContextControlSet,
1740 OHCI1394_AsRspTrContextControlClear,
1741 OHCI1394_AsRspTrCommandPtr);
1742
1743 if (ohci->at_resp_context == NULL) {
1744 FAIL("failed to allocate AT Resp context");
1745 }
1746
1747 ohci->ir_context =
1748 alloc_dma_rcv_ctx(ohci, 2, IR_NUM_DESC,
1749 IR_BUF_SIZE, IR_SPLIT_BUF_SIZE,
1750 OHCI1394_IsoRcvContextControlSet,
1751 OHCI1394_IsoRcvContextControlClear,
1752 OHCI1394_IsoRcvCommandPtr);
1753
1754 if (ohci->ir_context == NULL) {
1755 FAIL("failed to allocate IR context");
1756 }
1757
1758 ohci->IR_channel_usage= 0x0000000000000000;
1759 spin_lock_init(&ohci->IR_channel_lock);
1760
1761 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13)
1762 ohci->registers = ioremap_nocache(dev->base_address[0],
1763 OHCI1394_REGISTER_SIZE);
1764 #else
1765 ohci->registers = ioremap_nocache(dev->resource[0].start,
1766 OHCI1394_REGISTER_SIZE);
1767 #endif
1768
1769 if (ohci->registers == NULL) {
1770 FAIL("failed to remap registers - card not accessible");
1771 }
1772
1773 PRINT(KERN_INFO, ohci->id, "remapped memory spaces reg 0x%p",
1774 ohci->registers);
1775
1776 if (!request_irq(dev->irq, ohci_irq_handler, SA_SHIRQ,
1777 OHCI1394_DRIVER_NAME, ohci)) {
1778 PRINT(KERN_INFO, ohci->id, "allocated interrupt %d", dev->irq);
1779 } else {
1780 FAIL("failed to allocate shared interrupt %d", dev->irq);
1781 }
1782
1783 ohci_init_config_rom(ohci);
1784
1785 return 0;
1786 #undef FAIL
1787 }
1788
1789 #ifdef CONFIG_PROC_FS
1790
1791 #define SR(fmt, reg0, reg1, reg2)\
1792 p += sprintf(p,fmt,reg_read(ohci, reg0),\
1793 reg_read(ohci, reg1),reg_read(ohci, reg2));
1794
1795 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
1796 static int ohci_get_status(char *buf)
1797 #else
1798 int ohci_get_info(char *buf, char **start, off_t fpos,
1799 int length, int dummy)
1800 #endif
1801 {
1802 struct ti_ohci *ohci=&cards[0];
1803 struct hpsb_host *host=ohci->host;
1804 char *p=buf;
1805 //unsigned char phyreg;
1806 //int i, nports;
1807 int i;
1808
1809 struct dma_rcv_ctx *d=NULL;
1810 struct dma_trm_ctx *dt=NULL;
1811
1812 p += sprintf(p,"IEEE-1394 OHCI Driver status report:\n");
1813 p += sprintf(p," bus number: 0x%x Node ID: 0x%x\n",
1814 (reg_read(ohci, OHCI1394_NodeID) & 0xFFC0) >> 6,
1815 reg_read(ohci, OHCI1394_NodeID)&0x3f);
1816 #if 0
1817 p += sprintf(p," hardware version %d.%d GUID_ROM is %s\n\n",
1818 (reg_read(ohci, OHCI1394_Version) & 0xFF0000) >>16,
1819 reg_read(ohci, OHCI1394_Version) & 0xFF,
1820 (reg_read(ohci, OHCI1394_Version) & 0x01000000)
1821 ? "set" : "clear");
1822 #endif
1823 p += sprintf(p,"\n### Host data ###\n");
1824 p += sprintf(p,"node_count: %8d ",host->node_count);
1825 p += sprintf(p,"node_id : %08X\n",host->node_id);
1826 p += sprintf(p,"irm_id : %08X ",host->irm_id);
1827 p += sprintf(p,"busmgr_id : %08X\n",host->busmgr_id);
1828 p += sprintf(p,"%s %s %s\n",
1829 host->initialized ? "initialized" : "",
1830 host->in_bus_reset ? "in_bus_reset" : "",
1831 host->attempt_root ? "attempt_root" : "");
1832 p += sprintf(p,"%s %s %s %s\n",
1833 host->is_root ? "root" : "",
1834 host->is_cycmst ? "cycle_master" : "",
1835 host->is_irm ? "iso_res_mgr" : "",
1836 host->is_busmgr ? "bus_mgr" : "");
1837
1838 p += sprintf(p,"\n---Iso Receive DMA---\n");
1839
1840 d = ohci->ir_context;
1841 #if 0
1842 for (i=0; i<d->num_desc; i++) {
1843 p += sprintf(p, "IR buf[%d] : %p prg[%d]: %p\n",
1844 i, d->buf[i], i, d->prg[i]);
1845 }
1846 #endif
1847 p += sprintf(p, "Current buf: %d offset: %d\n",
1848 d->buf_ind,d->buf_offset);
1849
1850 p += sprintf(p,"\n---Async Receive DMA---\n");
1851 d = ohci->ar_req_context;
1852 #if 0
1853 for (i=0; i<d->num_desc; i++) {
1854 p += sprintf(p, "AR req buf[%d] : %p prg[%d]: %p\n",
1855 i, d->buf[i], i, d->prg[i]);
1856 }
1857 #endif
1858 p += sprintf(p, "Ar req current buf: %d offset: %d\n",
1859 d->buf_ind,d->buf_offset);
1860
1861 d = ohci->ar_resp_context;
1862 #if 0
1863 for (i=0; i<d->num_desc; i++) {
1864 p += sprintf(p, "AR resp buf[%d] : %p prg[%d]: %p\n",
1865 i, d->buf[i], i, d->prg[i]);
1866 }
1867 #endif
1868 p += sprintf(p, "AR resp current buf: %d offset: %d\n",
1869 d->buf_ind,d->buf_offset);
1870
1871 p += sprintf(p,"\n---Async Transmit DMA---\n");
1872 dt = ohci->at_req_context;
1873 p += sprintf(p, "AT req prg: %d sent: %d free: %d branchAddrPtr: %p\n",
1874 dt->prg_ind, dt->sent_ind, dt->free_prgs,
1875 dt->branchAddrPtr);
1876 p += sprintf(p, "AT req queue: first: %p last: %p\n",
1877 dt->fifo_first, dt->fifo_last);
1878 dt = ohci->at_resp_context;
1879 #if 0
1880 for (i=0; i<dt->num_desc; i++) {
1881 p += sprintf(p, "------- AT resp prg[%02d] ------\n",i);
1882 p += sprintf(p, "%p: control : %08x\n",
1883 &(dt->prg[i].begin.control),
1884 dt->prg[i].begin.control);
1885 p += sprintf(p, "%p: address : %08x\n",
1886 &(dt->prg[i].begin.address),
1887 dt->prg[i].begin.address);
1888 p += sprintf(p, "%p: brancAddr: %08x\n",
1889 &(dt->prg[i].begin.branchAddress),
1890 dt->prg[i].begin.branchAddress);
1891 p += sprintf(p, "%p: status : %08x\n",
1892 &(dt->prg[i].begin.status),
1893 dt->prg[i].begin.status);
1894 p += sprintf(p, "%p: header[0]: %08x\n",
1895 &(dt->prg[i].data[0]),
1896 dt->prg[i].data[0]);
1897 p += sprintf(p, "%p: header[1]: %08x\n",
1898 &(dt->prg[i].data[1]),
1899 dt->prg[i].data[1]);
1900 p += sprintf(p, "%p: header[2]: %08x\n",
1901 &(dt->prg[i].data[2]),
1902 dt->prg[i].data[2]);
1903 p += sprintf(p, "%p: header[3]: %08x\n",
1904 &(dt->prg[i].data[3]),
1905 dt->prg[i].data[3]);
1906 p += sprintf(p, "%p: control : %08x\n",
1907 &(dt->prg[i].end.control),
1908 dt->prg[i].end.control);
1909 p += sprintf(p, "%p: address : %08x\n",
1910 &(dt->prg[i].end.address),
1911 dt->prg[i].end.address);
1912 p += sprintf(p, "%p: brancAddr: %08x\n",
1913 &(dt->prg[i].end.branchAddress),
1914 dt->prg[i].end.branchAddress);
1915 p += sprintf(p, "%p: status : %08x\n",
1916 &(dt->prg[i].end.status),
1917 dt->prg[i].end.status);
1918 }
1919 #endif
1920 p += sprintf(p, "AR resp prg: %d sent: %d free: %d"
1921 " branchAddrPtr: %p\n",
1922 dt->prg_ind, dt->sent_ind, dt->free_prgs,
1923 dt->branchAddrPtr);
1924 p += sprintf(p, "AT resp queue: first: %p last: %p\n",
1925 dt->fifo_first, dt->fifo_last);
1926
1927 /* ----- Register Dump ----- */
1928 p += sprintf(p,"\n### HC Register dump ###\n");
1929 SR("Version : %08x GUID_ROM : %08x ATRetries : %08x\n",
1930 OHCI1394_Version, OHCI1394_GUID_ROM, OHCI1394_ATRetries);
1931 SR("CSRData : %08x CSRCompData : %08x CSRControl : %08x\n",
1932 OHCI1394_CSRData, OHCI1394_CSRCompareData, OHCI1394_CSRControl);
1933 SR("ConfigROMhdr: %08x BusID : %08x BusOptions : %08x\n",
1934 OHCI1394_ConfigROMhdr, OHCI1394_BusID, OHCI1394_BusOptions);
1935 SR("GUIDHi : %08x GUIDLo : %08x ConfigROMmap: %08x\n",
1936 OHCI1394_GUIDHi, OHCI1394_GUIDLo, OHCI1394_ConfigROMmap);
1937 SR("PtdWrAddrLo : %08x PtdWrAddrHi : %08x VendorID : %08x\n",
1938 OHCI1394_PostedWriteAddressLo, OHCI1394_PostedWriteAddressHi,
1939 OHCI1394_VendorID);
1940 SR("HCControl : %08x SelfIDBuffer: %08x SelfIDCount : %08x\n",
1941 OHCI1394_HCControlSet, OHCI1394_SelfIDBuffer, OHCI1394_SelfIDCount);
1942 SR("IRMuChMaskHi: %08x IRMuChMaskLo: %08x IntEvent : %08x\n",
1943 OHCI1394_IRMultiChanMaskHiSet, OHCI1394_IRMultiChanMaskLoSet,
1944 OHCI1394_IntEventSet);
1945 SR("IntMask : %08x IsoXmIntEvnt: %08x IsoXmIntMask: %08x\n",
1946 OHCI1394_IntMaskSet, OHCI1394_IsoXmitIntEventSet,
1947 OHCI1394_IsoXmitIntMaskSet);
1948 SR("IsoRcvIntEvt: %08x IsoRcvIntMsk: %08x FairnessCtrl: %08x\n",
1949 OHCI1394_IsoRecvIntEventSet, OHCI1394_IsoRecvIntMaskSet,
1950 OHCI1394_FairnessControl);
1951 SR("LinkControl : %08x NodeID : %08x PhyControl : %08x\n",
1952 OHCI1394_LinkControlSet, OHCI1394_NodeID, OHCI1394_PhyControl);
1953 SR("IsoCyclTimer: %08x AsRqFilterHi: %08x AsRqFilterLo: %08x\n",
1954 OHCI1394_IsochronousCycleTimer,
1955 OHCI1394_AsReqFilterHiSet, OHCI1394_AsReqFilterLoSet);
1956 SR("PhyReqFiltHi: %08x PhyReqFiltLo: %08x PhyUpperBnd : %08x\n",
1957 OHCI1394_PhyReqFilterHiSet, OHCI1394_PhyReqFilterLoSet,
1958 OHCI1394_PhyUpperBound);
1959 SR("AsRqTrCxtCtl: %08x AsRqTrCmdPtr: %08x AsRsTrCtxCtl: %08x\n",
1960 OHCI1394_AsReqTrContextControlSet, OHCI1394_AsReqTrCommandPtr,
1961 OHCI1394_AsRspTrContextControlSet);
1962 SR("AsRsTrCmdPtr: %08x AsRqRvCtxCtl: %08x AsRqRvCmdPtr: %08x\n",
1963 OHCI1394_AsRspTrCommandPtr, OHCI1394_AsReqRcvContextControlSet,
1964 OHCI1394_AsReqRcvCommandPtr);
1965 SR("AsRsRvCtxCtl: %08x AsRsRvCmdPtr: %08x IntEvent : %08x\n",
1966 OHCI1394_AsRspRcvContextControlSet, OHCI1394_AsRspRcvCommandPtr,
1967 OHCI1394_IntEventSet);
1968 for (i=0;i<ohci->nb_iso_rcv_ctx;i++) {
1969 p += sprintf(p,"IsoRCtxCtl%02d: %08x IsoRCmdPtr%02d: %08x"
1970 " IsoRCxtMch%02d: %08x\n", i,
1971 reg_read(ohci,
1972 OHCI1394_IsoRcvContextControlSet+32*i),
1973 i,reg_read(ohci, OHCI1394_IsoRcvCommandPtr+32*i),
1974 i,reg_read(ohci,
1975 OHCI1394_IsoRcvContextMatch+32*i));
1976 }
1977 for (i=0;i<ohci->nb_iso_xmit_ctx;i++) {
1978 p += sprintf(p,"IsoTCtxCtl%02d: %08x IsoTCmdPtr%02d: %08x\n",
1979 i,
1980 reg_read(ohci,
1981 OHCI1394_IsoXmitContextControlSet+32*i),
1982 i,reg_read(ohci,OHCI1394_IsoXmitCommandPtr+32*i));
1983 }
1984
1985 #if 0
1986 p += sprintf(p,"\n### Phy Register dump ###\n");
1987 phyreg=get_phy_reg(ohci,1);
1988 p += sprintf(p,"offset: %d val: 0x%02x -> RHB: %d"
1989 "IBR: %d Gap_count: %d\n",
1990 1,phyreg,(phyreg&0x80) != 0,
1991 (phyreg&0x40) !=0, phyreg&0x3f);
1992 phyreg=get_phy_reg(ohci,2);
1993 nports=phyreg&0x1f;
1994 p += sprintf(p,"offset: %d val: 0x%02x -> SPD: %d"
1995 " E : %d Ports : %2d\n",
1996 2,phyreg, (phyreg&0xC0)>>6, (phyreg&0x20) !=0, nports);
1997 for (i=0;i<nports;i++) {
1998 phyreg=get_phy_reg(ohci,3+i);
1999 p += sprintf(p,"offset: %d val: 0x%02x -> [port %d]"
2000 " TPA: %d TPB: %d | %s %s\n",
2001 3+i,phyreg,
2002 i, (phyreg&0xC0)>>6, (phyreg&0x30)>>4,
2003 (phyreg&0x08) ? "child" : "parent",
2004 (phyreg&0x04) ? "connected" : "disconnected");
2005 }
2006 phyreg=get_phy_reg(ohci,3+i);
2007 p += sprintf(p,"offset: %d val: 0x%02x -> ENV: %s Reg_count: %d\n",
2008 3+i,phyreg,
2009 (((phyreg&0xC0)>>6)==0) ? "backplane" :
2010 (((phyreg&0xC0)>>6)==1) ? "cable" : "reserved",
2011 phyreg&0x3f);
2012 #endif
2013
2014 return p - buf;
2015 }
2016
2017 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
2018 static int ohci1394_read_proc(char *page, char **start, off_t off,
2019 int count, int *eof, void *data)
2020 {
2021 int len = ohci_get_status(page);
2022 if (len <= off+count) *eof = 1;
2023 *start = page + off;
2024 len -= off;
2025 if (len>count) len = count;
2026 if (len<0) len = 0;
2027 return len;
2028 }
2029 #else
2030 struct proc_dir_entry ohci_proc_entry =
2031 {
2032 0, /* Inode number - dynamic */
2033 8, /* Length of the file name */
2034 "ohci1394", /* The file name */
2035 S_IFREG | S_IRUGO, /* File mode */
2036 1, /* Number of links */
2037 0, 0, /* The uid and gid for the file */
2038 0, /* The size of the file reported by ls. */
2039 NULL, /* functions which can be done on the inode */
2040 ohci_get_info, /* The read function for this file */
2041 NULL
2042 };
2043 #endif /* LINUX_VERSION_CODE */
2044 #endif /* CONFIG_PROC_FS */
2045
2046 static void remove_card(struct ti_ohci *ohci)
2047 {
2048 /*
2049 * Reset the board properly before leaving
2050 * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de>
2051 */
2052 ohci_soft_reset(ohci);
2053
2054 /* Free AR dma */
2055 free_dma_rcv_ctx(&ohci->ar_req_context);
2056 free_dma_rcv_ctx(&ohci->ar_resp_context);
2057
2058 /* Free AT dma */
2059 free_dma_trm_ctx(&ohci->at_req_context);
2060 free_dma_trm_ctx(&ohci->at_resp_context);
2061
2062 /* Free IR dma */
2063 free_dma_rcv_ctx(&ohci->ir_context);
2064
2065 /* Free self-id buffer */
2066 if (ohci->selfid_buf_cpu)
2067 pci_free_consistent(ohci->dev, 2048,
2068 ohci->selfid_buf_cpu,
2069 ohci->selfid_buf_bus);
2070
2071 /* Free config rom */
2072 if (ohci->csr_config_rom_cpu)
2073 pci_free_consistent(ohci->dev, sizeof(ohci_csr_rom),
2074 ohci->csr_config_rom_cpu,
2075 ohci->csr_config_rom_bus);
2076
2077 /* Free the IRQ */
2078 free_irq(ohci->dev->irq, ohci);
2079
2080 if (ohci->registers)
2081 iounmap(ohci->registers);
2082
2083 ohci->state = 0;
2084 }
2085
2086 static int init_driver()
2087 {
2088 struct pci_dev *dev = NULL;
2089 int success = 0;
2090 int i;
2091
2092 if (num_of_cards) {
2093 PRINT_G(KERN_DEBUG, __PRETTY_FUNCTION__ " called again");
2094 return 0;
2095 }
2096
2097 PRINT_G(KERN_INFO, "looking for Ohci1394 cards");
2098
2099 for (i = 0; supported_chips[i][0] != -1; i++) {
2100 while ((dev = pci_find_device(supported_chips[i][0],
2101 supported_chips[i][1], dev))
2102 != NULL) {
2103 if (add_card(dev) == 0) {
2104 success = 1;
2105 }
2106 }
2107 }
2108
2109 if (success == 0) {
2110 PRINT_G(KERN_WARNING, "no operable Ohci1394 cards found");
2111 return -ENXIO;
2112 }
2113
2114 #ifdef CONFIG_PROC_FS
2115 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
2116 create_proc_read_entry ("ohci1394", 0, NULL, ohci1394_read_proc, NULL);
2117 #else
2118 if (proc_register(&proc_root, &ohci_proc_entry)) {
2119 PRINT_G(KERN_ERR, "unable to register proc file\n");
2120 return -EIO;
2121 }
2122 #endif
2123 #endif
2124 return 0;
2125 }
2126
2127 static size_t get_ohci_rom(struct hpsb_host *host, const quadlet_t **ptr)
2128 {
2129 struct ti_ohci *ohci=host->hostdata;
2130
2131 DBGMSG(ohci->id, "request csr_rom address: %08X",
2132 (u32)ohci->csr_config_rom_cpu);
2133
2134 *ptr = ohci->csr_config_rom_cpu;
2135 return sizeof(ohci_csr_rom);
2136 }
2137
2138 struct hpsb_host_template *get_ohci_template(void)
2139 {
2140 static struct hpsb_host_template tmpl;
2141 static int initialized = 0;
2142
2143 if (!initialized) {
2144 /* Initialize by field names so that a template structure
2145 * reorganization does not influence this code. */
2146 tmpl.name = "ohci1394";
2147
2148 tmpl.detect_hosts = ohci_detect;
2149 tmpl.initialize_host = ohci_initialize;
2150 tmpl.release_host = ohci_remove;
2151 tmpl.get_rom = get_ohci_rom;
2152 tmpl.transmit_packet = ohci_transmit;
2153 tmpl.devctl = ohci_devctl;
2154
2155 initialized = 1;
2156 }
2157
2158 return &tmpl;
2159 }
2160
2161 void ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg)
2162 {
2163 int i=0;
2164
2165 /* stop the channel program if it's still running */
2166 reg_write(ohci, reg, 0x8000);
2167
2168 /* Wait until it effectively stops */
2169 while (reg_read(ohci, reg) & 0x400) {
2170 i++;
2171 if (i>5000) {
2172 PRINT(KERN_ERR, ohci->id,
2173 "runaway loop while stopping context...");
2174 break;
2175 }
2176 }
2177 if (msg) PRINT(KERN_ERR, ohci->id, "%s\n dma prg stopped\n", msg);
2178 }
2179
2180 struct ti_ohci *ohci1394_get_struct(int card_num)
2181 {
2182 if (card_num>=0 && card_num<num_of_cards)
2183 return &cards[card_num];
2184 return NULL;
2185 }
2186
2187 int ohci1394_register_video(struct ti_ohci *ohci,
2188 struct video_template *tmpl)
2189 {
2190 if (ohci->video_tmpl)
2191 return -ENFILE;
2192 ohci->video_tmpl = tmpl;
2193 MOD_INC_USE_COUNT;
2194 return 0;
2195 }
2196
2197 void ohci1394_unregister_video(struct ti_ohci *ohci,
2198 struct video_template *tmpl)
2199 {
2200 if (ohci->video_tmpl != tmpl) {
2201 PRINT(KERN_ERR, ohci->id,
2202 "Trying to unregister wrong video device");
2203 }
2204 else {
2205 ohci->video_tmpl = NULL;
2206 MOD_DEC_USE_COUNT;
2207 }
2208 }
2209
2210 #if 0
2211 int ohci_compare_swap(struct ti_ohci *ohci, quadlet_t *data,
2212 quadlet_t compare, int sel)
2213 {
2214 int timeout = 255;
2215 reg_write(ohci, OHCI1394_CSRData, *data);
2216 reg_write(ohci, OHCI1394_CSRCompareData, compare);
2217 reg_write(ohci, OHCI1394_CSRControl, sel);
2218 while(!(reg_read(ohci, OHCI1394_CSRControl)&0x80000000)) {
2219 if (timeout--) {
2220 PRINT(KERN_INFO, ohci->id, "request_channel timeout");
2221 return -1;
2222 }
2223 }
2224 *data = reg_read(ohci, OHCI1394_CSRData);
2225 return 0;
2226 }
2227
2228 int ohci1394_request_channel(struct ti_ohci *ohci, int channel)
2229 {
2230 int csrSel;
2231 quadlet_t chan, data1=0, data2=0;
2232 int timeout = 32;
2233
2234 if (channel<32) {
2235 chan = 1<<channel;
2236 csrSel = 2;
2237 }
2238 else {
2239 chan = 1<<(channel-32);
2240 csrSel = 3;
2241 }
2242 if (ohci_compare_swap(ohci, &data1, 0, csrSel)<0) {
2243 PRINT(KERN_INFO, ohci->id, "request_channel timeout");
2244 return -1;
2245 }
2246 while (timeout--) {
2247 if (data1 & chan) {
2248 PRINT(KERN_INFO, ohci->id,
2249 "request channel %d failed", channel);
2250 return -1;
2251 }
2252 data2 = data1;
2253 data1 |= chan;
2254 if (ohci_compare_swap(ohci, &data1, data2, csrSel)<0) {
2255 PRINT(KERN_INFO, ohci->id, "request_channel timeout");
2256 return -1;
2257 }
2258 if (data1==data2) {
2259 PRINT(KERN_INFO, ohci->id,
2260 "request channel %d succeded", channel);
2261 return 0;
2262 }
2263 }
2264 PRINT(KERN_INFO, ohci->id, "request channel %d failed", channel);
2265 return -1;
2266 }
2267 #endif
2268
2269 EXPORT_SYMBOL(ohci1394_stop_context);
2270 EXPORT_SYMBOL(ohci1394_get_struct);
2271 EXPORT_SYMBOL(ohci1394_register_video);
2272 EXPORT_SYMBOL(ohci1394_unregister_video);
2273
2274 #ifdef MODULE
2275
2276 /* EXPORT_NO_SYMBOLS; */
2277
2278 MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
2279 MODULE_DESCRIPTION("driver for PCI Ohci IEEE-1394 controller");
2280 MODULE_SUPPORTED_DEVICE("ohci1394");
2281
2282 void cleanup_module(void)
2283 {
2284 hpsb_unregister_lowlevel(get_ohci_template());
2285 #ifdef CONFIG_PROC_FS
2286 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
2287 remove_proc_entry ("ohci1394", NULL);
2288 #else
2289 proc_unregister(&proc_root, ohci_proc_entry.low_ino);
2290 #endif
2291 #endif
2292
2293 PRINT_G(KERN_INFO, "removed " OHCI1394_DRIVER_NAME " module\n");
2294 }
2295
2296 int init_module(void)
2297 {
2298 memset(cards, 0, MAX_OHCI1394_CARDS * sizeof (struct ti_ohci));
2299
2300 if (hpsb_register_lowlevel(get_ohci_template())) {
2301 PRINT_G(KERN_ERR, "registering failed\n");
2302 return -ENXIO;
2303 }
2304 return 0;
2305 }
2306
2307 #endif /* MODULE */
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