drivers/ieee1394/csr.h

   1
   2 #ifndef _IEEE1394_CSR_H
   3 #define _IEEE1394_CSR_H
   4
   5 #define CSR_REGISTER_BASE  0xfffff0000000ULL
   6
   7 /* register offsets relative to CSR_REGISTER_BASE */
   8 #define CSR_STATE_CLEAR           0x0
   9 #define CSR_STATE_SET             0x4
  10 #define CSR_NODE_IDS              0x8
  11 #define CSR_RESET_START           0xc
  12 #define CSR_SPLIT_TIMEOUT_HI      0x18
  13 #define CSR_SPLIT_TIMEOUT_LO      0x1c
  14 #define CSR_CYCLE_TIME            0x200
  15 #define CSR_BUS_TIME              0x204
  16 #define CSR_BUSY_TIMEOUT          0x210
  17 #define CSR_BUS_MANAGER_ID        0x21c
  18 #define CSR_BANDWIDTH_AVAILABLE   0x220
  19 #define CSR_CHANNELS_AVAILABLE_HI 0x224
  20 #define CSR_CHANNELS_AVAILABLE_LO 0x228
  21 #define CSR_CONFIG_ROM            0x400
  22 #define CSR_CONFIG_ROM_END        0x800
  23 #define CSR_FCP_COMMAND           0xB00
  24 #define CSR_FCP_RESPONSE          0xD00
  25 #define CSR_FCP_END               0xF00
  26 #define CSR_TOPOLOGY_MAP          0x1000
  27 #define CSR_TOPOLOGY_MAP_END      0x1400
  28 #define CSR_SPEED_MAP             0x2000
  29 #define CSR_SPEED_MAP_END         0x3000
  30
  31
  32 struct csr_control {
  33         spinlock_t lock;
  34
  35         quadlet_t state;
  36         quadlet_t node_ids;
  37         quadlet_t split_timeout_hi, split_timeout_lo;
  38         quadlet_t cycle_time;
  39         quadlet_t bus_time;
  40         quadlet_t bus_manager_id;
  41         quadlet_t bandwidth_available;
  42         quadlet_t channels_available_hi, channels_available_lo;
  43
  44         const quadlet_t *rom;
  45         size_t rom_size;
  46
  47         quadlet_t topology_map[256];
  48         quadlet_t speed_map[1024];
  49 };
  50
  51
  52 void init_csr(void);
  53
  54 #endif /* _IEEE1394_CSR_H */