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This is pre8 ...
[linux-2.6/linux-mips.git] / drivers / ide / ide-pci.c
blob8c935439491718cb3022a90d76bdfbcbb40d3830
1 /*
2 * linux/drivers/ide/ide-pci.c Version 1.05 June 9, 2000
3 *
4 * Copyright (c) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 *
6 * Copyright (c) 1995-1998 Mark Lord
7 * May be copied or modified under the terms of the GNU General Public License
8 */
9
10 /*
11 * This module provides support for automatic detection and
12 * configuration of all PCI IDE interfaces present in a system.
13 */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/mm.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/ide.h>
24
25 #include <asm/io.h>
26 #include <asm/irq.h>
27
28 #define DEVID_PIIXa ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0})
29 #define DEVID_PIIXb ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1})
30 #define DEVID_PIIX3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1})
31 #define DEVID_PIIX4 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB})
32 #define DEVID_PIIX4E ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1})
33 #define DEVID_PIIX4E2 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1})
34 #define DEVID_PIIX4U ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1})
35 #define DEVID_PIIX4U2 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1})
36 #define DEVID_PIIX4NX ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX})
37 #define DEVID_PIIX4U3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82820FW_5})
38 #define DEVID_VIA_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561})
39 #define DEVID_VP_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1})
40 #define DEVID_PDC20246 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246})
41 #define DEVID_PDC20262 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262})
42 #define DEVID_PDC20267 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267})
43 #define DEVID_RZ1000 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000})
44 #define DEVID_RZ1001 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001})
45 #define DEVID_SAMURAI ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE})
46 #define DEVID_CMD640 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640})
47 #define DEVID_CMD643 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643})
48 #define DEVID_CMD646 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646})
49 #define DEVID_CMD648 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648})
50 #define DEVID_CMD649 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649})
51 #define DEVID_SIS5513 ((ide_pci_devid_t){PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513})
52 #define DEVID_OPTI621 ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621})
53 #define DEVID_OPTI621V ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558})
54 #define DEVID_OPTI621X ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825})
55 #define DEVID_TRM290 ((ide_pci_devid_t){PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290})
56 #define DEVID_NS87410 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410})
57 #define DEVID_NS87415 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415})
58 #define DEVID_HT6565 ((ide_pci_devid_t){PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565})
59 #define DEVID_AEC6210 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF})
60 #define DEVID_AEC6260 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860})
61 #define DEVID_AEC6260R ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R})
62 #define DEVID_W82C105 ((ide_pci_devid_t){PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105})
63 #define DEVID_UM8673F ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F})
64 #define DEVID_UM8886A ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A})
65 #define DEVID_UM8886BF ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF})
66 #define DEVID_HPT34X ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343})
67 #define DEVID_HPT366 ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366})
68 #define DEVID_ALI15X3 ((ide_pci_devid_t){PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229})
69 #define DEVID_CY82C693 ((ide_pci_devid_t){PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693})
70 #define DEVID_HINT ((ide_pci_devid_t){0x3388, 0x8013})
71 #define DEVID_CS5530 ((ide_pci_devid_t){PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE})
72 #define DEVID_AMD7403 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7403})
73 #define DEVID_AMD7409 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409})
74
75 #define IDE_IGNORE ((void *)-1)
76
77 #ifdef CONFIG_BLK_DEV_AEC62XX
78 extern unsigned int pci_init_aec62xx(struct pci_dev *, const char *);
79 extern unsigned int ata66_aec62xx(ide_hwif_t *);
80 extern void ide_init_aec62xx(ide_hwif_t *);
81 extern void ide_dmacapable_aec62xx(ide_hwif_t *, unsigned long);
82 #define PCI_AEC62XX &pci_init_aec62xx
83 #define ATA66_AEC62XX &ata66_aec62xx
84 #define INIT_AEC62XX &ide_init_aec62xx
85 #define DMA_AEC62XX &ide_dmacapable_aec62xx
86 #else
87 #define PCI_AEC62XX NULL
88 #define ATA66_AEC62XX NULL
89 #define INIT_AEC62XX NULL
90 #define DMA_AEC62XX NULL
91 #endif
92
93 #ifdef CONFIG_BLK_DEV_ALI15X3
94 extern unsigned int pci_init_ali15x3(struct pci_dev *, const char *);
95 extern unsigned int ata66_ali15x3(ide_hwif_t *);
96 extern void ide_init_ali15x3(ide_hwif_t *);
97 extern void ide_dmacapable_ali15x3(ide_hwif_t *, unsigned long);
98 #define PCI_ALI15X3 &pci_init_ali15x3
99 #define ATA66_ALI15X3 &ata66_ali15x3
100 #define INIT_ALI15X3 &ide_init_ali15x3
101 #define DMA_ALI15X3 &ide_dmacapable_ali15x3
102 #else
103 #define PCI_ALI15X3 NULL
104 #define ATA66_ALI15X3 NULL
105 #define INIT_ALI15X3 NULL
106 #define DMA_ALI15X3 NULL
107 #endif
108
109 #ifdef CONFIG_BLK_DEV_AMD7409
110 extern unsigned int pci_init_amd7409(struct pci_dev *, const char *);
111 extern unsigned int ata66_amd7409(ide_hwif_t *);
112 extern void ide_init_amd7409(ide_hwif_t *);
113 extern void ide_dmacapable_amd7409(ide_hwif_t *, unsigned long);
114 #define PCI_AMD7409 &pci_init_amd7409
115 #define ATA66_AMD7409 &ata66_amd7409
116 #define INIT_AMD7409 &ide_init_amd7409
117 #define DMA_AMD7409 &ide_dmacapable_amd7409
118 #else
119 #define PCI_AMD7409 NULL
120 #define ATA66_AMD7409 NULL
121 #define INIT_AMD7409 NULL
122 #define DMA_AMD7409 NULL
123 #endif
124
125 #ifdef CONFIG_BLK_DEV_CMD64X
126 extern unsigned int pci_init_cmd64x(struct pci_dev *, const char *);
127 extern unsigned int ata66_cmd64x(ide_hwif_t *);
128 extern void ide_init_cmd64x(ide_hwif_t *);
129 extern void ide_dmacapable_cmd64x(ide_hwif_t *, unsigned long);
130 #define PCI_CMD64X &pci_init_cmd64x
131 #define ATA66_CMD64X &ata66_cmd64x
132 #define INIT_CMD64X &ide_init_cmd64x
133 #else
134 #define PCI_CMD64X NULL
135 #define ATA66_CMD64X NULL
136 #ifdef __sparc_v9__
137 #define INIT_CMD64X IDE_IGNORE
138 #else
139 #define INIT_CMD64X NULL
140 #endif
141 #endif
142
143 #ifdef CONFIG_BLK_DEV_CY82C693
144 extern unsigned int pci_init_cy82c693(struct pci_dev *, const char *);
145 extern void ide_init_cy82c693(ide_hwif_t *);
146 #define PCI_CY82C693 &pci_init_cy82c693
147 #define INIT_CY82C693 &ide_init_cy82c693
148 #else
149 #define PCI_CY82C693 NULL
150 #define INIT_CY82C693 NULL
151 #endif
152
153 #ifdef CONFIG_BLK_DEV_CS5530
154 extern unsigned int pci_init_cs5530(struct pci_dev *, const char *);
155 extern void ide_init_cs5530(ide_hwif_t *);
156 #define PCI_CS5530 &pci_init_cs5530
157 #define INIT_CS5530 &ide_init_cs5530
158 #else
159 #define PCI_CS5530 NULL
160 #define INIT_CS5530 NULL
161 #endif
162
163 #ifdef CONFIG_BLK_DEV_HPT34X
164 extern unsigned int pci_init_hpt34x(struct pci_dev *, const char *);
165 extern void ide_init_hpt34x(ide_hwif_t *);
166 #define PCI_HPT34X &pci_init_hpt34x
167 #define INIT_HPT34X &ide_init_hpt34x
168 #else
169 #define PCI_HPT34X NULL
170 #define INIT_HPT34X IDE_IGNORE
171 #endif
172
173 #ifdef CONFIG_BLK_DEV_HPT366
174 extern byte hpt363_shared_irq;
175 extern byte hpt363_shared_pin;
176 extern unsigned int pci_init_hpt366(struct pci_dev *, const char *);
177 extern unsigned int ata66_hpt366(ide_hwif_t *);
178 extern void ide_init_hpt366(ide_hwif_t *);
179 extern void ide_dmacapable_hpt366(ide_hwif_t *, unsigned long);
180 #define PCI_HPT366 &pci_init_hpt366
181 #define ATA66_HPT366 &ata66_hpt366
182 #define INIT_HPT366 &ide_init_hpt366
183 #define DMA_HPT366 &ide_dmacapable_hpt366
184 #else
185 static byte hpt363_shared_irq = 0;
186 static byte hpt363_shared_pin = 0;
187 #define PCI_HPT366 NULL
188 #define ATA66_HPT366 NULL
189 #define INIT_HPT366 NULL
190 #define DMA_HPT366 NULL
191 #endif
192
193 #ifdef CONFIG_BLK_DEV_NS87415
194 extern void ide_init_ns87415(ide_hwif_t *);
195 #define INIT_NS87415 &ide_init_ns87415
196 #else
197 #define INIT_NS87415 IDE_IGNORE
198 #endif
199
200 #ifdef CONFIG_BLK_DEV_OPTI621
201 extern void ide_init_opti621(ide_hwif_t *);
202 #define INIT_OPTI621 &ide_init_opti621
203 #else
204 #define INIT_OPTI621 NULL
205 #endif
206
207 #ifdef CONFIG_BLK_DEV_PDC202XX
208 extern unsigned int pci_init_pdc202xx(struct pci_dev *, const char *);
209 extern unsigned int ata66_pdc202xx(ide_hwif_t *);
210 extern void ide_init_pdc202xx(ide_hwif_t *);
211 #define PCI_PDC202XX &pci_init_pdc202xx
212 #define ATA66_PDC202XX &ata66_pdc202xx
213 #define INIT_PDC202XX &ide_init_pdc202xx
214 #else
215 #define PCI_PDC202XX NULL
216 #define ATA66_PDC202XX NULL
217 #define INIT_PDC202XX NULL
218 #endif
219
220 #ifdef CONFIG_BLK_DEV_PIIX
221 extern unsigned int pci_init_piix(struct pci_dev *, const char *);
222 extern unsigned int ata66_piix(ide_hwif_t *);
223 extern void ide_init_piix(ide_hwif_t *);
224 #define PCI_PIIX &pci_init_piix
225 #define ATA66_PIIX &ata66_piix
226 #define INIT_PIIX &ide_init_piix
227 #else
228 #define PCI_PIIX NULL
229 #define ATA66_PIIX NULL
230 #define INIT_PIIX NULL
231 #endif
232
233 #ifdef CONFIG_BLK_DEV_RZ1000
234 extern void ide_init_rz1000(ide_hwif_t *);
235 #define INIT_RZ1000 &ide_init_rz1000
236 #else
237 #define INIT_RZ1000 IDE_IGNORE
238 #endif
239
240 #define INIT_SAMURAI NULL
241
242 #ifdef CONFIG_BLK_DEV_SIS5513
243 extern unsigned int pci_init_sis5513(struct pci_dev *, const char *);
244 extern unsigned int ata66_sis5513(ide_hwif_t *);
245 extern void ide_init_sis5513(ide_hwif_t *);
246 #define PCI_SIS5513 &pci_init_sis5513
247 #define ATA66_SIS5513 &ata66_sis5513
248 #define INIT_SIS5513 &ide_init_sis5513
249 #else
250 #define PCI_SIS5513 NULL
251 #define ATA66_SIS5513 NULL
252 #define INIT_SIS5513 NULL
253 #endif
254
255 #ifdef CONFIG_BLK_DEV_SL82C105
256 extern void ide_init_sl82c105(ide_hwif_t *);
257 extern void ide_dmacapable_sl82c105(ide_hwif_t *, unsigned long);
258 #define INIT_W82C105 &ide_init_sl82c105
259 #define DMA_W82C105 &ide_dmacapable_sl82c105
260 #else
261 #define INIT_W82C105 IDE_IGNORE
262 #define DMA_W82C105 NULL
263 #endif
264
265 #ifdef CONFIG_BLK_DEV_TRM290
266 extern void ide_init_trm290(ide_hwif_t *);
267 #define INIT_TRM290 &ide_init_trm290
268 #else
269 #define INIT_TRM290 IDE_IGNORE
270 #endif
271
272 #ifdef CONFIG_BLK_DEV_VIA82CXXX
273 extern unsigned int pci_init_via82cxxx(struct pci_dev *, const char *);
274 extern unsigned int ata66_via82cxxx(ide_hwif_t *);
275 extern void ide_init_via82cxxx(ide_hwif_t *);
276 extern void ide_dmacapable_via82cxxx(ide_hwif_t *, unsigned long);
277 #define PCI_VIA82CXXX &pci_init_via82cxxx
278 #define ATA66_VIA82CXXX &ata66_via82cxxx
279 #define INIT_VIA82CXXX &ide_init_via82cxxx
280 #define DMA_VIA82CXXX &ide_dmacapable_via82cxxx
281 #else
282 #define PCI_VIA82CXXX NULL
283 #define ATA66_VIA82CXXX NULL
284 #define INIT_VIA82CXXX NULL
285 #define DMA_VIA82CXXX NULL
286 #endif
287
288 typedef struct ide_pci_enablebit_s {
289 byte reg; /* byte pci reg holding the enable-bit */
290 byte mask; /* mask to isolate the enable-bit */
291 byte val; /* value of masked reg when "enabled" */
292 } ide_pci_enablebit_t;
293
294 typedef struct ide_pci_device_s {
295 ide_pci_devid_t devid;
296 char *name;
297 unsigned int (*init_chipset)(struct pci_dev *dev, const char *name);
298 unsigned int (*ata66_check)(ide_hwif_t *hwif);
299 void (*init_hwif)(ide_hwif_t *hwif);
300 void (*dma_init)(ide_hwif_t *hwif, unsigned long dmabase);
301 ide_pci_enablebit_t enablebits[2];
302 byte bootable;
303 unsigned int extra;
304 } ide_pci_device_t;
305
306 static ide_pci_device_t ide_pci_chipsets[] __initdata = {
307 {DEVID_PIIXa, "PIIX", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
308 {DEVID_PIIXb, "PIIX", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
309 {DEVID_PIIX3, "PIIX3", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
310 {DEVID_PIIX4, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
311 {DEVID_PIIX4E, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
312 {DEVID_PIIX4E2, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
313 {DEVID_PIIX4U, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
314 {DEVID_PIIX4U2, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
315 {DEVID_PIIX4NX, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
316 {DEVID_PIIX4U3, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
317 {DEVID_VIA_IDE, "VIA_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
318 {DEVID_VP_IDE, "VP_IDE", PCI_VIA82CXXX, ATA66_VIA82CXXX,INIT_VIA82CXXX, DMA_VIA82CXXX, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 },
319 {DEVID_PDC20246,"PDC20246", PCI_PDC202XX, NULL, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 16 },
320 {DEVID_PDC20262,"PDC20262", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
321 {DEVID_PDC20267,"PDC20267", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
322 {DEVID_RZ1000, "RZ1000", NULL, NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
323 {DEVID_RZ1001, "RZ1001", NULL, NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
324 {DEVID_SAMURAI, "SAMURAI", NULL, NULL, INIT_SAMURAI, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
325 {DEVID_CMD640, "CMD640", NULL, NULL, IDE_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
326 {DEVID_NS87410, "NS87410", NULL, NULL, NULL, NULL, {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, ON_BOARD, 0 },
327 {DEVID_SIS5513, "SIS5513", PCI_SIS5513, ATA66_SIS5513, INIT_SIS5513, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, ON_BOARD, 0 },
328 {DEVID_CMD643, "CMD643", PCI_CMD64X, NULL, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
329 {DEVID_CMD646, "CMD646", PCI_CMD64X, NULL, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, ON_BOARD, 0 },
330 {DEVID_CMD648, "CMD648", PCI_CMD64X, ATA66_CMD64X, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
331 {DEVID_CMD649, "CMD649", PCI_CMD64X, ATA66_CMD64X, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
332 {DEVID_HT6565, "HT6565", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
333 {DEVID_OPTI621, "OPTI621", NULL, NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 },
334 {DEVID_OPTI621X,"OPTI621X", NULL, NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 },
335 {DEVID_TRM290, "TRM290", NULL, NULL, INIT_TRM290, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
336 {DEVID_NS87415, "NS87415", NULL, NULL, INIT_NS87415, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
337 {DEVID_AEC6210, "AEC6210", PCI_AEC62XX, NULL, INIT_AEC62XX, DMA_AEC62XX, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0 },
338 {DEVID_AEC6260, "AEC6260", PCI_AEC62XX, ATA66_AEC62XX, INIT_AEC62XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 0 },
339 {DEVID_AEC6260R,"AEC6260R", PCI_AEC62XX, ATA66_AEC62XX, INIT_AEC62XX, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0 },
340 {DEVID_W82C105, "W82C105", NULL, NULL, INIT_W82C105, DMA_W82C105, {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, ON_BOARD, 0 },
341 {DEVID_UM8673F, "UM8673F", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
342 {DEVID_UM8886A, "UM8886A", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
343 {DEVID_UM8886BF,"UM8886BF", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
344 {DEVID_HPT34X, "HPT34X", PCI_HPT34X, NULL, INIT_HPT34X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 16 },
345 {DEVID_HPT366, "HPT366", PCI_HPT366, ATA66_HPT366, INIT_HPT366, DMA_HPT366, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 240 },
346 {DEVID_ALI15X3, "ALI15X3", PCI_ALI15X3, ATA66_ALI15X3, INIT_ALI15X3, DMA_ALI15X3, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
347 {DEVID_CY82C693,"CY82C693", PCI_CY82C693, NULL, INIT_CY82C693, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
348 {DEVID_HINT, "HINT_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
349 {DEVID_CS5530, "CS5530", PCI_CS5530, NULL, INIT_CS5530, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
350 {DEVID_AMD7403, "AMD7403", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
351 {DEVID_AMD7409, "AMD7409", PCI_AMD7409, ATA66_AMD7409, INIT_AMD7409, DMA_AMD7409, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 },
352 {IDE_PCI_DEVID_NULL, "PCI_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }};
353
354 /*
355 * This allows offboard ide-pci cards the enable a BIOS, verify interrupt
356 * settings of split-mirror pci-config space, place chipset into init-mode,
357 * and/or preserve an interrupt if the card is not native ide support.
358 */
359 static unsigned int __init ide_special_settings (struct pci_dev *dev, const char *name)
360 {
361 switch(dev->device) {
362 case PCI_DEVICE_ID_TTI_HPT366:
363 case PCI_DEVICE_ID_PROMISE_20246:
364 case PCI_DEVICE_ID_PROMISE_20262:
365 case PCI_DEVICE_ID_PROMISE_20267:
366 case PCI_DEVICE_ID_ARTOP_ATP850UF:
367 case PCI_DEVICE_ID_ARTOP_ATP860:
368 case PCI_DEVICE_ID_ARTOP_ATP860R:
369 return dev->irq;
370 default:
371 break;
372 }
373 return 0;
374 }
375
376 /*
377 * Match a PCI IDE port against an entry in ide_hwifs[],
378 * based on io_base port if possible.
379 */
380 static ide_hwif_t __init *ide_match_hwif (unsigned long io_base, byte bootable, const char *name)
381 {
382 int h;
383 ide_hwif_t *hwif;
384
385 /*
386 * Look for a hwif with matching io_base specified using
387 * parameters to ide_setup().
388 */
389 for (h = 0; h < MAX_HWIFS; ++h) {
390 hwif = &ide_hwifs[h];
391 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
392 if (hwif->chipset == ide_generic)
393 return hwif; /* a perfect match */
394 }
395 }
396 /*
397 * Look for a hwif with matching io_base default value.
398 * If chipset is "ide_unknown", then claim that hwif slot.
399 * Otherwise, some other chipset has already claimed it.. :(
400 */
401 for (h = 0; h < MAX_HWIFS; ++h) {
402 hwif = &ide_hwifs[h];
403 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
404 if (hwif->chipset == ide_unknown)
405 return hwif; /* match */
406 printk("%s: port 0x%04lx already claimed by %s\n", name, io_base, hwif->name);
407 return NULL; /* already claimed */
408 }
409 }
410 /*
411 * Okay, there is no hwif matching our io_base,
412 * so we'll just claim an unassigned slot.
413 * Give preference to claiming other slots before claiming ide0/ide1,
414 * just in case there's another interface yet-to-be-scanned
415 * which uses ports 1f0/170 (the ide0/ide1 defaults).
416 *
417 * Unless there is a bootable card that does not use the standard
418 * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag.
419 */
420 if (bootable) {
421 for (h = 0; h < MAX_HWIFS; ++h) {
422 hwif = &ide_hwifs[h];
423 if (hwif->chipset == ide_unknown)
424 return hwif; /* pick an unused entry */
425 }
426 } else {
427 for (h = 2; h < MAX_HWIFS; ++h) {
428 hwif = ide_hwifs + h;
429 if (hwif->chipset == ide_unknown)
430 return hwif; /* pick an unused entry */
431 }
432 }
433 for (h = 0; h < 2; ++h) {
434 hwif = ide_hwifs + h;
435 if (hwif->chipset == ide_unknown)
436 return hwif; /* pick an unused entry */
437 }
438 printk("%s: too many IDE interfaces, no room in table\n", name);
439 return NULL;
440 }
441
442 static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
443 {
444 byte reg, progif = 0;
445
446 /*
447 * Place both IDE interfaces into PCI "native" mode:
448 */
449 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
450 if ((progif & 0xa) != 0xa) {
451 printk("%s: device not capable of full native PCI mode\n", name);
452 return 1;
453 }
454 printk("%s: placing both ports into native PCI mode\n", name);
455 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
456 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
457 printk("%s: rewrite of PROGIF failed, wanted 0x%04x, got 0x%04x\n", name, progif|5, progif);
458 return 1;
459 }
460 }
461 /*
462 * Setup base registers for IDE command/control spaces for each interface:
463 */
464 for (reg = 0; reg < 4; reg++) {
465 struct resource *res = dev->resource + reg;
466 if (!(res->flags & PCI_BASE_ADDRESS_SPACE_IO))
467 continue;
468 if (!res->start) {
469 printk("%s: Missing I/O address #%d\n", name, reg);
470 return 1;
471 }
472 }
473 return 0;
474 }
475
476 /*
477 * ide_setup_pci_device() looks at the primary/secondary interfaces
478 * on a PCI IDE device and, if they are enabled, prepares the IDE driver
479 * for use with them. This generic code works for most PCI chipsets.
480 *
481 * One thing that is not standardized is the location of the
482 * primary/secondary interface "enable/disable" bits. For chipsets that
483 * we "know" about, this information is in the ide_pci_device_t struct;
484 * for all other chipsets, we just assume both interfaces are enabled.
485 */
486 static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *d)
487 {
488 unsigned int port, at_least_one_hwif_enabled = 0, autodma = 0, pciirq = 0;
489 unsigned short pcicmd = 0, tried_config = 0;
490 byte tmp = 0;
491 ide_hwif_t *hwif, *mate = NULL;
492 unsigned int class_rev;
493
494 #ifdef CONFIG_IDEDMA_AUTO
495 autodma = 1;
496 #endif
497 check_if_enabled:
498 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
499 printk("%s: error accessing PCI regs\n", d->name);
500 return;
501 }
502 if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
503 /*
504 * PnP BIOS was *supposed* to have set this device up for us,
505 * but we can do it ourselves, so long as the BIOS has assigned an IRQ
506 * (or possibly the device is using a "legacy header" for IRQs).
507 * Maybe the user deliberately *disabled* the device,
508 * but we'll eventually ignore it again if no drives respond.
509 */
510 if (tried_config++
511 || ide_setup_pci_baseregs(dev, d->name)
512 || pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {
513 printk("%s: device disabled (BIOS)\n", d->name);
514 return;
515 }
516 autodma = 0; /* default DMA off if we had to configure it here */
517 goto check_if_enabled;
518 }
519 if (tried_config)
520 printk("%s: device enabled (Linux)\n", d->name);
521
522 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
523 class_rev &= 0xff;
524
525 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X)) {
526 /* see comments in hpt34x.c on why..... */
527 char *chipset_names[] = {"HPT343", "HPT345"};
528 strcpy(d->name, chipset_names[(pcicmd & PCI_COMMAND_MEMORY)]);
529 d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
530 }
531
532 printk("%s: chipset revision %d\n", d->name, class_rev);
533
534 /*
535 * Can we trust the reported IRQ?
536 */
537 pciirq = dev->irq;
538 if ((dev->class & ~(0xfa)) != ((PCI_CLASS_STORAGE_IDE << 8) | 5)) {
539 printk("%s: not 100%% native mode: will probe irqs later\n", d->name);
540 /*
541 * This allows offboard ide-pci cards the enable a BIOS,
542 * verify interrupt settings of split-mirror pci-config
543 * space, place chipset into init-mode, and/or preserve
544 * an interrupt if the card is not native ide support.
545 */
546 pciirq = (d->init_chipset) ? d->init_chipset(dev, d->name) : ide_special_settings(dev, d->name);
547 } else if (tried_config) {
548 printk("%s: will probe irqs later\n", d->name);
549 pciirq = 0;
550 } else if (!pciirq) {
551 printk("%s: bad irq (%d): will probe later\n", d->name, pciirq);
552 pciirq = 0;
553 } else {
554 if (d->init_chipset)
555 (void) d->init_chipset(dev, d->name);
556 #ifdef __sparc__
557 printk("%s: 100%% native mode on irq %s\n",
558 d->name, __irq_itoa(pciirq));
559 #else
560 printk("%s: 100%% native mode on irq %d\n", d->name, pciirq);
561 #endif
562 }
563
564 /*
565 * Set up the IDE ports
566 */
567 for (port = 0; port <= 1; ++port) {
568 unsigned long base = 0, ctl = 0;
569 ide_pci_enablebit_t *e = &(d->enablebits[port]);
570 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || (tmp & e->mask) != e->val))
571 continue; /* port not enabled */
572 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) && (port) && (class_rev < 0x03))
573 return;
574 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE || (dev->class & (port ? 4 : 1)) != 0) {
575 ctl = dev->resource[(2*port)+1].start;
576 base = dev->resource[2*port].start;
577 if (!(ctl & PCI_BASE_ADDRESS_IO_MASK) ||
578 !(base & PCI_BASE_ADDRESS_IO_MASK)) {
579 printk("%s: IO baseregs (BIOS) are reported as MEM, report to <andre@linux-ide.org>.\n", d->name);
580 #if 0
581 /* FIXME! This really should check that it really gets the IO/MEM part right! */
582 continue;
583 #endif
584 }
585 }
586 if ((ctl && !base) || (base && !ctl)) {
587 printk("%s: inconsistent baseregs (BIOS) for port %d, skipping\n", d->name, port);
588 continue;
589 }
590 if (!ctl)
591 ctl = port ? 0x374 : 0x3f4; /* use default value */
592 if (!base)
593 base = port ? 0x170 : 0x1f0; /* use default value */
594 if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL)
595 continue; /* no room in ide_hwifs[] */
596 if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
597 ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL);
598 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
599 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
600 }
601 hwif->chipset = ide_pci;
602 hwif->pci_dev = dev;
603 hwif->pci_devid = d->devid;
604 hwif->channel = port;
605 if (!hwif->irq)
606 hwif->irq = pciirq;
607 if (mate) {
608 hwif->mate = mate;
609 mate->mate = hwif;
610 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210)) {
611 hwif->serialized = 1;
612 mate->serialized = 1;
613 }
614 }
615 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) ||
616 IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886BF) ||
617 IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8673F)) {
618 hwif->irq = hwif->channel ? 15 : 14;
619 goto bypass_umc_dma;
620 }
621 if (hwif->udma_four) {
622 printk("%s: ATA-66/100 forced bit set (WARNING)!!\n", d->name);
623 } else {
624 hwif->udma_four = (d->ata66_check) ? d->ata66_check(hwif) : 0;
625 }
626 #ifdef CONFIG_BLK_DEV_IDEDMA
627 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_SIS5513) ||
628 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260) ||
629 IDE_PCI_DEVID_EQ(d->devid, DEVID_PIIX4NX) ||
630 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X))
631 autodma = 0;
632 if (autodma)
633 hwif->autodma = 1;
634 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20246) ||
635 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20262) ||
636 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20267) ||
637 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210) ||
638 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260) ||
639 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260R) ||
640 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X) ||
641 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) ||
642 IDE_PCI_DEVID_EQ(d->devid, DEVID_CS5530) ||
643 IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) ||
644 IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD646) ||
645 IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD648) ||
646 IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD649) ||
647 ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 0x80))) {
648 unsigned long dma_base = ide_get_or_set_dma_base(hwif, (!mate && d->extra) ? d->extra : 0, d->name);
649 if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) {
650 /*
651 * Set up BM-DMA capability (PnP BIOS should have done this)
652 */
653 hwif->autodma = 0; /* default DMA off if we had to configure it here */
654 (void) pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_MASTER);
655 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) {
656 printk("%s: %s error updating PCICMD\n", hwif->name, d->name);
657 dma_base = 0;
658 }
659 }
660 if (dma_base) {
661 if (d->dma_init) {
662 d->dma_init(hwif, dma_base);
663 } else {
664 ide_setup_dma(hwif, dma_base, 8);
665 }
666 } else {
667 printk("%s: %s Bus-Master DMA disabled (BIOS)\n", hwif->name, d->name);
668 }
669 }
670 #endif /* CONFIG_BLK_DEV_IDEDMA */
671 bypass_umc_dma:
672 if (d->init_hwif) /* Call chipset-specific routine for each enabled hwif */
673 d->init_hwif(hwif);
674 mate = hwif;
675 at_least_one_hwif_enabled = 1;
676 }
677 if (!at_least_one_hwif_enabled)
678 printk("%s: neither IDE port enabled (BIOS)\n", d->name);
679 }
680
681 static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_device_t *d)
682 {
683 struct pci_dev *dev2 = NULL, *findev;
684 ide_pci_device_t *d2;
685 unsigned char pin1 = 0, pin2 = 0;
686 unsigned int class_rev;
687 char *chipset_names[] = {"HPT366", "HPT366", "HPT368", "HPT370", "HPT370A"};
688
689 if (PCI_FUNC(dev->devfn) & 1)
690 return;
691
692 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
693 class_rev &= 0xff;
694
695 strcpy(d->name, chipset_names[class_rev]);
696
697 switch(class_rev) {
698 case 4:
699 case 3: printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
700 ide_setup_pci_device(dev, d);
701 return;
702 default: break;
703 }
704
705 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
706 pci_for_each_dev(findev) {
707 if ((findev->vendor == dev->vendor) &&
708 (findev->device == dev->device) &&
709 ((findev->devfn - dev->devfn) == 1) &&
710 (PCI_FUNC(findev->devfn) & 1)) {
711 dev2 = findev;
712 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
713 hpt363_shared_pin = (pin1 != pin2) ? 1 : 0;
714 hpt363_shared_irq = (dev->irq == dev2->irq) ? 1 : 0;
715 if (hpt363_shared_pin && hpt363_shared_irq) {
716 d->bootable = ON_BOARD;
717 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n", d->name, pin1, pin2);
718 }
719 break;
720 }
721 }
722 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
723 ide_setup_pci_device(dev, d);
724 if (!dev2)
725 return;
726 d2 = d;
727 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d2->name, dev2->bus->number, dev2->devfn);
728 ide_setup_pci_device(dev2, d2);
729 }
730
731 /*
732 * ide_scan_pcibus() gets invoked at boot time from ide.c.
733 * It finds all PCI IDE controllers and calls ide_setup_pci_device for them.
734 */
735 void __init ide_scan_pcidev (struct pci_dev *dev)
736 {
737 ide_pci_devid_t devid;
738 ide_pci_device_t *d;
739
740 devid.vid = dev->vendor;
741 devid.did = dev->device;
742 for (d = ide_pci_chipsets; d->devid.vid && !IDE_PCI_DEVID_EQ(d->devid, devid); ++d);
743 if (d->init_hwif == IDE_IGNORE)
744 printk("%s: ignored by ide_scan_pci_device() (uses own driver)\n", d->name);
745 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_OPTI621V) && !(PCI_FUNC(dev->devfn) & 1))
746 return;
747 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)))
748 return; /* CY82C693 is more than only a IDE controller */
749 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) && !(PCI_FUNC(dev->devfn) & 1))
750 return; /* UM8886A/BF pair */
751 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366))
752 hpt366_device_order_fixup(dev, d);
753 else if (!IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL) || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
754 if (IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL))
755 printk("%s: unknown IDE controller on PCI bus %02x device %02x, VID=%04x, DID=%04x\n",
756 d->name, dev->bus->number, dev->devfn, devid.vid, devid.did);
757 else
758 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
759 ide_setup_pci_device(dev, d);
760 }
761 }
762
763 void __init ide_scan_pcibus (int scan_direction)
764 {
765 struct pci_dev *dev;
766
767 if (!scan_direction) {
768 pci_for_each_dev(dev) {
769 ide_scan_pcidev(dev);
770 }
771 } else {
772 pci_for_each_dev_reverse(dev) {
773 ide_scan_pcidev(dev);
774 }
775 }
776 }
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