drivers/block/cy82c693.c

   1 /*
   2  * linux/drivers/block/cy82c693.c       Version 0.34    Dec. 13, 1999
   3  *
   4  *  Copyright (C) 1998-99 Andreas S. Krebs (akrebs@altavista.net), Maintainer
   5  *  Copyright (C) 1998-99 Andre Hedrick, Integrater
   6  *
   7  * CYPRESS CY82C693 chipset IDE controller
   8  *
   9  * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
  10  * Writting the driver was quite simple, since most of the job is
  11  * done by the generic pci-ide support.
  12  * The hard part was finding the CY82C693's datasheet on Cypress's
  13  * web page :-(. But Altavista solved this problem :-).
  14  *
  15  *
  16  * Notes:
  17  * - I recently got a 16.8G IBM DTTA, so I was able to test it with
  18  *   a large and fast disk - the results look great, so I'd say the
  19  *   driver is working fine :-)
  20  *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
  21  * - this is my first linux driver, so there's probably a lot  of room
  22  *   for optimizations and bug fixing, so feel free to do it.
  23  * - use idebus=xx parameter to set PCI bus speed - needed to calc
  24  *   timings for PIO modes (default will be 40)
  25  * - if using PIO mode it's a good idea to set the PIO mode and
  26  *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
  27  * - I had some problems with my IBM DHEA with PIO modes < 2
  28  *   (lost interrupts) ?????
  29  * - first tests with DMA look okay, they seem to work, but there is a
  30  *   problem with sound - the BusMaster IDE TimeOut should fixed this
  31  *
  32  *
  33  * History:
  34  * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
  35  * ASK@1999-01-23: v0.33 made a few minor code clean ups
  36  *                       removed DMA clock speed setting by default
  37  *                       added boot message
  38  * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
  39  *                       added support to set DMA Controller Clock Speed
  40  * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes on some drive
  41  * ASK@1998-10-29: v0.3 added support to set DMA modes
  42  * ASK@1998-10-28: v0.2 added support to set PIO modes
  43  * ASK@1998-10-27: v0.1 first version - chipset detection
  44  *
  45  */
  46
  47 #include <linux/types.h>
  48 #include <linux/pci.h>
  49 #include <linux/delay.h>
  50 #include <linux/ide.h>
  51
  52 #include <asm/io.h>
  53
  54 #include "ide_modes.h"
  55
  56 /* the current version */
  57 #define CY82_VERSION    "CY82C693U driver v0.34 99-09-03 Andreas S. Krebs (akrebs@altavista.net)"
  58
  59 /*
  60  *      The following are used to debug the driver.
  61  */
  62 #define CY82C693_DEBUG_LOGS     0
  63 #define CY82C693_DEBUG_INFO     0
  64
  65 /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
  66 #undef CY82C693_SETDMA_CLOCK
  67
  68 /*
  69  * note: the value for busmaster timeout is tricky and i got it by trial and error !
  70  *       using a to low value will cause DMA timeouts and drop IDE performance
  71  *       using a to high value will cause audio playback to scatter
  72  *       if you know a better value or how to calc it, please let me know
  73  */
  74 #define BUSMASTER_TIMEOUT       0x50    /* twice the value written in cy82c693ub datasheet */
  75 /*
  76  * the value above was tested on my machine and it seems to work okay
  77  */
  78
  79 /* here are the offset definitions for the registers */
  80 #define CY82_IDE_CMDREG         0x04
  81 #define CY82_IDE_ADDRSETUP      0x48
  82 #define CY82_IDE_MASTER_IOR     0x4C
  83 #define CY82_IDE_MASTER_IOW     0x4D
  84 #define CY82_IDE_SLAVE_IOR      0x4E
  85 #define CY82_IDE_SLAVE_IOW      0x4F
  86 #define CY82_IDE_MASTER_8BIT    0x50
  87 #define CY82_IDE_SLAVE_8BIT     0x51
  88
  89 #define CY82_INDEX_PORT         0x22
  90 #define CY82_DATA_PORT          0x23
  91
  92 #define CY82_INDEX_CTRLREG1     0x01
  93 #define CY82_INDEX_CHANNEL0     0x30
  94 #define CY82_INDEX_CHANNEL1     0x31
  95 #define CY82_INDEX_TIMEOUT      0x32
  96
  97 /* the max PIO mode - from datasheet */
  98 #define CY82C693_MAX_PIO        4
  99
 100 /* the min and max PCI bus speed in MHz - from datasheet */
 101 #define CY82C963_MIN_BUS_SPEED  25
 102 #define CY82C963_MAX_BUS_SPEED  33
 103
 104 /* the struct for the PIO mode timings */
 105 typedef struct pio_clocks_s {
 106         byte    address_time;           /* Address setup (clocks) */
 107         byte    time_16r;               /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
 108         byte    time_16w;               /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
 109         byte    time_8;                 /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
 110 } pio_clocks_t;
 111
 112 /*
 113  * calc clocks using bus_speed
 114  * returns (rounded up) time in bus clocks for time in ns
 115  */
 116 static int calc_clk (int time, int bus_speed)
 117 {
 118         int clocks;
 119
 120         clocks = (time*bus_speed+999)/1000 -1;
 121
 122         if (clocks < 0)
 123                 clocks = 0;
 124
 125         if (clocks > 0x0F)
 126                 clocks = 0x0F;
 127
 128         return clocks;
 129 }
 130
 131 /*
 132  * compute the values for the clock registers for PIO
 133  * mode and pci_clk [MHz] speed
 134  *
 135  * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 136  *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 137  *
 138  */
 139 static void compute_clocks (byte pio, pio_clocks_t *p_pclk)
 140 {
 141         int clk1, clk2;
 142         int bus_speed;
 143
 144         bus_speed = ide_system_bus_speed();     /* get speed of PCI bus */
 145         /* we don't check against CY82C693's min and max speed,
 146          * so you can play with the idebus=xx parameter
 147          */
 148
 149         if (pio > CY82C693_MAX_PIO)
 150                 pio = CY82C693_MAX_PIO;
 151
 152         /* let's calc the address setup time clocks */
 153         p_pclk->address_time = (byte)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
 154
 155         /* let's calc the active and recovery time clocks */
 156         clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
 157
 158         /* calc recovery timing */
 159         clk2 =  ide_pio_timings[pio].cycle_time -
 160                 ide_pio_timings[pio].active_time -
 161                 ide_pio_timings[pio].setup_time;
 162
 163         clk2 = calc_clk(clk2, bus_speed);
 164
 165         clk1 = (clk1<<4)|clk2;  /* combine active and recovery clocks */
 166
 167         /* note: we use the same values for 16bit IOR and IOW
 168          *      those are all the same, since I don't have other
 169          *      timings than those from ide_modes.h
 170          */
 171
 172         p_pclk->time_16r = (byte)clk1;
 173         p_pclk->time_16w = (byte)clk1;
 174
 175         /* what are good values for 8bit ?? */
 176         p_pclk->time_8 = (byte)clk1;
 177 }
 178
 179 /*
 180  * set DMA mode a specific channel for CY82C693
 181  */
 182 static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
 183 {
 184         byte index;
 185         byte data;
 186
 187         if (mode>2)     /* make sure we set a valid mode */
 188                 mode = 2;
 189
 190         if (mode > drive->id->tDMA)  /* to be absolutly sure we have a valid mode */
 191                 mode = drive->id->tDMA;
 192
 193         index = (HWIF(drive)->channel==0) ? CY82_INDEX_CHANNEL0 : CY82_INDEX_CHANNEL1;
 194
 195 #if CY82C693_DEBUG_LOGS
 196         /* for debug let's show the previous values */
 197
 198         OUT_BYTE(index, CY82_INDEX_PORT);
 199         data = IN_BYTE(CY82_DATA_PORT);
 200
 201         printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n", drive->name, HWIF(drive)->channel, drive->select.b.unit, (data&0x3), ((data>>2)&1));
 202 #endif /* CY82C693_DEBUG_LOGS */
 203
 204         data = (byte)mode|(byte)(single<<2);
 205
 206         OUT_BYTE(index, CY82_INDEX_PORT);
 207         OUT_BYTE(data, CY82_DATA_PORT);
 208
 209 #if CY82C693_DEBUG_INFO
 210         printk (KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n", drive->name, HWIF(drive)->channel, drive->select.b.unit, mode, single);
 211 #endif /* CY82C693_DEBUG_INFO */
 212
 213         /*
 214          * note: below we set the value for Bus Master IDE TimeOut Register
 215          * I'm not absolutly sure what this does, but it solved my problem
 216          * with IDE DMA and sound, so I now can play sound and work with
 217          * my IDE driver at the same time :-)
 218          *
 219          * If you know the correct (best) value for this register please
 220          * let me know - ASK
 221          */
 222
 223         data = BUSMASTER_TIMEOUT;
 224         OUT_BYTE(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
 225         OUT_BYTE(data, CY82_DATA_PORT);
 226
 227 #if CY82C693_DEBUG_INFO
 228         printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n", drive->name, data);
 229 #endif /* CY82C693_DEBUG_INFO */
 230 }
 231
 232 /*
 233  * used to set DMA mode for CY82C693 (single and multi modes)
 234  */
 235 static int cy82c693_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
 236 {
 237         /*
 238          * if the function is dma on, set dma mode for drive everything
 239          * else is done by the defaul func
 240          */
 241         if (func == ide_dma_on) {
 242                 struct hd_driveid *id = drive->id;
 243
 244 #if CY82C693_DEBUG_INFO
 245                 printk (KERN_INFO "dma_on: %s\n", drive->name);
 246 #endif /* CY82C693_DEBUG_INFO */
 247
 248                 if (id != NULL) {
 249                        /* Enable DMA on any drive that has DMA (multi or single) enabled */
 250                        if (id->field_valid & 2) {       /* regular DMA */
 251                                int mmode, smode;
 252
 253                                mmode = id->dma_mword & (id->dma_mword >> 8);
 254                                smode = id->dma_1word & (id->dma_1word >> 8);
 255
 256                                if (mmode != 0)
 257                                      cy82c693_dma_enable(drive, (mmode >> 1), 0); /* enable multi */
 258                                else if (smode != 0)
 259                                      cy82c693_dma_enable(drive, (smode >> 1), 1); /* enable single */
 260                         }
 261                 }
 262         }
 263         return ide_dmaproc(func, drive);
 264 }
 265
 266 /*
 267  * tune ide drive - set PIO mode
 268  */
 269 static void cy82c693_tune_drive (ide_drive_t *drive, byte pio)
 270 {
 271         ide_hwif_t *hwif = HWIF(drive);
 272         struct pci_dev *dev = hwif->pci_dev;
 273         pio_clocks_t pclk;
 274         unsigned int addrCtrl;
 275
 276         /* select primary or secondary channel */
 277         if (hwif->index > 0) {  /* drive is on the secondary channel */
 278                 dev = pci_find_slot(dev->bus->number, dev->devfn+1);
 279                 if (!dev) {
 280                         printk(KERN_ERR "%s: tune_drive: Cannot find secondary interface!\n", drive->name);
 281                         return;
 282                 }
 283         }
 284
 285 #if CY82C693_DEBUG_LOGS
 286         /* for debug let's show the register values */
 287
 288         if (drive->select.b.unit == 0) {
 289                 /*
 290                  * get master drive registers
 291                  * address setup control register
 292                  * is 32 bit !!!
 293                  */
 294                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 295                 addrCtrl &= 0x0F;
 296
 297                 /* now let's get the remaining registers */
 298                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
 299                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
 300                 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
 301         } else {
 302                 /*
 303                  * set slave drive registers
 304                  * address setup control register
 305                  * is 32 bit !!!
 306                  */
 307                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 308
 309                 addrCtrl &= 0xF0;
 310                 addrCtrl >>= 4;
 311
 312                 /* now let's get the remaining registers */
 313                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
 314                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
 315                 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
 316         }
 317
 318         printk (KERN_INFO "%s (ch=%d, dev=%d): PIO timing is (addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", drive->name, hwif->channel, drive->select.b.unit, addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 319 #endif /* CY82C693_DEBUG_LOGS */
 320
 321         /* first let's calc the pio modes */
 322         pio = ide_get_best_pio_mode(drive, pio, CY82C693_MAX_PIO, NULL);
 323
 324 #if CY82C693_DEBUG_INFO
 325         printk (KERN_INFO "%s: Selected PIO mode %d\n", drive->name, pio);
 326 #endif /* CY82C693_DEBUG_INFO */
 327
 328         compute_clocks(pio, &pclk);  /* let's calc the values for this PIO mode */
 329
 330         /* now let's write  the clocks registers */
 331         if (drive->select.b.unit == 0) {
 332                 /*
 333                  * set master drive
 334                  * address setup control register
 335                  * is 32 bit !!!
 336                  */
 337                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 338
 339                 addrCtrl &= (~0xF);
 340                 addrCtrl |= (unsigned int)pclk.address_time;
 341                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 342
 343                 /* now let's set the remaining registers */
 344                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
 345                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
 346                 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
 347
 348                 addrCtrl &= 0xF;
 349         } else {
 350                 /*
 351                  * set slave drive
 352                  * address setup control register
 353                  * is 32 bit !!!
 354                  */
 355                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 356
 357                 addrCtrl &= (~0xF0);
 358                 addrCtrl |= ((unsigned int)pclk.address_time<<4);
 359                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 360
 361                 /* now let's set the remaining registers */
 362                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
 363                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
 364                 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
 365
 366                 addrCtrl >>= 4;
 367                 addrCtrl &= 0xF;
 368         }
 369
 370 #if CY82C693_DEBUG_INFO
 371         printk (KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to (addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", drive->name, hwif->channel, drive->select.b.unit, addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 372 #endif /* CY82C693_DEBUG_INFO */
 373 }
 374
 375 /*
 376  * this function is called during init and is used to setup the cy82c693 chip
 377  */
 378 /*
 379  * FIXME! "pci_init_cy82c693" really should replace
 380  * the "init_cy82c693_chip", it is the correct location to tinker/setup
 381  * the device prior to INIT.
 382  */
 383
 384 unsigned int __init pci_init_cy82c693(struct pci_dev *dev, const char *name)
 385 {
 386 #ifdef CY82C693_SETDMA_CLOCK
 387         byte data;
 388 #endif /* CY82C693_SETDMA_CLOCK */
 389
 390         /* write info about this verion of the driver */
 391         printk (KERN_INFO CY82_VERSION "\n");
 392
 393 #ifdef CY82C693_SETDMA_CLOCK
 394        /* okay let's set the DMA clock speed */
 395
 396         OUT_BYTE(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 397         data = IN_BYTE(CY82_DATA_PORT);
 398
 399 #if CY82C693_DEBUG_INFO
 400         printk (KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n", name, data);
 401 #endif /* CY82C693_DEBUG_INFO */
 402
 403         /*
 404          * for some reason sometimes the DMA controller
 405          * speed is set to ATCLK/2 ???? - we fix this here
 406          *
 407          * note: i don't know what causes this strange behaviour,
 408          *       but even changing the dma speed doesn't solve it :-(
 409          *       the ide performance is still only half the normal speed
 410          *
 411          *       if anybody knows what goes wrong with my machine, please
 412          *       let me know - ASK
 413          */
 414
 415         data |= 0x03;
 416
 417         OUT_BYTE(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 418         OUT_BYTE(data, CY82_DATA_PORT);
 419
 420 #if CY82C693_DEBUG_INFO
 421         printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n", name, data);
 422 #endif /* CY82C693_DEBUG_INFO */
 423
 424 #endif /* CY82C693_SETDMA_CLOCK */
 425         return 0;
 426 }
 427
 428 /*
 429  * the init function - called for each ide channel once
 430  */
 431 void __init ide_init_cy82c693(ide_hwif_t *hwif)
 432 {
 433         hwif->chipset = ide_cy82c693;
 434         hwif->tuneproc = &cy82c693_tune_drive;
 435         if (hwif->dma_base) {
 436                 hwif->dmaproc = &cy82c693_dmaproc;
 437         } else {
 438                 hwif->drives[0].autotune = 1;
 439                 hwif->drives[1].autotune = 1;
 440         }
 441 }
 442