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Merge with Linux 2.3.40.
[linux-2.6/linux-mips.git] / arch / alpha / kernel / core_mcpcia.c
blob847958212449f7a2655adcda7732af169c25361d
1 /*
2 * linux/arch/alpha/kernel/core_mcpcia.c
3 *
4 * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
5 *
6 * Code common to all MCbus-PCI Adaptor core logic chipsets
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/sched.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15
16 #include <asm/ptrace.h>
17 #include <asm/system.h>
18 #include <asm/hwrpb.h>
19
20 #define __EXTERN_INLINE inline
21 #include <asm/io.h>
22 #include <asm/core_mcpcia.h>
23 #undef __EXTERN_INLINE
24
25 #include "proto.h"
26 #include "pci_impl.h"
27
28 /*
29 * NOTE: Herein lie back-to-back mb instructions. They are magic.
30 * One plausible explanation is that the i/o controller does not properly
31 * handle the system transaction. Another involves timing. Ho hum.
32 */
33
34 /*
35 * BIOS32-style PCI interface:
36 */
37
38 #define DEBUG_CFG 0
39
40 #if DEBUG_CFG
41 # define DBG_CFG(args) printk args
42 #else
43 # define DBG_CFG(args)
44 #endif
45
46 #define MCPCIA_MAX_HOSES 4
47
48 /* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively. Durango adds
49 PCI2 and PCI3 at MID 6 and 7 respectively. */
50
51 #define hose2mid(h) ((h) + 4)
52
53
54 /*
55 * Given a bus, device, and function number, compute resulting
56 * configuration space address and setup the MCPCIA_HAXR2 register
57 * accordingly. It is therefore not safe to have concurrent
58 * invocations to configuration space access routines, but there
59 * really shouldn't be any need for this.
60 *
61 * Type 0:
62 *
63 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
64 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
65 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
66 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
67 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
68 *
69 * 31:11 Device select bit.
70 * 10:8 Function number
71 * 7:2 Register number
72 *
73 * Type 1:
74 *
75 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
76 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
77 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
78 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
79 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
80 *
81 * 31:24 reserved
82 * 23:16 bus number (8 bits = 128 possible buses)
83 * 15:11 Device number (5 bits)
84 * 10:8 function number
85 * 7:2 register number
86 *
87 * Notes:
88 * The function number selects which function of a multi-function device
89 * (e.g., SCSI and Ethernet).
90 *
91 * The register selects a DWORD (32 bit) register offset. Hence it
92 * doesn't get shifted by 2 bits as we want to "drop" the bottom two
93 * bits.
94 */
95
96 static unsigned int
97 conf_read(unsigned long addr, unsigned char type1,
98 struct pci_controler *hose)
99 {
100 unsigned long flags;
101 unsigned long mid = hose2mid(hose->index);
102 unsigned int stat0, value, temp, cpu;
103
104 cpu = smp_processor_id();
105
106 __save_and_cli(flags);
107
108 DBG_CFG(("conf_read(addr=0x%lx, type1=%d, hose=%d)\n",
109 addr, type1, mid));
110
111 /* Reset status register to avoid losing errors. */
112 stat0 = *(vuip)MCPCIA_CAP_ERR(mid);
113 *(vuip)MCPCIA_CAP_ERR(mid) = stat0;
114 mb();
115 temp = *(vuip)MCPCIA_CAP_ERR(mid);
116 DBG_CFG(("conf_read: MCPCIA_CAP_ERR(%d) was 0x%x\n", mid, stat0));
117
118 mb();
119 draina();
120 mcheck_expected(cpu) = 1;
121 mcheck_taken(cpu) = 0;
122 mcheck_extra(cpu) = mid;
123 mb();
124
125 /* Access configuration space. */
126 value = *((vuip)addr);
127 mb();
128 mb(); /* magic */
129
130 if (mcheck_taken(cpu)) {
131 mcheck_taken(cpu) = 0;
132 value = 0xffffffffU;
133 mb();
134 }
135 mcheck_expected(cpu) = 0;
136 mb();
137
138 DBG_CFG(("conf_read(): finished\n"));
139
140 __restore_flags(flags);
141 return value;
142 }
143
144 static void
145 conf_write(unsigned long addr, unsigned int value, unsigned char type1,
146 struct pci_controler *hose)
147 {
148 unsigned long flags;
149 unsigned long mid = hose2mid(hose->index);
150 unsigned int stat0, temp, cpu;
151
152 cpu = smp_processor_id();
153
154 __save_and_cli(flags); /* avoid getting hit by machine check */
155
156 /* Reset status register to avoid losing errors. */
157 stat0 = *(vuip)MCPCIA_CAP_ERR(mid);
158 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb();
159 temp = *(vuip)MCPCIA_CAP_ERR(mid);
160 DBG_CFG(("conf_write: MCPCIA CAP_ERR(%d) was 0x%x\n", mid, stat0));
161
162 draina();
163 mcheck_expected(cpu) = 1;
164 mcheck_extra(cpu) = mid;
165 mb();
166
167 /* Access configuration space. */
168 *((vuip)addr) = value;
169 mb();
170 mb(); /* magic */
171 temp = *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */
172 mcheck_expected(cpu) = 0;
173 mb();
174
175 DBG_CFG(("conf_write(): finished\n"));
176 __restore_flags(flags);
177 }
178
179 static int
180 mk_conf_addr(struct pci_dev *dev, int where, struct pci_controler *hose,
181 unsigned long *pci_addr, unsigned char *type1)
182 {
183 u8 bus = dev->bus->number;
184 u8 devfn = dev->devfn;
185 unsigned long addr;
186
187 DBG_CFG(("mk_conf_addr(bus=%d,devfn=0x%x,hose=%d,where=0x%x,"
188 " pci_addr=0x%p, type1=0x%p)\n",
189 bus, devfn, hose->index, where, pci_addr, type1));
190
191 /* Type 1 configuration cycle for *ALL* busses. */
192 *type1 = 1;
193
194 if (dev->bus->number == hose->first_busno)
195 bus = 0;
196 addr = (bus << 16) | (devfn << 8) | (where);
197 addr <<= 5; /* swizzle for SPARSE */
198 addr |= hose->config_space;
199
200 *pci_addr = addr;
201 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
202 return 0;
203 }
204
205 static int
206 mcpcia_read_config_byte(struct pci_dev *dev, int where, u8 *value)
207 {
208 struct pci_controler *hose = dev->sysdata;
209 unsigned long addr, w;
210 unsigned char type1;
211
212 if (mk_conf_addr(dev, where, hose, &addr, &type1))
213 return PCIBIOS_DEVICE_NOT_FOUND;
214
215 addr |= 0x00;
216 w = conf_read(addr, type1, hose);
217 *value = __kernel_extbl(w, where & 3);
218 return PCIBIOS_SUCCESSFUL;
219 }
220
221 static int
222 mcpcia_read_config_word(struct pci_dev *dev, int where, u16 *value)
223 {
224 struct pci_controler *hose = dev->sysdata;
225 unsigned long addr, w;
226 unsigned char type1;
227
228 if (mk_conf_addr(dev, where, hose, &addr, &type1))
229 return PCIBIOS_DEVICE_NOT_FOUND;
230
231 addr |= 0x08;
232 w = conf_read(addr, type1, hose);
233 *value = __kernel_extwl(w, where & 3);
234 return PCIBIOS_SUCCESSFUL;
235 }
236
237 static int
238 mcpcia_read_config_dword(struct pci_dev *dev, int where, u32 *value)
239 {
240 struct pci_controler *hose = dev->sysdata;
241 unsigned long addr;
242 unsigned char type1;
243
244 if (mk_conf_addr(dev, where, hose, &addr, &type1))
245 return PCIBIOS_DEVICE_NOT_FOUND;
246
247 addr |= 0x18;
248 *value = conf_read(addr, type1, hose);
249 return PCIBIOS_SUCCESSFUL;
250 }
251
252 static int
253 mcpcia_write_config(struct pci_dev *dev, int where, u32 value, long mask)
254 {
255 struct pci_controler *hose = dev->sysdata;
256 unsigned long addr;
257 unsigned char type1;
258
259 if (mk_conf_addr(dev, where, hose, &addr, &type1))
260 return PCIBIOS_DEVICE_NOT_FOUND;
261
262 addr |= mask;
263 value = __kernel_insql(value, where & 3);
264 conf_write(addr, value, type1, hose);
265 return PCIBIOS_SUCCESSFUL;
266 }
267
268 static int
269 mcpcia_write_config_byte(struct pci_dev *dev, int where, u8 value)
270 {
271 return mcpcia_write_config(dev, where, value, 0x00);
272 }
273
274 static int
275 mcpcia_write_config_word(struct pci_dev *dev, int where, u16 value)
276 {
277 return mcpcia_write_config(dev, where, value, 0x08);
278 }
279
280 static int
281 mcpcia_write_config_dword(struct pci_dev *dev, int where, u32 value)
282 {
283 return mcpcia_write_config(dev, where, value, 0x18);
284 }
285
286 struct pci_ops mcpcia_pci_ops =
287 {
288 read_byte: mcpcia_read_config_byte,
289 read_word: mcpcia_read_config_word,
290 read_dword: mcpcia_read_config_dword,
291 write_byte: mcpcia_write_config_byte,
292 write_word: mcpcia_write_config_word,
293 write_dword: mcpcia_write_config_dword
294 };
295 \f
296 static int __init
297 mcpcia_probe_hose(int h)
298 {
299 int cpu = smp_processor_id();
300 int mid = hose2mid(h);
301 unsigned int pci_rev;
302
303 /* Gotta be REAL careful. If hose is absent, we get an mcheck. */
304
305 mb();
306 mb();
307 draina();
308 wrmces(7);
309 mcheck_expected(cpu) = 2; /* indicates probing */
310 mcheck_taken(cpu) = 0;
311 mcheck_extra(cpu) = mid;
312 mb();
313
314 /* Access the bus revision word. */
315 pci_rev = *(vuip)MCPCIA_REV(mid);
316
317 mb();
318 mb(); /* magic */
319 if (mcheck_taken(cpu)) {
320 mcheck_taken(cpu) = 0;
321 pci_rev = 0xffffffff;
322 mb();
323 }
324 mcheck_expected(cpu) = 0;
325 mb();
326
327 return (pci_rev >> 16) == PCI_CLASS_BRIDGE_HOST;
328 }
329
330 static void __init
331 mcpcia_new_hose(int h)
332 {
333 struct pci_controler *hose;
334 struct resource *io, *mem, *hae_mem;
335 int mid = hose2mid(h);
336
337 hose = alloc_pci_controler();
338 io = alloc_resource();
339 mem = alloc_resource();
340 hae_mem = alloc_resource();
341
342 hose->io_space = io;
343 hose->mem_space = hae_mem;
344 hose->config_space = MCPCIA_CONF(mid);
345 hose->index = h;
346
347 io->start = MCPCIA_IO(mid) - MCPCIA_IO_BIAS;
348 io->end = io->start + 0xffff;
349 io->name = pci_io_names[h];
350 io->flags = IORESOURCE_IO;
351
352 mem->start = MCPCIA_DENSE(mid) - MCPCIA_MEM_BIAS;
353 mem->end = mem->start + 0xffffffff;
354 mem->name = pci_mem_names[h];
355 mem->flags = IORESOURCE_MEM;
356
357 hae_mem->start = mem->start;
358 hae_mem->end = mem->start + MCPCIA_MEM_MASK;
359 hae_mem->name = pci_hae0_name;
360 hae_mem->flags = IORESOURCE_MEM;
361
362 if (request_resource(&ioport_resource, io) < 0)
363 printk(KERN_ERR "Failed to request IO on hose %d\n", h);
364 if (request_resource(&iomem_resource, mem) < 0)
365 printk(KERN_ERR "Failed to request MEM on hose %d\n", h);
366 if (request_resource(mem, hae_mem) < 0)
367 printk(KERN_ERR "Failed to request HAE_MEM on hose %d\n", h);
368 }
369
370 static void
371 mcpcia_pci_clr_err(int mid)
372 {
373 *(vuip)MCPCIA_CAP_ERR(mid);
374 *(vuip)MCPCIA_CAP_ERR(mid) = 0xffffffff; /* Clear them all. */
375 mb();
376 *(vuip)MCPCIA_CAP_ERR(mid); /* Re-read for force write. */
377 }
378
379 static void __init
380 mcpcia_startup_hose(struct pci_controler *hose)
381 {
382 int mid = hose2mid(hose->index);
383 unsigned int tmp;
384
385 mcpcia_pci_clr_err(mid);
386
387 /*
388 * Set up error reporting.
389 */
390 tmp = *(vuip)MCPCIA_CAP_ERR(mid);
391 tmp |= 0x0006; /* master/target abort */
392 *(vuip)MCPCIA_CAP_ERR(mid) = tmp;
393 mb();
394 tmp = *(vuip)MCPCIA_CAP_ERR(mid);
395
396 /*
397 * Set up the PCI->physical memory translation windows.
398 * For now, windows 1,2 and 3 are disabled. In the
399 * future, we may want to use them to do scatter/
400 * gather DMA.
401 *
402 * Window 0 goes at 2 GB and is 2 GB large.
403 */
404
405 *(vuip)MCPCIA_W0_BASE(mid) = 1U | (MCPCIA_DMA_WIN_BASE & 0xfff00000U);
406 *(vuip)MCPCIA_W0_MASK(mid) = (MCPCIA_DMA_WIN_SIZE - 1) & 0xfff00000U;
407 *(vuip)MCPCIA_T0_BASE(mid) = 0;
408
409 *(vuip)MCPCIA_W1_BASE(mid) = 0x0;
410 *(vuip)MCPCIA_W2_BASE(mid) = 0x0;
411 *(vuip)MCPCIA_W3_BASE(mid) = 0x0;
412
413 *(vuip)MCPCIA_HBASE(mid) = 0x0;
414 mb();
415
416 #if 0
417 tmp = *(vuip)MCPCIA_INT_CTL(mid);
418 printk("mcpcia_startup_hose: INT_CTL was 0x%x\n", tmp);
419 *(vuip)MCPCIA_INT_CTL(mid) = 1U;
420 mb();
421 tmp = *(vuip)MCPCIA_INT_CTL(mid);
422 #endif
423
424 *(vuip)MCPCIA_HAE_MEM(mid) = 0U;
425 mb();
426 *(vuip)MCPCIA_HAE_MEM(mid); /* read it back. */
427 *(vuip)MCPCIA_HAE_IO(mid) = 0;
428 mb();
429 *(vuip)MCPCIA_HAE_IO(mid); /* read it back. */
430 }
431
432 void __init
433 mcpcia_init_arch(void)
434 {
435 /* With multiple PCI busses, we play with I/O as physical addrs. */
436 ioport_resource.end = ~0UL;
437 iomem_resource.end = ~0UL;
438
439 /* Allocate hose 0. That's the one that all the ISA junk hangs
440 off of, from which we'll be registering stuff here in a bit.
441 Other hose detection is done in mcpcia_init_hoses, which is
442 called from init_IRQ. */
443
444 mcpcia_new_hose(0);
445 }
446
447 /* This is called from init_IRQ, since we cannot take interrupts
448 before then. Which means we cannot do this in init_arch. */
449
450 void __init
451 mcpcia_init_hoses(void)
452 {
453 struct pci_controler *hose;
454 int h, hose_count = 0;
455
456 /* First, find how many hoses we have. */
457 for (h = 0; h < MCPCIA_MAX_HOSES; ++h) {
458 if (mcpcia_probe_hose(h)) {
459 if (h != 0)
460 mcpcia_new_hose(h);
461 hose_count++;
462 }
463 }
464
465 printk("mcpcia_init_hoses: found %d hoses\n", hose_count);
466
467 /* Now do init for each hose. */
468 for (hose = hose_head; hose; hose = hose->next)
469 mcpcia_startup_hose(hose);
470 }
471
472 static void
473 mcpcia_print_uncorrectable(struct el_MCPCIA_uncorrected_frame_mcheck *logout)
474 {
475 struct el_common_EV5_uncorrectable_mcheck *frame;
476 int i;
477
478 frame = &logout->procdata;
479
480 /* Print PAL fields */
481 for (i = 0; i < 24; i += 2) {
482 printk(" paltmp[%d-%d] = %16lx %16lx\n",
483 i, i+1, frame->paltemp[i], frame->paltemp[i+1]);
484 }
485 for (i = 0; i < 8; i += 2) {
486 printk(" shadow[%d-%d] = %16lx %16lx\n",
487 i, i+1, frame->shadow[i],
488 frame->shadow[i+1]);
489 }
490 printk(" Addr of excepting instruction = %16lx\n",
491 frame->exc_addr);
492 printk(" Summary of arithmetic traps = %16lx\n",
493 frame->exc_sum);
494 printk(" Exception mask = %16lx\n",
495 frame->exc_mask);
496 printk(" Base address for PALcode = %16lx\n",
497 frame->pal_base);
498 printk(" Interrupt Status Reg = %16lx\n",
499 frame->isr);
500 printk(" CURRENT SETUP OF EV5 IBOX = %16lx\n",
501 frame->icsr);
502 printk(" I-CACHE Reg %s parity error = %16lx\n",
503 (frame->ic_perr_stat & 0x800L) ?
504 "Data" : "Tag",
505 frame->ic_perr_stat);
506 printk(" D-CACHE error Reg = %16lx\n",
507 frame->dc_perr_stat);
508 if (frame->dc_perr_stat & 0x2) {
509 switch (frame->dc_perr_stat & 0x03c) {
510 case 8:
511 printk(" Data error in bank 1\n");
512 break;
513 case 4:
514 printk(" Data error in bank 0\n");
515 break;
516 case 20:
517 printk(" Tag error in bank 1\n");
518 break;
519 case 10:
520 printk(" Tag error in bank 0\n");
521 break;
522 }
523 }
524 printk(" Effective VA = %16lx\n",
525 frame->va);
526 printk(" Reason for D-stream = %16lx\n",
527 frame->mm_stat);
528 printk(" EV5 SCache address = %16lx\n",
529 frame->sc_addr);
530 printk(" EV5 SCache TAG/Data parity = %16lx\n",
531 frame->sc_stat);
532 printk(" EV5 BC_TAG_ADDR = %16lx\n",
533 frame->bc_tag_addr);
534 printk(" EV5 EI_ADDR: Phys addr of Xfer = %16lx\n",
535 frame->ei_addr);
536 printk(" Fill Syndrome = %16lx\n",
537 frame->fill_syndrome);
538 printk(" EI_STAT reg = %16lx\n",
539 frame->ei_stat);
540 printk(" LD_LOCK = %16lx\n",
541 frame->ld_lock);
542 }
543
544 void
545 mcpcia_machine_check(unsigned long vector, unsigned long la_ptr,
546 struct pt_regs * regs)
547 {
548 struct el_common *mchk_header;
549 struct el_MCPCIA_uncorrected_frame_mcheck *mchk_logout;
550 unsigned int cpu = smp_processor_id();
551 int expected;
552
553 mchk_header = (struct el_common *)la_ptr;
554 mchk_logout = (struct el_MCPCIA_uncorrected_frame_mcheck *)la_ptr;
555 expected = mcheck_expected(cpu);
556
557 mb();
558 mb(); /* magic */
559 draina();
560
561 switch (expected) {
562 case 0:
563 {
564 /* FIXME: how do we figure out which hose the
565 error was on? */
566 struct pci_controler *hose;
567 for (hose = hose_head; hose; hose = hose->next)
568 mcpcia_pci_clr_err(hose2mid(hose->index));
569 break;
570 }
571 case 1:
572 mcpcia_pci_clr_err(mcheck_extra(cpu));
573 break;
574 default:
575 /* Otherwise, we're being called from mcpcia_probe_hose
576 and there's no hose clear an error from. */
577 break;
578 }
579
580 wrmces(0x7);
581 mb();
582
583 process_mcheck_info(vector, la_ptr, regs, "MCPCIA", expected != 0);
584 if (!expected && vector != 0x620 && vector != 0x630)
585 mcpcia_print_uncorrectable(mchk_logout);
586 }
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