2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
36 #include <acpi/acpi_bus.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
50 static int assign_irq_vector(int irq
, cpumask_t mask
);
52 #define __apicdebuginit __init
54 int sis_apic_bug
; /* not actually supported, dummy for compile */
56 static int no_timer_check
;
58 static int disable_timer_pin_1 __initdata
;
60 int timer_over_8254 __initdata
= 0;
62 /* Where if anywhere is the i8259 connect in external int mode */
63 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
65 static DEFINE_SPINLOCK(ioapic_lock
);
66 static DEFINE_SPINLOCK(vector_lock
);
69 * # of IRQ routing registers
71 int nr_ioapic_registers
[MAX_IO_APICS
];
74 * Rough estimation of how many shared IRQs there are, can
77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
81 * This is performance-critical, we want to do it O(1)
83 * the indexing order of this array favors 1:1 mappings
84 * between pins and IRQs.
87 static struct irq_pin_list
{
88 short apic
, pin
, next
;
89 } irq_2_pin
[PIN_MAP_SIZE
];
91 #define __DO_ACTION(R, ACTION, FINAL) \
95 struct irq_pin_list *entry = irq_2_pin + irq; \
97 BUG_ON(irq >= NR_IRQS); \
103 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
105 io_apic_modify(entry->apic, reg); \
108 entry = irq_2_pin + entry->next; \
114 struct { u32 w1
, w2
; };
115 struct IO_APIC_route_entry entry
;
118 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
120 union entry_union eu
;
122 spin_lock_irqsave(&ioapic_lock
, flags
);
123 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
124 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
125 spin_unlock_irqrestore(&ioapic_lock
, flags
);
129 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
132 union entry_union eu
;
134 spin_lock_irqsave(&ioapic_lock
, flags
);
135 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
136 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
137 spin_unlock_irqrestore(&ioapic_lock
, flags
);
141 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
144 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
146 BUG_ON(irq
>= NR_IRQS
);
153 io_apic_write(apic
, 0x11 + pin
*2, dest
);
154 reg
= io_apic_read(apic
, 0x10 + pin
*2);
157 io_apic_modify(apic
, reg
);
160 entry
= irq_2_pin
+ entry
->next
;
164 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
171 cpus_and(tmp
, mask
, cpu_online_map
);
175 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
177 vector
= assign_irq_vector(irq
, mask
);
182 cpu_set(vector
>> 8, tmp
);
183 dest
= cpu_mask_to_apicid(tmp
);
186 * Only the high 8 bits are valid.
188 dest
= SET_APIC_LOGICAL_ID(dest
);
190 spin_lock_irqsave(&ioapic_lock
, flags
);
191 __target_IO_APIC_irq(irq
, dest
, vector
& 0xff);
192 set_native_irq_info(irq
, mask
);
193 spin_unlock_irqrestore(&ioapic_lock
, flags
);
198 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
199 * shared ISA-space IRQs, so we have to support them. We are super
200 * fast in the common case, and fast for shared ISA-space IRQs.
202 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
204 static int first_free_entry
= NR_IRQS
;
205 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
207 BUG_ON(irq
>= NR_IRQS
);
209 entry
= irq_2_pin
+ entry
->next
;
211 if (entry
->pin
!= -1) {
212 entry
->next
= first_free_entry
;
213 entry
= irq_2_pin
+ entry
->next
;
214 if (++first_free_entry
>= PIN_MAP_SIZE
)
215 panic("io_apic.c: ran out of irq_2_pin entries!");
222 #define DO_ACTION(name,R,ACTION, FINAL) \
224 static void name##_IO_APIC_irq (unsigned int irq) \
225 __DO_ACTION(R, ACTION, FINAL)
227 DO_ACTION( __mask
, 0, |= 0x00010000, io_apic_sync(entry
->apic
) )
229 DO_ACTION( __unmask
, 0, &= 0xfffeffff, )
232 static void mask_IO_APIC_irq (unsigned int irq
)
236 spin_lock_irqsave(&ioapic_lock
, flags
);
237 __mask_IO_APIC_irq(irq
);
238 spin_unlock_irqrestore(&ioapic_lock
, flags
);
241 static void unmask_IO_APIC_irq (unsigned int irq
)
245 spin_lock_irqsave(&ioapic_lock
, flags
);
246 __unmask_IO_APIC_irq(irq
);
247 spin_unlock_irqrestore(&ioapic_lock
, flags
);
250 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
252 struct IO_APIC_route_entry entry
;
254 /* Check delivery_mode to be sure we're not clearing an SMI pin */
255 entry
= ioapic_read_entry(apic
, pin
);
256 if (entry
.delivery_mode
== dest_SMI
)
259 * Disable it in the IO-APIC irq-routing table:
261 memset(&entry
, 0, sizeof(entry
));
263 ioapic_write_entry(apic
, pin
, entry
);
266 static void clear_IO_APIC (void)
270 for (apic
= 0; apic
< nr_ioapics
; apic
++)
271 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
272 clear_IO_APIC_pin(apic
, pin
);
275 int skip_ioapic_setup
;
278 /* dummy parsing: see setup.c */
280 static int __init
disable_ioapic_setup(char *str
)
282 skip_ioapic_setup
= 1;
285 early_param("noapic", disable_ioapic_setup
);
287 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
288 static int __init
disable_timer_pin_setup(char *arg
)
290 disable_timer_pin_1
= 1;
293 __setup("disable_timer_pin_1", disable_timer_pin_setup
);
295 static int __init
setup_disable_8254_timer(char *s
)
297 timer_over_8254
= -1;
300 static int __init
setup_enable_8254_timer(char *s
)
306 __setup("disable_8254_timer", setup_disable_8254_timer
);
307 __setup("enable_8254_timer", setup_enable_8254_timer
);
311 * Find the IRQ entry number of a certain pin.
313 static int find_irq_entry(int apic
, int pin
, int type
)
317 for (i
= 0; i
< mp_irq_entries
; i
++)
318 if (mp_irqs
[i
].mpc_irqtype
== type
&&
319 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
320 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
321 mp_irqs
[i
].mpc_dstirq
== pin
)
328 * Find the pin to which IRQ[irq] (ISA) is connected
330 static int __init
find_isa_irq_pin(int irq
, int type
)
334 for (i
= 0; i
< mp_irq_entries
; i
++) {
335 int lbus
= mp_irqs
[i
].mpc_srcbus
;
337 if (test_bit(lbus
, mp_bus_not_pci
) &&
338 (mp_irqs
[i
].mpc_irqtype
== type
) &&
339 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
341 return mp_irqs
[i
].mpc_dstirq
;
346 static int __init
find_isa_irq_apic(int irq
, int type
)
350 for (i
= 0; i
< mp_irq_entries
; i
++) {
351 int lbus
= mp_irqs
[i
].mpc_srcbus
;
353 if (test_bit(lbus
, mp_bus_not_pci
) &&
354 (mp_irqs
[i
].mpc_irqtype
== type
) &&
355 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
358 if (i
< mp_irq_entries
) {
360 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
361 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
370 * Find a specific PCI IRQ entry.
371 * Not an __init, possibly needed by modules
373 static int pin_2_irq(int idx
, int apic
, int pin
);
375 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
377 int apic
, i
, best_guess
= -1;
379 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
381 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
382 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
385 for (i
= 0; i
< mp_irq_entries
; i
++) {
386 int lbus
= mp_irqs
[i
].mpc_srcbus
;
388 for (apic
= 0; apic
< nr_ioapics
; apic
++)
389 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
390 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
393 if (!test_bit(lbus
, mp_bus_not_pci
) &&
394 !mp_irqs
[i
].mpc_irqtype
&&
396 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
397 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
399 if (!(apic
|| IO_APIC_IRQ(irq
)))
402 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
405 * Use the first all-but-pin matching entry as a
406 * best-guess fuzzy result for broken mptables.
412 BUG_ON(best_guess
>= NR_IRQS
);
416 /* ISA interrupts are always polarity zero edge triggered,
417 * when listed as conforming in the MP table. */
419 #define default_ISA_trigger(idx) (0)
420 #define default_ISA_polarity(idx) (0)
422 /* PCI interrupts are always polarity one level triggered,
423 * when listed as conforming in the MP table. */
425 #define default_PCI_trigger(idx) (1)
426 #define default_PCI_polarity(idx) (1)
428 static int __init
MPBIOS_polarity(int idx
)
430 int bus
= mp_irqs
[idx
].mpc_srcbus
;
434 * Determine IRQ line polarity (high active or low active):
436 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
438 case 0: /* conforms, ie. bus-type dependent polarity */
439 if (test_bit(bus
, mp_bus_not_pci
))
440 polarity
= default_ISA_polarity(idx
);
442 polarity
= default_PCI_polarity(idx
);
444 case 1: /* high active */
449 case 2: /* reserved */
451 printk(KERN_WARNING
"broken BIOS!!\n");
455 case 3: /* low active */
460 default: /* invalid */
462 printk(KERN_WARNING
"broken BIOS!!\n");
470 static int MPBIOS_trigger(int idx
)
472 int bus
= mp_irqs
[idx
].mpc_srcbus
;
476 * Determine IRQ trigger mode (edge or level sensitive):
478 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
480 case 0: /* conforms, ie. bus-type dependent */
481 if (test_bit(bus
, mp_bus_not_pci
))
482 trigger
= default_ISA_trigger(idx
);
484 trigger
= default_PCI_trigger(idx
);
491 case 2: /* reserved */
493 printk(KERN_WARNING
"broken BIOS!!\n");
502 default: /* invalid */
504 printk(KERN_WARNING
"broken BIOS!!\n");
512 static inline int irq_polarity(int idx
)
514 return MPBIOS_polarity(idx
);
517 static inline int irq_trigger(int idx
)
519 return MPBIOS_trigger(idx
);
522 static int pin_2_irq(int idx
, int apic
, int pin
)
525 int bus
= mp_irqs
[idx
].mpc_srcbus
;
528 * Debugging check, we are in big trouble if this message pops up!
530 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
531 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
533 if (test_bit(bus
, mp_bus_not_pci
)) {
534 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
537 * PCI IRQs are mapped in order
541 irq
+= nr_ioapic_registers
[i
++];
544 BUG_ON(irq
>= NR_IRQS
);
548 static inline int IO_APIC_irq_trigger(int irq
)
552 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
553 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
554 idx
= find_irq_entry(apic
,pin
,mp_INT
);
555 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
556 return irq_trigger(idx
);
560 * nonexistent IRQs are edge default
565 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
566 unsigned int irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_EXTERNAL_VECTOR
, 0 };
568 static int __assign_irq_vector(int irq
, cpumask_t mask
)
571 * NOTE! The local APIC isn't very good at handling
572 * multiple interrupts at the same interrupt level.
573 * As the interrupt level is determined by taking the
574 * vector number and shifting that right by 4, we
575 * want to spread these out a bit so that they don't
576 * all fall in the same interrupt level.
578 * Also, we've got to be careful not to trash gate
579 * 0x80, because int 0x80 is hm, kind of importantish. ;)
584 } pos
[NR_CPUS
] = { [ 0 ... NR_CPUS
- 1] = {FIRST_DEVICE_VECTOR
, 0} };
588 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
590 if (IO_APIC_VECTOR(irq
) > 0)
591 old_vector
= IO_APIC_VECTOR(irq
);
592 if ((old_vector
> 0) && cpu_isset(old_vector
>> 8, mask
)) {
596 for_each_cpu_mask(cpu
, mask
) {
598 vector
= pos
[cpu
].vector
;
599 offset
= pos
[cpu
].offset
;
602 if (vector
>= FIRST_SYSTEM_VECTOR
) {
603 /* If we run out of vectors on large boxen, must share them. */
604 offset
= (offset
+ 1) % 8;
605 vector
= FIRST_DEVICE_VECTOR
+ offset
;
607 if (unlikely(pos
[cpu
].vector
== vector
))
609 if (vector
== IA32_SYSCALL_VECTOR
)
611 if (per_cpu(vector_irq
, cpu
)[vector
] != -1)
614 pos
[cpu
].vector
= vector
;
615 pos
[cpu
].offset
= offset
;
616 if (old_vector
>= 0) {
617 int old_cpu
= old_vector
>> 8;
619 per_cpu(vector_irq
, old_cpu
)[old_vector
] = -1;
621 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
623 IO_APIC_VECTOR(irq
) = vector
;
629 static int assign_irq_vector(int irq
, cpumask_t mask
)
634 spin_lock_irqsave(&vector_lock
, flags
);
635 vector
= __assign_irq_vector(irq
, mask
);
636 spin_unlock_irqrestore(&vector_lock
, flags
);
640 extern void (*interrupt
[NR_IRQS
])(void);
642 static struct irq_chip ioapic_chip
;
644 #define IOAPIC_AUTO -1
645 #define IOAPIC_EDGE 0
646 #define IOAPIC_LEVEL 1
648 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
650 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
651 trigger
== IOAPIC_LEVEL
)
652 set_irq_chip_and_handler(irq
, &ioapic_chip
,
655 set_irq_chip_and_handler(irq
, &ioapic_chip
,
659 static void __init
setup_IO_APIC_irqs(void)
661 struct IO_APIC_route_entry entry
;
662 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
665 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
667 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
668 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
671 * add it to the IO-APIC irq-routing table:
673 memset(&entry
,0,sizeof(entry
));
675 entry
.delivery_mode
= INT_DELIVERY_MODE
;
676 entry
.dest_mode
= INT_DEST_MODE
;
677 entry
.mask
= 0; /* enable IRQ */
678 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
680 idx
= find_irq_entry(apic
,pin
,mp_INT
);
683 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
686 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
690 entry
.trigger
= irq_trigger(idx
);
691 entry
.polarity
= irq_polarity(idx
);
693 if (irq_trigger(idx
)) {
696 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
699 irq
= pin_2_irq(idx
, apic
, pin
);
700 add_pin_to_irq(irq
, apic
, pin
);
702 if (!apic
&& !IO_APIC_IRQ(irq
))
705 if (IO_APIC_IRQ(irq
)) {
707 vector
= assign_irq_vector(irq
, TARGET_CPUS
);
712 cpu_set(vector
>> 8, mask
);
713 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(mask
);
714 entry
.vector
= vector
& 0xff;
716 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
717 if (!apic
&& (irq
< 16))
718 disable_8259A_irq(irq
);
720 ioapic_write_entry(apic
, pin
, entry
);
722 spin_lock_irqsave(&ioapic_lock
, flags
);
723 set_native_irq_info(irq
, TARGET_CPUS
);
724 spin_unlock_irqrestore(&ioapic_lock
, flags
);
729 apic_printk(APIC_VERBOSE
," not connected.\n");
733 * Set up the 8259A-master output pin as broadcast to all
736 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
738 struct IO_APIC_route_entry entry
;
741 memset(&entry
,0,sizeof(entry
));
743 disable_8259A_irq(0);
746 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
749 * We use logical delivery to get the timer IRQ
752 entry
.dest_mode
= INT_DEST_MODE
;
753 entry
.mask
= 0; /* unmask IRQ now */
754 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
755 entry
.delivery_mode
= INT_DELIVERY_MODE
;
758 entry
.vector
= vector
;
761 * The timer IRQ doesn't have to know that behind the
762 * scene we have a 8259A-master in AEOI mode ...
764 set_irq_chip_and_handler(0, &ioapic_chip
, handle_edge_irq
);
767 * Add it to the IO-APIC irq-routing table:
769 spin_lock_irqsave(&ioapic_lock
, flags
);
770 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
771 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
772 spin_unlock_irqrestore(&ioapic_lock
, flags
);
777 void __init
UNEXPECTED_IO_APIC(void)
781 void __apicdebuginit
print_IO_APIC(void)
784 union IO_APIC_reg_00 reg_00
;
785 union IO_APIC_reg_01 reg_01
;
786 union IO_APIC_reg_02 reg_02
;
789 if (apic_verbosity
== APIC_QUIET
)
792 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
793 for (i
= 0; i
< nr_ioapics
; i
++)
794 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
795 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
798 * We are a bit conservative about what we expect. We have to
799 * know about every hardware change ASAP.
801 printk(KERN_INFO
"testing the IO APIC.......................\n");
803 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
805 spin_lock_irqsave(&ioapic_lock
, flags
);
806 reg_00
.raw
= io_apic_read(apic
, 0);
807 reg_01
.raw
= io_apic_read(apic
, 1);
808 if (reg_01
.bits
.version
>= 0x10)
809 reg_02
.raw
= io_apic_read(apic
, 2);
810 spin_unlock_irqrestore(&ioapic_lock
, flags
);
813 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
814 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
815 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
816 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
817 UNEXPECTED_IO_APIC();
819 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
820 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
821 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
822 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
823 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
824 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
825 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
826 (reg_01
.bits
.entries
!= 0x2E) &&
827 (reg_01
.bits
.entries
!= 0x3F) &&
828 (reg_01
.bits
.entries
!= 0x03)
830 UNEXPECTED_IO_APIC();
832 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
833 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
834 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
835 (reg_01
.bits
.version
!= 0x02) && /* 82801BA IO-APICs (ICH2) */
836 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
837 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
838 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
839 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
841 UNEXPECTED_IO_APIC();
842 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
843 UNEXPECTED_IO_APIC();
845 if (reg_01
.bits
.version
>= 0x10) {
846 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
847 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
848 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
849 UNEXPECTED_IO_APIC();
852 printk(KERN_DEBUG
".... IRQ redirection table:\n");
854 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
855 " Stat Dest Deli Vect: \n");
857 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
858 struct IO_APIC_route_entry entry
;
860 entry
= ioapic_read_entry(apic
, i
);
862 printk(KERN_DEBUG
" %02x %03X %02X ",
864 entry
.dest
.logical
.logical_dest
,
865 entry
.dest
.physical
.physical_dest
868 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
873 entry
.delivery_status
,
880 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
881 for (i
= 0; i
< NR_IRQS
; i
++) {
882 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
885 printk(KERN_DEBUG
"IRQ%d ", i
);
887 printk("-> %d:%d", entry
->apic
, entry
->pin
);
890 entry
= irq_2_pin
+ entry
->next
;
895 printk(KERN_INFO
".................................... done.\n");
902 static __apicdebuginit
void print_APIC_bitfield (int base
)
907 if (apic_verbosity
== APIC_QUIET
)
910 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
911 for (i
= 0; i
< 8; i
++) {
912 v
= apic_read(base
+ i
*0x10);
913 for (j
= 0; j
< 32; j
++) {
923 void __apicdebuginit
print_local_APIC(void * dummy
)
925 unsigned int v
, ver
, maxlvt
;
927 if (apic_verbosity
== APIC_QUIET
)
930 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
931 smp_processor_id(), hard_smp_processor_id());
932 v
= apic_read(APIC_ID
);
933 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
934 v
= apic_read(APIC_LVR
);
935 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
936 ver
= GET_APIC_VERSION(v
);
937 maxlvt
= get_maxlvt();
939 v
= apic_read(APIC_TASKPRI
);
940 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
942 v
= apic_read(APIC_ARBPRI
);
943 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
944 v
& APIC_ARBPRI_MASK
);
945 v
= apic_read(APIC_PROCPRI
);
946 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
948 v
= apic_read(APIC_EOI
);
949 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
950 v
= apic_read(APIC_RRR
);
951 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
952 v
= apic_read(APIC_LDR
);
953 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
954 v
= apic_read(APIC_DFR
);
955 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
956 v
= apic_read(APIC_SPIV
);
957 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
959 printk(KERN_DEBUG
"... APIC ISR field:\n");
960 print_APIC_bitfield(APIC_ISR
);
961 printk(KERN_DEBUG
"... APIC TMR field:\n");
962 print_APIC_bitfield(APIC_TMR
);
963 printk(KERN_DEBUG
"... APIC IRR field:\n");
964 print_APIC_bitfield(APIC_IRR
);
966 v
= apic_read(APIC_ESR
);
967 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
969 v
= apic_read(APIC_ICR
);
970 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
971 v
= apic_read(APIC_ICR2
);
972 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
974 v
= apic_read(APIC_LVTT
);
975 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
977 if (maxlvt
> 3) { /* PC is LVT#4. */
978 v
= apic_read(APIC_LVTPC
);
979 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
981 v
= apic_read(APIC_LVT0
);
982 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
983 v
= apic_read(APIC_LVT1
);
984 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
986 if (maxlvt
> 2) { /* ERR is LVT#3. */
987 v
= apic_read(APIC_LVTERR
);
988 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
991 v
= apic_read(APIC_TMICT
);
992 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
993 v
= apic_read(APIC_TMCCT
);
994 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
995 v
= apic_read(APIC_TDCR
);
996 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1000 void print_all_local_APICs (void)
1002 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1005 void __apicdebuginit
print_PIC(void)
1008 unsigned long flags
;
1010 if (apic_verbosity
== APIC_QUIET
)
1013 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1015 spin_lock_irqsave(&i8259A_lock
, flags
);
1017 v
= inb(0xa1) << 8 | inb(0x21);
1018 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1020 v
= inb(0xa0) << 8 | inb(0x20);
1021 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1025 v
= inb(0xa0) << 8 | inb(0x20);
1029 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1031 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1033 v
= inb(0x4d1) << 8 | inb(0x4d0);
1034 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1039 static void __init
enable_IO_APIC(void)
1041 union IO_APIC_reg_01 reg_01
;
1042 int i8259_apic
, i8259_pin
;
1044 unsigned long flags
;
1046 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1047 irq_2_pin
[i
].pin
= -1;
1048 irq_2_pin
[i
].next
= 0;
1052 * The number of IO-APIC IRQ registers (== #pins):
1054 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1055 spin_lock_irqsave(&ioapic_lock
, flags
);
1056 reg_01
.raw
= io_apic_read(apic
, 1);
1057 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1058 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1060 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1062 /* See if any of the pins is in ExtINT mode */
1063 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1064 struct IO_APIC_route_entry entry
;
1065 entry
= ioapic_read_entry(apic
, pin
);
1067 /* If the interrupt line is enabled and in ExtInt mode
1068 * I have found the pin where the i8259 is connected.
1070 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1071 ioapic_i8259
.apic
= apic
;
1072 ioapic_i8259
.pin
= pin
;
1078 /* Look to see what if the MP table has reported the ExtINT */
1079 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1080 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1081 /* Trust the MP table if nothing is setup in the hardware */
1082 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1083 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1084 ioapic_i8259
.pin
= i8259_pin
;
1085 ioapic_i8259
.apic
= i8259_apic
;
1087 /* Complain if the MP table and the hardware disagree */
1088 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1089 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1091 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1095 * Do not trust the IO-APIC being empty at bootup
1101 * Not an __init, needed by the reboot code
1103 void disable_IO_APIC(void)
1106 * Clear the IO-APIC before rebooting:
1111 * If the i8259 is routed through an IOAPIC
1112 * Put that IOAPIC in virtual wire mode
1113 * so legacy interrupts can be delivered.
1115 if (ioapic_i8259
.pin
!= -1) {
1116 struct IO_APIC_route_entry entry
;
1118 memset(&entry
, 0, sizeof(entry
));
1119 entry
.mask
= 0; /* Enabled */
1120 entry
.trigger
= 0; /* Edge */
1122 entry
.polarity
= 0; /* High */
1123 entry
.delivery_status
= 0;
1124 entry
.dest_mode
= 0; /* Physical */
1125 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1127 entry
.dest
.physical
.physical_dest
=
1128 GET_APIC_ID(apic_read(APIC_ID
));
1131 * Add it to the IO-APIC irq-routing table:
1133 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1136 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1140 * There is a nasty bug in some older SMP boards, their mptable lies
1141 * about the timer IRQ. We do the following to work around the situation:
1143 * - timer IRQ defaults to IO-APIC IRQ
1144 * - if this function detects that timer IRQs are defunct, then we fall
1145 * back to ISA timer IRQs
1147 static int __init
timer_irq_works(void)
1149 unsigned long t1
= jiffies
;
1152 /* Let ten ticks pass... */
1153 mdelay((10 * 1000) / HZ
);
1156 * Expect a few ticks at least, to be sure some possible
1157 * glue logic does not lock up after one or two first
1158 * ticks in a non-ExtINT mode. Also the local APIC
1159 * might have cached one ExtINT interrupt. Finally, at
1160 * least one tick may be lost due to delays.
1164 if (jiffies
- t1
> 4)
1170 * In the SMP+IOAPIC case it might happen that there are an unspecified
1171 * number of pending IRQ events unhandled. These cases are very rare,
1172 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1173 * better to do it this way as thus we do not have to be aware of
1174 * 'pending' interrupts in the IRQ path, except at this point.
1177 * Edge triggered needs to resend any interrupt
1178 * that was delayed but this is now handled in the device
1183 * Starting up a edge-triggered IO-APIC interrupt is
1184 * nasty - we need to make sure that we get the edge.
1185 * If it is already asserted for some reason, we need
1186 * return 1 to indicate that is was pending.
1188 * This is not complete - we should be able to fake
1189 * an edge even if it isn't on the 8259A...
1192 static unsigned int startup_ioapic_irq(unsigned int irq
)
1194 int was_pending
= 0;
1195 unsigned long flags
;
1197 spin_lock_irqsave(&ioapic_lock
, flags
);
1199 disable_8259A_irq(irq
);
1200 if (i8259A_irq_pending(irq
))
1203 __unmask_IO_APIC_irq(irq
);
1204 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1209 static int ioapic_retrigger_irq(unsigned int irq
)
1214 vector
= irq_vector
[irq
];
1216 cpu_set(vector
>> 8, mask
);
1218 send_IPI_mask(mask
, vector
& 0xff);
1224 * Level and edge triggered IO-APIC interrupts need different handling,
1225 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1226 * handled with the level-triggered descriptor, but that one has slightly
1227 * more overhead. Level-triggered interrupts cannot be handled with the
1228 * edge-triggered handler, without risking IRQ storms and other ugly
1232 static void ack_apic_edge(unsigned int irq
)
1234 move_native_irq(irq
);
1238 static void ack_apic_level(unsigned int irq
)
1240 int do_unmask_irq
= 0;
1242 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1243 /* If we are moving the irq we need to mask it */
1244 if (unlikely(irq_desc
[irq
].status
& IRQ_MOVE_PENDING
)) {
1246 mask_IO_APIC_irq(irq
);
1251 * We must acknowledge the irq before we move it or the acknowledge will
1252 * not propogate properly.
1256 /* Now we can move and renable the irq */
1257 move_masked_irq(irq
);
1258 if (unlikely(do_unmask_irq
))
1259 unmask_IO_APIC_irq(irq
);
1262 static struct irq_chip ioapic_chip __read_mostly
= {
1264 .startup
= startup_ioapic_irq
,
1265 .mask
= mask_IO_APIC_irq
,
1266 .unmask
= unmask_IO_APIC_irq
,
1267 .ack
= ack_apic_edge
,
1268 .eoi
= ack_apic_level
,
1270 .set_affinity
= set_ioapic_affinity_irq
,
1272 .retrigger
= ioapic_retrigger_irq
,
1275 static inline void init_IO_APIC_traps(void)
1280 * NOTE! The local APIC isn't very good at handling
1281 * multiple interrupts at the same interrupt level.
1282 * As the interrupt level is determined by taking the
1283 * vector number and shifting that right by 4, we
1284 * want to spread these out a bit so that they don't
1285 * all fall in the same interrupt level.
1287 * Also, we've got to be careful not to trash gate
1288 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1290 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1292 if (IO_APIC_IRQ(tmp
) && !IO_APIC_VECTOR(tmp
)) {
1294 * Hmm.. We don't have an entry for this,
1295 * so default to an old-fashioned 8259
1296 * interrupt if we can..
1299 make_8259A_irq(irq
);
1301 /* Strange. Oh, well.. */
1302 irq_desc
[irq
].chip
= &no_irq_chip
;
1307 static void enable_lapic_irq (unsigned int irq
)
1311 v
= apic_read(APIC_LVT0
);
1312 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1315 static void disable_lapic_irq (unsigned int irq
)
1319 v
= apic_read(APIC_LVT0
);
1320 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1323 static void ack_lapic_irq (unsigned int irq
)
1328 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
1330 static struct hw_interrupt_type lapic_irq_type __read_mostly
= {
1331 .typename
= "local-APIC-edge",
1332 .startup
= NULL
, /* startup_irq() not used for IRQ0 */
1333 .shutdown
= NULL
, /* shutdown_irq() not used for IRQ0 */
1334 .enable
= enable_lapic_irq
,
1335 .disable
= disable_lapic_irq
,
1336 .ack
= ack_lapic_irq
,
1337 .end
= end_lapic_irq
,
1340 static void setup_nmi (void)
1343 * Dirty trick to enable the NMI watchdog ...
1344 * We put the 8259A master into AEOI mode and
1345 * unmask on all local APICs LVT0 as NMI.
1347 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1348 * is from Maciej W. Rozycki - so we do not have to EOI from
1349 * the NMI handler or the timer interrupt.
1351 printk(KERN_INFO
"activating NMI Watchdog ...");
1353 enable_NMI_through_LVT0(NULL
);
1359 * This looks a bit hackish but it's about the only one way of sending
1360 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1361 * not support the ExtINT mode, unfortunately. We need to send these
1362 * cycles as some i82489DX-based boards have glue logic that keeps the
1363 * 8259A interrupt line asserted until INTA. --macro
1365 static inline void unlock_ExtINT_logic(void)
1368 struct IO_APIC_route_entry entry0
, entry1
;
1369 unsigned char save_control
, save_freq_select
;
1370 unsigned long flags
;
1372 pin
= find_isa_irq_pin(8, mp_INT
);
1373 apic
= find_isa_irq_apic(8, mp_INT
);
1377 spin_lock_irqsave(&ioapic_lock
, flags
);
1378 *(((int *)&entry0
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
1379 *(((int *)&entry0
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
1380 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1381 clear_IO_APIC_pin(apic
, pin
);
1383 memset(&entry1
, 0, sizeof(entry1
));
1385 entry1
.dest_mode
= 0; /* physical delivery */
1386 entry1
.mask
= 0; /* unmask IRQ now */
1387 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
1388 entry1
.delivery_mode
= dest_ExtINT
;
1389 entry1
.polarity
= entry0
.polarity
;
1393 spin_lock_irqsave(&ioapic_lock
, flags
);
1394 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
1395 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
1396 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1398 save_control
= CMOS_READ(RTC_CONTROL
);
1399 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1400 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1402 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1407 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1411 CMOS_WRITE(save_control
, RTC_CONTROL
);
1412 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1413 clear_IO_APIC_pin(apic
, pin
);
1415 spin_lock_irqsave(&ioapic_lock
, flags
);
1416 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
1417 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
1418 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1422 * This code may look a bit paranoid, but it's supposed to cooperate with
1423 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1424 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1425 * fanatically on his truly buggy board.
1427 * FIXME: really need to revamp this for modern platforms only.
1429 static inline void check_timer(void)
1431 int apic1
, pin1
, apic2
, pin2
;
1435 * get/set the timer IRQ vector:
1437 disable_8259A_irq(0);
1438 vector
= assign_irq_vector(0, TARGET_CPUS
);
1441 * Subtle, code in do_timer_interrupt() expects an AEOI
1442 * mode for the 8259A whenever interrupts are routed
1443 * through I/O APICs. Also IRQ0 has to be enabled in
1444 * the 8259A which implies the virtual wire has to be
1445 * disabled in the local APIC.
1447 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1449 if (timer_over_8254
> 0)
1450 enable_8259A_irq(0);
1452 pin1
= find_isa_irq_pin(0, mp_INT
);
1453 apic1
= find_isa_irq_apic(0, mp_INT
);
1454 pin2
= ioapic_i8259
.pin
;
1455 apic2
= ioapic_i8259
.apic
;
1457 apic_printk(APIC_VERBOSE
,KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1458 vector
, apic1
, pin1
, apic2
, pin2
);
1462 * Ok, does IRQ0 through the IOAPIC work?
1464 unmask_IO_APIC_irq(0);
1465 if (!no_timer_check
&& timer_irq_works()) {
1466 nmi_watchdog_default();
1467 if (nmi_watchdog
== NMI_IO_APIC
) {
1468 disable_8259A_irq(0);
1470 enable_8259A_irq(0);
1472 if (disable_timer_pin_1
> 0)
1473 clear_IO_APIC_pin(0, pin1
);
1476 clear_IO_APIC_pin(apic1
, pin1
);
1477 apic_printk(APIC_QUIET
,KERN_ERR
"..MP-BIOS bug: 8254 timer not "
1478 "connected to IO-APIC\n");
1481 apic_printk(APIC_VERBOSE
,KERN_INFO
"...trying to set up timer (IRQ0) "
1482 "through the 8259A ... ");
1484 apic_printk(APIC_VERBOSE
,"\n..... (found apic %d pin %d) ...",
1487 * legacy devices should be connected to IO APIC #0
1489 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
1490 if (timer_irq_works()) {
1491 apic_printk(APIC_VERBOSE
," works.\n");
1492 nmi_watchdog_default();
1493 if (nmi_watchdog
== NMI_IO_APIC
) {
1499 * Cleanup, just in case ...
1501 clear_IO_APIC_pin(apic2
, pin2
);
1503 apic_printk(APIC_VERBOSE
," failed.\n");
1505 if (nmi_watchdog
== NMI_IO_APIC
) {
1506 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1510 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
1512 disable_8259A_irq(0);
1513 irq_desc
[0].chip
= &lapic_irq_type
;
1514 apic_write(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
1515 enable_8259A_irq(0);
1517 if (timer_irq_works()) {
1518 apic_printk(APIC_VERBOSE
," works.\n");
1521 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
1522 apic_printk(APIC_VERBOSE
," failed.\n");
1524 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
1528 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1530 unlock_ExtINT_logic();
1532 if (timer_irq_works()) {
1533 apic_printk(APIC_VERBOSE
," works.\n");
1536 apic_printk(APIC_VERBOSE
," failed :(.\n");
1537 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1540 static int __init
notimercheck(char *s
)
1545 __setup("no_timer_check", notimercheck
);
1549 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1550 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1551 * Linux doesn't really care, as it's not actually used
1552 * for any interrupt handling anyway.
1554 #define PIC_IRQS (1<<2)
1556 void __init
setup_IO_APIC(void)
1561 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
1563 io_apic_irqs
= ~PIC_IRQS
;
1565 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
1568 setup_IO_APIC_irqs();
1569 init_IO_APIC_traps();
1575 struct sysfs_ioapic_data
{
1576 struct sys_device dev
;
1577 struct IO_APIC_route_entry entry
[0];
1579 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
1581 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1583 struct IO_APIC_route_entry
*entry
;
1584 struct sysfs_ioapic_data
*data
;
1587 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
1588 entry
= data
->entry
;
1589 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
1590 *entry
= ioapic_read_entry(dev
->id
, i
);
1595 static int ioapic_resume(struct sys_device
*dev
)
1597 struct IO_APIC_route_entry
*entry
;
1598 struct sysfs_ioapic_data
*data
;
1599 unsigned long flags
;
1600 union IO_APIC_reg_00 reg_00
;
1603 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
1604 entry
= data
->entry
;
1606 spin_lock_irqsave(&ioapic_lock
, flags
);
1607 reg_00
.raw
= io_apic_read(dev
->id
, 0);
1608 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
1609 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
1610 io_apic_write(dev
->id
, 0, reg_00
.raw
);
1612 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1613 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
1614 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
1619 static struct sysdev_class ioapic_sysdev_class
= {
1620 set_kset_name("ioapic"),
1621 .suspend
= ioapic_suspend
,
1622 .resume
= ioapic_resume
,
1625 static int __init
ioapic_init_sysfs(void)
1627 struct sys_device
* dev
;
1628 int i
, size
, error
= 0;
1630 error
= sysdev_class_register(&ioapic_sysdev_class
);
1634 for (i
= 0; i
< nr_ioapics
; i
++ ) {
1635 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
1636 * sizeof(struct IO_APIC_route_entry
);
1637 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
1638 if (!mp_ioapic_data
[i
]) {
1639 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
1642 memset(mp_ioapic_data
[i
], 0, size
);
1643 dev
= &mp_ioapic_data
[i
]->dev
;
1645 dev
->cls
= &ioapic_sysdev_class
;
1646 error
= sysdev_register(dev
);
1648 kfree(mp_ioapic_data
[i
]);
1649 mp_ioapic_data
[i
] = NULL
;
1650 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
1658 device_initcall(ioapic_init_sysfs
);
1661 * Dynamic irq allocate and deallocation
1663 int create_irq(void)
1665 /* Allocate an unused irq */
1669 unsigned long flags
;
1672 spin_lock_irqsave(&vector_lock
, flags
);
1673 for (new = (NR_IRQS
- 1); new >= 0; new--) {
1674 if (platform_legacy_irq(new))
1676 if (irq_vector
[new] != 0)
1678 vector
= __assign_irq_vector(new, TARGET_CPUS
);
1679 if (likely(vector
> 0))
1683 spin_unlock_irqrestore(&vector_lock
, flags
);
1686 dynamic_irq_init(irq
);
1691 void destroy_irq(unsigned int irq
)
1693 unsigned long flags
;
1695 dynamic_irq_cleanup(irq
);
1697 spin_lock_irqsave(&vector_lock
, flags
);
1698 irq_vector
[irq
] = 0;
1699 spin_unlock_irqrestore(&vector_lock
, flags
);
1703 * MSI mesage composition
1705 #ifdef CONFIG_PCI_MSI
1706 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
1711 vector
= assign_irq_vector(irq
, TARGET_CPUS
);
1716 cpu_set(vector
>> 8, tmp
);
1717 dest
= cpu_mask_to_apicid(tmp
);
1719 msg
->address_hi
= MSI_ADDR_BASE_HI
;
1722 ((INT_DEST_MODE
== 0) ?
1723 MSI_ADDR_DEST_MODE_PHYSICAL
:
1724 MSI_ADDR_DEST_MODE_LOGICAL
) |
1725 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
1726 MSI_ADDR_REDIRECTION_CPU
:
1727 MSI_ADDR_REDIRECTION_LOWPRI
) |
1728 MSI_ADDR_DEST_ID(dest
);
1731 MSI_DATA_TRIGGER_EDGE
|
1732 MSI_DATA_LEVEL_ASSERT
|
1733 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
1734 MSI_DATA_DELIVERY_FIXED
:
1735 MSI_DATA_DELIVERY_LOWPRI
) |
1736 MSI_DATA_VECTOR(vector
);
1742 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
1749 cpus_and(tmp
, mask
, cpu_online_map
);
1750 if (cpus_empty(tmp
))
1753 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
1755 vector
= assign_irq_vector(irq
, mask
);
1760 cpu_set(vector
>> 8, tmp
);
1761 dest
= cpu_mask_to_apicid(tmp
);
1763 read_msi_msg(irq
, &msg
);
1765 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
1766 msg
.data
|= MSI_DATA_VECTOR(vector
);
1767 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
1768 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
1770 write_msi_msg(irq
, &msg
);
1771 set_native_irq_info(irq
, mask
);
1773 #endif /* CONFIG_SMP */
1776 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1777 * which implement the MSI or MSI-X Capability Structure.
1779 static struct irq_chip msi_chip
= {
1781 .unmask
= unmask_msi_irq
,
1782 .mask
= mask_msi_irq
,
1783 .ack
= ack_apic_edge
,
1785 .set_affinity
= set_msi_irq_affinity
,
1787 .retrigger
= ioapic_retrigger_irq
,
1790 int arch_setup_msi_irq(unsigned int irq
, struct pci_dev
*dev
)
1794 ret
= msi_compose_msg(dev
, irq
, &msg
);
1798 write_msi_msg(irq
, &msg
);
1800 set_irq_chip_and_handler(irq
, &msi_chip
, handle_edge_irq
);
1805 void arch_teardown_msi_irq(unsigned int irq
)
1810 #endif /* CONFIG_PCI_MSI */
1813 * Hypertransport interrupt support
1815 #ifdef CONFIG_HT_IRQ
1819 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
1822 low
= read_ht_irq_low(irq
);
1823 high
= read_ht_irq_high(irq
);
1825 low
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
1826 high
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
1828 low
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
1829 high
|= HT_IRQ_HIGH_DEST_ID(dest
);
1831 write_ht_irq_low(irq
, low
);
1832 write_ht_irq_high(irq
, high
);
1835 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
1841 cpus_and(tmp
, mask
, cpu_online_map
);
1842 if (cpus_empty(tmp
))
1845 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
1847 vector
= assign_irq_vector(irq
, mask
);
1852 cpu_set(vector
>> 8, tmp
);
1853 dest
= cpu_mask_to_apicid(tmp
);
1855 target_ht_irq(irq
, dest
, vector
& 0xff);
1856 set_native_irq_info(irq
, mask
);
1860 static struct hw_interrupt_type ht_irq_chip
= {
1862 .mask
= mask_ht_irq
,
1863 .unmask
= unmask_ht_irq
,
1864 .ack
= ack_apic_edge
,
1866 .set_affinity
= set_ht_irq_affinity
,
1868 .retrigger
= ioapic_retrigger_irq
,
1871 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
1875 vector
= assign_irq_vector(irq
, TARGET_CPUS
);
1882 cpu_set(vector
>> 8, tmp
);
1883 dest
= cpu_mask_to_apicid(tmp
);
1885 high
= HT_IRQ_HIGH_DEST_ID(dest
);
1887 low
= HT_IRQ_LOW_BASE
|
1888 HT_IRQ_LOW_DEST_ID(dest
) |
1889 HT_IRQ_LOW_VECTOR(vector
) |
1890 ((INT_DEST_MODE
== 0) ?
1891 HT_IRQ_LOW_DM_PHYSICAL
:
1892 HT_IRQ_LOW_DM_LOGICAL
) |
1893 HT_IRQ_LOW_RQEOI_EDGE
|
1894 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
1895 HT_IRQ_LOW_MT_FIXED
:
1896 HT_IRQ_LOW_MT_ARBITRATED
);
1898 write_ht_irq_low(irq
, low
);
1899 write_ht_irq_high(irq
, high
);
1901 set_irq_chip_and_handler(irq
, &ht_irq_chip
, handle_edge_irq
);
1905 #endif /* CONFIG_HT_IRQ */
1907 /* --------------------------------------------------------------------------
1908 ACPI-based IOAPIC Configuration
1909 -------------------------------------------------------------------------- */
1913 #define IO_APIC_MAX_ID 0xFE
1915 int __init
io_apic_get_redir_entries (int ioapic
)
1917 union IO_APIC_reg_01 reg_01
;
1918 unsigned long flags
;
1920 spin_lock_irqsave(&ioapic_lock
, flags
);
1921 reg_01
.raw
= io_apic_read(ioapic
, 1);
1922 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1924 return reg_01
.bits
.entries
;
1928 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
1930 struct IO_APIC_route_entry entry
;
1931 unsigned long flags
;
1935 if (!IO_APIC_IRQ(irq
)) {
1936 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
1942 * IRQs < 16 are already in the irq_2_pin[] map
1945 add_pin_to_irq(irq
, ioapic
, pin
);
1948 vector
= assign_irq_vector(irq
, TARGET_CPUS
);
1953 cpu_set(vector
>> 8, mask
);
1956 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1957 * Note that we mask (disable) IRQs now -- these get enabled when the
1958 * corresponding device driver registers for this IRQ.
1961 memset(&entry
,0,sizeof(entry
));
1963 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1964 entry
.dest_mode
= INT_DEST_MODE
;
1965 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(mask
);
1966 entry
.trigger
= triggering
;
1967 entry
.polarity
= polarity
;
1968 entry
.mask
= 1; /* Disabled (masked) */
1969 entry
.vector
= vector
& 0xff;
1971 apic_printk(APIC_VERBOSE
,KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1972 "IRQ %d Mode:%i Active:%i)\n", ioapic
,
1973 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
1974 triggering
, polarity
);
1976 ioapic_register_intr(irq
, entry
.vector
, triggering
);
1978 if (!ioapic
&& (irq
< 16))
1979 disable_8259A_irq(irq
);
1981 ioapic_write_entry(ioapic
, pin
, entry
);
1983 spin_lock_irqsave(&ioapic_lock
, flags
);
1984 set_native_irq_info(irq
, TARGET_CPUS
);
1985 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1990 #endif /* CONFIG_ACPI */
1994 * This function currently is only a helper for the i386 smp boot process where
1995 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1996 * so mask in all cases should simply be TARGET_CPUS
1999 void __init
setup_ioapic_dest(void)
2001 int pin
, ioapic
, irq
, irq_entry
;
2003 if (skip_ioapic_setup
== 1)
2006 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2007 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2008 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2009 if (irq_entry
== -1)
2011 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2012 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);