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[PATCH] dz: Fixes to make it work
[linux-2.6/linux-mips.git] / drivers / ieee1394 / csr.c
blobab0c80f61b9d184152d6ed2005cfae5f360e7835
1 /*
2 * IEEE 1394 for Linux
3 *
4 * CSR implementation, iso/bus manager implementation.
5 *
6 * Copyright (C) 1999 Andreas E. Bombe
7 * 2002 Manfred Weihs <weihs@ict.tuwien.ac.at>
8 *
9 * This code is licensed under the GPL. See the file COPYING in the root
10 * directory of the kernel sources for details.
11 *
12 *
13 * Contributions:
14 *
15 * Manfred Weihs <weihs@ict.tuwien.ac.at>
16 * configuration ROM manipulation
17 *
18 */
19
20 #include <linux/jiffies.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/param.h>
25 #include <linux/spinlock.h>
26 #include <linux/string.h>
27
28 #include "csr1212.h"
29 #include "ieee1394_types.h"
30 #include "hosts.h"
31 #include "ieee1394.h"
32 #include "highlevel.h"
33 #include "ieee1394_core.h"
34
35 /* Module Parameters */
36 /* this module parameter can be used to disable mapping of the FCP registers */
37
38 static int fcp = 1;
39 module_param(fcp, int, 0444);
40 MODULE_PARM_DESC(fcp, "Map FCP registers (default = 1, disable = 0).");
41
42 static struct csr1212_keyval *node_cap = NULL;
43
44 static void add_host(struct hpsb_host *host);
45 static void remove_host(struct hpsb_host *host);
46 static void host_reset(struct hpsb_host *host);
47 static int read_maps(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
48 u64 addr, size_t length, u16 fl);
49 static int write_fcp(struct hpsb_host *host, int nodeid, int dest,
50 quadlet_t *data, u64 addr, size_t length, u16 flags);
51 static int read_regs(struct hpsb_host *host, int nodeid, quadlet_t *buf,
52 u64 addr, size_t length, u16 flags);
53 static int write_regs(struct hpsb_host *host, int nodeid, int destid,
54 quadlet_t *data, u64 addr, size_t length, u16 flags);
55 static int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store,
56 u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl);
57 static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store,
58 u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl);
59 static int read_config_rom(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
60 u64 addr, size_t length, u16 fl);
61 static u64 allocate_addr_range(u64 size, u32 alignment, void *__host);
62 static void release_addr_range(u64 addr, void *__host);
63
64 static struct hpsb_highlevel csr_highlevel = {
65 .name = "standard registers",
66 .add_host = add_host,
67 .remove_host = remove_host,
68 .host_reset = host_reset,
69 };
70
71 static struct hpsb_address_ops map_ops = {
72 .read = read_maps,
73 };
74
75 static struct hpsb_address_ops fcp_ops = {
76 .write = write_fcp,
77 };
78
79 static struct hpsb_address_ops reg_ops = {
80 .read = read_regs,
81 .write = write_regs,
82 .lock = lock_regs,
83 .lock64 = lock64_regs,
84 };
85
86 static struct hpsb_address_ops config_rom_ops = {
87 .read = read_config_rom,
88 };
89
90 struct csr1212_bus_ops csr_bus_ops = {
91 .allocate_addr_range = allocate_addr_range,
92 .release_addr = release_addr_range,
93 };
94
95
96 static u16 csr_crc16(unsigned *data, int length)
97 {
98 int check=0, i;
99 int shift, sum, next=0;
100
101 for (i = length; i; i--) {
102 for (next = check, shift = 28; shift >= 0; shift -= 4 ) {
103 sum = ((next >> 12) ^ (be32_to_cpu(*data) >> shift)) & 0xf;
104 next = (next << 4) ^ (sum << 12) ^ (sum << 5) ^ (sum);
105 }
106 check = next & 0xffff;
107 data++;
108 }
109
110 return check;
111 }
112
113 static void host_reset(struct hpsb_host *host)
114 {
115 host->csr.state &= 0x300;
116
117 host->csr.bus_manager_id = 0x3f;
118 host->csr.bandwidth_available = 4915;
119 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */
120 host->csr.channels_available_lo = ~0;
121 host->csr.broadcast_channel = 0x80000000 | 31;
122
123 if (host->is_irm) {
124 if (host->driver->hw_csr_reg) {
125 host->driver->hw_csr_reg(host, 2, 0xfffffffe, ~0);
126 }
127 }
128
129 host->csr.node_ids = host->node_id << 16;
130
131 if (!host->is_root) {
132 /* clear cmstr bit */
133 host->csr.state &= ~0x100;
134 }
135
136 host->csr.topology_map[1] =
137 cpu_to_be32(be32_to_cpu(host->csr.topology_map[1]) + 1);
138 host->csr.topology_map[2] = cpu_to_be32(host->node_count << 16
139 | host->selfid_count);
140 host->csr.topology_map[0] =
141 cpu_to_be32((host->selfid_count + 2) << 16
142 | csr_crc16(host->csr.topology_map + 1,
143 host->selfid_count + 2));
144
145 host->csr.speed_map[1] =
146 cpu_to_be32(be32_to_cpu(host->csr.speed_map[1]) + 1);
147 host->csr.speed_map[0] = cpu_to_be32(0x3f1 << 16
148 | csr_crc16(host->csr.speed_map+1,
149 0x3f1));
150 }
151
152 /*
153 * HI == seconds (bits 0:2)
154 * LO == fractions of a second in units of 125usec (bits 19:31)
155 *
156 * Convert SPLIT_TIMEOUT to jiffies.
157 * The default and minimum as per 1394a-2000 clause 8.3.2.2.6 is 100ms.
158 */
159 static inline void calculate_expire(struct csr_control *csr)
160 {
161 unsigned long usecs =
162 (csr->split_timeout_hi & 0x07) * USEC_PER_SEC +
163 (csr->split_timeout_lo >> 19) * 125L;
164
165 csr->expire = usecs_to_jiffies(usecs > 100000L ? usecs : 100000L);
166
167 HPSB_VERBOSE("CSR: setting expire to %lu, HZ=%u", csr->expire, HZ);
168 }
169
170
171 static void add_host(struct hpsb_host *host)
172 {
173 struct csr1212_keyval *root;
174 quadlet_t bus_info[CSR_BUS_INFO_SIZE];
175
176 hpsb_register_addrspace(&csr_highlevel, host, &reg_ops,
177 CSR_REGISTER_BASE,
178 CSR_REGISTER_BASE + CSR_CONFIG_ROM);
179 hpsb_register_addrspace(&csr_highlevel, host, &config_rom_ops,
180 CSR_REGISTER_BASE + CSR_CONFIG_ROM,
181 CSR_REGISTER_BASE + CSR_CONFIG_ROM_END);
182 if (fcp) {
183 hpsb_register_addrspace(&csr_highlevel, host, &fcp_ops,
184 CSR_REGISTER_BASE + CSR_FCP_COMMAND,
185 CSR_REGISTER_BASE + CSR_FCP_END);
186 }
187 hpsb_register_addrspace(&csr_highlevel, host, &map_ops,
188 CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP,
189 CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP_END);
190 hpsb_register_addrspace(&csr_highlevel, host, &map_ops,
191 CSR_REGISTER_BASE + CSR_SPEED_MAP,
192 CSR_REGISTER_BASE + CSR_SPEED_MAP_END);
193
194 spin_lock_init(&host->csr.lock);
195
196 host->csr.state = 0;
197 host->csr.node_ids = 0;
198 host->csr.split_timeout_hi = 0;
199 host->csr.split_timeout_lo = 800 << 19;
200 calculate_expire(&host->csr);
201 host->csr.cycle_time = 0;
202 host->csr.bus_time = 0;
203 host->csr.bus_manager_id = 0x3f;
204 host->csr.bandwidth_available = 4915;
205 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */
206 host->csr.channels_available_lo = ~0;
207 host->csr.broadcast_channel = 0x80000000 | 31;
208
209 if (host->is_irm) {
210 if (host->driver->hw_csr_reg) {
211 host->driver->hw_csr_reg(host, 2, 0xfffffffe, ~0);
212 }
213 }
214
215 if (host->csr.max_rec >= 9)
216 host->csr.max_rom = 2;
217 else if (host->csr.max_rec >= 5)
218 host->csr.max_rom = 1;
219 else
220 host->csr.max_rom = 0;
221
222 host->csr.generation = 2;
223
224 bus_info[1] = __constant_cpu_to_be32(0x31333934);
225 bus_info[2] = cpu_to_be32((hpsb_disable_irm ? 0 : 1 << CSR_IRMC_SHIFT) |
226 (1 << CSR_CMC_SHIFT) |
227 (1 << CSR_ISC_SHIFT) |
228 (0 << CSR_BMC_SHIFT) |
229 (0 << CSR_PMC_SHIFT) |
230 (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) |
231 (host->csr.max_rec << CSR_MAX_REC_SHIFT) |
232 (host->csr.max_rom << CSR_MAX_ROM_SHIFT) |
233 (host->csr.generation << CSR_GENERATION_SHIFT) |
234 host->csr.lnk_spd);
235
236 bus_info[3] = cpu_to_be32(host->csr.guid_hi);
237 bus_info[4] = cpu_to_be32(host->csr.guid_lo);
238
239 /* The hardware copy of the bus info block will be set later when a
240 * bus reset is issued. */
241
242 csr1212_init_local_csr(host->csr.rom, bus_info, host->csr.max_rom);
243
244 root = host->csr.rom->root_kv;
245
246 if(csr1212_attach_keyval_to_directory(root, node_cap) != CSR1212_SUCCESS) {
247 HPSB_ERR("Failed to attach Node Capabilities to root directory");
248 }
249
250 host->update_config_rom = 1;
251 }
252
253 static void remove_host(struct hpsb_host *host)
254 {
255 quadlet_t bus_info[CSR_BUS_INFO_SIZE];
256
257 bus_info[1] = __constant_cpu_to_be32(0x31333934);
258 bus_info[2] = cpu_to_be32((0 << CSR_IRMC_SHIFT) |
259 (0 << CSR_CMC_SHIFT) |
260 (0 << CSR_ISC_SHIFT) |
261 (0 << CSR_BMC_SHIFT) |
262 (0 << CSR_PMC_SHIFT) |
263 (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) |
264 (host->csr.max_rec << CSR_MAX_REC_SHIFT) |
265 (0 << CSR_MAX_ROM_SHIFT) |
266 (0 << CSR_GENERATION_SHIFT) |
267 host->csr.lnk_spd);
268
269 bus_info[3] = cpu_to_be32(host->csr.guid_hi);
270 bus_info[4] = cpu_to_be32(host->csr.guid_lo);
271
272 csr1212_detach_keyval_from_directory(host->csr.rom->root_kv, node_cap);
273
274 csr1212_init_local_csr(host->csr.rom, bus_info, 0);
275 host->update_config_rom = 1;
276 }
277
278
279 int hpsb_update_config_rom(struct hpsb_host *host, const quadlet_t *new_rom,
280 size_t buffersize, unsigned char rom_version)
281 {
282 unsigned long flags;
283 int ret;
284
285 HPSB_NOTICE("hpsb_update_config_rom() is deprecated");
286
287 spin_lock_irqsave(&host->csr.lock, flags);
288 if (rom_version != host->csr.generation)
289 ret = -1;
290 else if (buffersize > host->csr.rom->cache_head->size)
291 ret = -2;
292 else {
293 /* Just overwrite the generated ConfigROM image with new data,
294 * it can be regenerated later. */
295 memcpy(host->csr.rom->cache_head->data, new_rom, buffersize);
296 host->csr.rom->cache_head->len = buffersize;
297
298 if (host->driver->set_hw_config_rom)
299 host->driver->set_hw_config_rom(host, host->csr.rom->bus_info_data);
300 /* Increment the generation number to keep some sort of sync
301 * with the newer ConfigROM manipulation method. */
302 host->csr.generation++;
303 if (host->csr.generation > 0xf || host->csr.generation < 2)
304 host->csr.generation = 2;
305 ret=0;
306 }
307 spin_unlock_irqrestore(&host->csr.lock, flags);
308 return ret;
309 }
310
311
312 /* Read topology / speed maps and configuration ROM */
313 static int read_maps(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
314 u64 addr, size_t length, u16 fl)
315 {
316 unsigned long flags;
317 int csraddr = addr - CSR_REGISTER_BASE;
318 const char *src;
319
320 spin_lock_irqsave(&host->csr.lock, flags);
321
322 if (csraddr < CSR_SPEED_MAP) {
323 src = ((char *)host->csr.topology_map) + csraddr
324 - CSR_TOPOLOGY_MAP;
325 } else {
326 src = ((char *)host->csr.speed_map) + csraddr - CSR_SPEED_MAP;
327 }
328
329 memcpy(buffer, src, length);
330 spin_unlock_irqrestore(&host->csr.lock, flags);
331 return RCODE_COMPLETE;
332 }
333
334
335 #define out if (--length == 0) break
336
337 static int read_regs(struct hpsb_host *host, int nodeid, quadlet_t *buf,
338 u64 addr, size_t length, u16 flags)
339 {
340 int csraddr = addr - CSR_REGISTER_BASE;
341 int oldcycle;
342 quadlet_t ret;
343
344 if ((csraddr | length) & 0x3)
345 return RCODE_TYPE_ERROR;
346
347 length /= 4;
348
349 switch (csraddr) {
350 case CSR_STATE_CLEAR:
351 *(buf++) = cpu_to_be32(host->csr.state);
352 out;
353 case CSR_STATE_SET:
354 *(buf++) = cpu_to_be32(host->csr.state);
355 out;
356 case CSR_NODE_IDS:
357 *(buf++) = cpu_to_be32(host->csr.node_ids);
358 out;
359
360 case CSR_RESET_START:
361 return RCODE_TYPE_ERROR;
362
363 /* address gap - handled by default below */
364
365 case CSR_SPLIT_TIMEOUT_HI:
366 *(buf++) = cpu_to_be32(host->csr.split_timeout_hi);
367 out;
368 case CSR_SPLIT_TIMEOUT_LO:
369 *(buf++) = cpu_to_be32(host->csr.split_timeout_lo);
370 out;
371
372 /* address gap */
373 return RCODE_ADDRESS_ERROR;
374
375 case CSR_CYCLE_TIME:
376 oldcycle = host->csr.cycle_time;
377 host->csr.cycle_time =
378 host->driver->devctl(host, GET_CYCLE_COUNTER, 0);
379
380 if (oldcycle > host->csr.cycle_time) {
381 /* cycle time wrapped around */
382 host->csr.bus_time += 1 << 7;
383 }
384 *(buf++) = cpu_to_be32(host->csr.cycle_time);
385 out;
386 case CSR_BUS_TIME:
387 oldcycle = host->csr.cycle_time;
388 host->csr.cycle_time =
389 host->driver->devctl(host, GET_CYCLE_COUNTER, 0);
390
391 if (oldcycle > host->csr.cycle_time) {
392 /* cycle time wrapped around */
393 host->csr.bus_time += (1 << 7);
394 }
395 *(buf++) = cpu_to_be32(host->csr.bus_time
396 | (host->csr.cycle_time >> 25));
397 out;
398
399 /* address gap */
400 return RCODE_ADDRESS_ERROR;
401
402 case CSR_BUSY_TIMEOUT:
403 /* not yet implemented */
404 return RCODE_ADDRESS_ERROR;
405
406 case CSR_BUS_MANAGER_ID:
407 if (host->driver->hw_csr_reg)
408 ret = host->driver->hw_csr_reg(host, 0, 0, 0);
409 else
410 ret = host->csr.bus_manager_id;
411
412 *(buf++) = cpu_to_be32(ret);
413 out;
414 case CSR_BANDWIDTH_AVAILABLE:
415 if (host->driver->hw_csr_reg)
416 ret = host->driver->hw_csr_reg(host, 1, 0, 0);
417 else
418 ret = host->csr.bandwidth_available;
419
420 *(buf++) = cpu_to_be32(ret);
421 out;
422 case CSR_CHANNELS_AVAILABLE_HI:
423 if (host->driver->hw_csr_reg)
424 ret = host->driver->hw_csr_reg(host, 2, 0, 0);
425 else
426 ret = host->csr.channels_available_hi;
427
428 *(buf++) = cpu_to_be32(ret);
429 out;
430 case CSR_CHANNELS_AVAILABLE_LO:
431 if (host->driver->hw_csr_reg)
432 ret = host->driver->hw_csr_reg(host, 3, 0, 0);
433 else
434 ret = host->csr.channels_available_lo;
435
436 *(buf++) = cpu_to_be32(ret);
437 out;
438
439 case CSR_BROADCAST_CHANNEL:
440 *(buf++) = cpu_to_be32(host->csr.broadcast_channel);
441 out;
442
443 /* address gap to end - fall through to default */
444 default:
445 return RCODE_ADDRESS_ERROR;
446 }
447
448 return RCODE_COMPLETE;
449 }
450
451 static int write_regs(struct hpsb_host *host, int nodeid, int destid,
452 quadlet_t *data, u64 addr, size_t length, u16 flags)
453 {
454 int csraddr = addr - CSR_REGISTER_BASE;
455
456 if ((csraddr | length) & 0x3)
457 return RCODE_TYPE_ERROR;
458
459 length /= 4;
460
461 switch (csraddr) {
462 case CSR_STATE_CLEAR:
463 /* FIXME FIXME FIXME */
464 printk("doh, someone wants to mess with state clear\n");
465 out;
466 case CSR_STATE_SET:
467 printk("doh, someone wants to mess with state set\n");
468 out;
469
470 case CSR_NODE_IDS:
471 host->csr.node_ids &= NODE_MASK << 16;
472 host->csr.node_ids |= be32_to_cpu(*(data++)) & (BUS_MASK << 16);
473 host->node_id = host->csr.node_ids >> 16;
474 host->driver->devctl(host, SET_BUS_ID, host->node_id >> 6);
475 out;
476
477 case CSR_RESET_START:
478 /* FIXME - perform command reset */
479 out;
480
481 /* address gap */
482 return RCODE_ADDRESS_ERROR;
483
484 case CSR_SPLIT_TIMEOUT_HI:
485 host->csr.split_timeout_hi =
486 be32_to_cpu(*(data++)) & 0x00000007;
487 calculate_expire(&host->csr);
488 out;
489 case CSR_SPLIT_TIMEOUT_LO:
490 host->csr.split_timeout_lo =
491 be32_to_cpu(*(data++)) & 0xfff80000;
492 calculate_expire(&host->csr);
493 out;
494
495 /* address gap */
496 return RCODE_ADDRESS_ERROR;
497
498 case CSR_CYCLE_TIME:
499 /* should only be set by cycle start packet, automatically */
500 host->csr.cycle_time = be32_to_cpu(*data);
501 host->driver->devctl(host, SET_CYCLE_COUNTER,
502 be32_to_cpu(*(data++)));
503 out;
504 case CSR_BUS_TIME:
505 host->csr.bus_time = be32_to_cpu(*(data++)) & 0xffffff80;
506 out;
507
508 /* address gap */
509 return RCODE_ADDRESS_ERROR;
510
511 case CSR_BUSY_TIMEOUT:
512 /* not yet implemented */
513 return RCODE_ADDRESS_ERROR;
514
515 case CSR_BUS_MANAGER_ID:
516 case CSR_BANDWIDTH_AVAILABLE:
517 case CSR_CHANNELS_AVAILABLE_HI:
518 case CSR_CHANNELS_AVAILABLE_LO:
519 /* these are not writable, only lockable */
520 return RCODE_TYPE_ERROR;
521
522 case CSR_BROADCAST_CHANNEL:
523 /* only the valid bit can be written */
524 host->csr.broadcast_channel = (host->csr.broadcast_channel & ~0x40000000)
525 | (be32_to_cpu(*data) & 0x40000000);
526 out;
527
528 /* address gap to end - fall through */
529 default:
530 return RCODE_ADDRESS_ERROR;
531 }
532
533 return RCODE_COMPLETE;
534 }
535
536 #undef out
537
538
539 static int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store,
540 u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl)
541 {
542 int csraddr = addr - CSR_REGISTER_BASE;
543 unsigned long flags;
544 quadlet_t *regptr = NULL;
545
546 if (csraddr & 0x3)
547 return RCODE_TYPE_ERROR;
548
549 if (csraddr < CSR_BUS_MANAGER_ID || csraddr > CSR_CHANNELS_AVAILABLE_LO
550 || extcode != EXTCODE_COMPARE_SWAP)
551 goto unsupported_lockreq;
552
553 data = be32_to_cpu(data);
554 arg = be32_to_cpu(arg);
555
556 /* Is somebody releasing the broadcast_channel on us? */
557 if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x1)) {
558 /* Note: this is may not be the right way to handle
559 * the problem, so we should look into the proper way
560 * eventually. */
561 HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release "
562 "broadcast channel 31. Ignoring.",
563 NODE_BUS_ARGS(host, nodeid));
564
565 data &= ~0x1; /* keep broadcast channel allocated */
566 }
567
568 if (host->driver->hw_csr_reg) {
569 quadlet_t old;
570
571 old = host->driver->
572 hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2,
573 data, arg);
574
575 *store = cpu_to_be32(old);
576 return RCODE_COMPLETE;
577 }
578
579 spin_lock_irqsave(&host->csr.lock, flags);
580
581 switch (csraddr) {
582 case CSR_BUS_MANAGER_ID:
583 regptr = &host->csr.bus_manager_id;
584 *store = cpu_to_be32(*regptr);
585 if (*regptr == arg)
586 *regptr = data;
587 break;
588
589 case CSR_BANDWIDTH_AVAILABLE:
590 {
591 quadlet_t bandwidth;
592 quadlet_t old;
593 quadlet_t new;
594
595 regptr = &host->csr.bandwidth_available;
596 old = *regptr;
597
598 /* bandwidth available algorithm adapted from IEEE 1394a-2000 spec */
599 if (arg > 0x1fff) {
600 *store = cpu_to_be32(old); /* change nothing */
601 break;
602 }
603 data &= 0x1fff;
604 if (arg >= data) {
605 /* allocate bandwidth */
606 bandwidth = arg - data;
607 if (old >= bandwidth) {
608 new = old - bandwidth;
609 *store = cpu_to_be32(arg);
610 *regptr = new;
611 } else {
612 *store = cpu_to_be32(old);
613 }
614 } else {
615 /* deallocate bandwidth */
616 bandwidth = data - arg;
617 if (old + bandwidth < 0x2000) {
618 new = old + bandwidth;
619 *store = cpu_to_be32(arg);
620 *regptr = new;
621 } else {
622 *store = cpu_to_be32(old);
623 }
624 }
625 break;
626 }
627
628 case CSR_CHANNELS_AVAILABLE_HI:
629 {
630 /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */
631 quadlet_t affected_channels = arg ^ data;
632
633 regptr = &host->csr.channels_available_hi;
634
635 if ((arg & affected_channels) == (*regptr & affected_channels)) {
636 *regptr ^= affected_channels;
637 *store = cpu_to_be32(arg);
638 } else {
639 *store = cpu_to_be32(*regptr);
640 }
641
642 break;
643 }
644
645 case CSR_CHANNELS_AVAILABLE_LO:
646 {
647 /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */
648 quadlet_t affected_channels = arg ^ data;
649
650 regptr = &host->csr.channels_available_lo;
651
652 if ((arg & affected_channels) == (*regptr & affected_channels)) {
653 *regptr ^= affected_channels;
654 *store = cpu_to_be32(arg);
655 } else {
656 *store = cpu_to_be32(*regptr);
657 }
658 break;
659 }
660 }
661
662 spin_unlock_irqrestore(&host->csr.lock, flags);
663
664 return RCODE_COMPLETE;
665
666 unsupported_lockreq:
667 switch (csraddr) {
668 case CSR_STATE_CLEAR:
669 case CSR_STATE_SET:
670 case CSR_RESET_START:
671 case CSR_NODE_IDS:
672 case CSR_SPLIT_TIMEOUT_HI:
673 case CSR_SPLIT_TIMEOUT_LO:
674 case CSR_CYCLE_TIME:
675 case CSR_BUS_TIME:
676 case CSR_BROADCAST_CHANNEL:
677 return RCODE_TYPE_ERROR;
678
679 case CSR_BUSY_TIMEOUT:
680 /* not yet implemented - fall through */
681 default:
682 return RCODE_ADDRESS_ERROR;
683 }
684 }
685
686 static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store,
687 u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl)
688 {
689 int csraddr = addr - CSR_REGISTER_BASE;
690 unsigned long flags;
691
692 data = be64_to_cpu(data);
693 arg = be64_to_cpu(arg);
694
695 if (csraddr & 0x3)
696 return RCODE_TYPE_ERROR;
697
698 if (csraddr != CSR_CHANNELS_AVAILABLE
699 || extcode != EXTCODE_COMPARE_SWAP)
700 goto unsupported_lock64req;
701
702 /* Is somebody releasing the broadcast_channel on us? */
703 if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x100000000ULL)) {
704 /* Note: this is may not be the right way to handle
705 * the problem, so we should look into the proper way
706 * eventually. */
707 HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release "
708 "broadcast channel 31. Ignoring.",
709 NODE_BUS_ARGS(host, nodeid));
710
711 data &= ~0x100000000ULL; /* keep broadcast channel allocated */
712 }
713
714 if (host->driver->hw_csr_reg) {
715 quadlet_t data_hi, data_lo;
716 quadlet_t arg_hi, arg_lo;
717 quadlet_t old_hi, old_lo;
718
719 data_hi = data >> 32;
720 data_lo = data & 0xFFFFFFFF;
721 arg_hi = arg >> 32;
722 arg_lo = arg & 0xFFFFFFFF;
723
724 old_hi = host->driver->hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2,
725 data_hi, arg_hi);
726
727 old_lo = host->driver->hw_csr_reg(host, ((csraddr + 4) - CSR_BUS_MANAGER_ID) >> 2,
728 data_lo, arg_lo);
729
730 *store = cpu_to_be64(((octlet_t)old_hi << 32) | old_lo);
731 } else {
732 octlet_t old;
733 octlet_t affected_channels = arg ^ data;
734
735 spin_lock_irqsave(&host->csr.lock, flags);
736
737 old = ((octlet_t)host->csr.channels_available_hi << 32) | host->csr.channels_available_lo;
738
739 if ((arg & affected_channels) == (old & affected_channels)) {
740 host->csr.channels_available_hi ^= (affected_channels >> 32);
741 host->csr.channels_available_lo ^= (affected_channels & 0xffffffff);
742 *store = cpu_to_be64(arg);
743 } else {
744 *store = cpu_to_be64(old);
745 }
746
747 spin_unlock_irqrestore(&host->csr.lock, flags);
748 }
749
750 /* Is somebody erroneously releasing the broadcast_channel on us? */
751 if (host->csr.channels_available_hi & 0x1)
752 host->csr.channels_available_hi &= ~0x1;
753
754 return RCODE_COMPLETE;
755
756 unsupported_lock64req:
757 switch (csraddr) {
758 case CSR_STATE_CLEAR:
759 case CSR_STATE_SET:
760 case CSR_RESET_START:
761 case CSR_NODE_IDS:
762 case CSR_SPLIT_TIMEOUT_HI:
763 case CSR_SPLIT_TIMEOUT_LO:
764 case CSR_CYCLE_TIME:
765 case CSR_BUS_TIME:
766 case CSR_BUS_MANAGER_ID:
767 case CSR_BROADCAST_CHANNEL:
768 case CSR_BUSY_TIMEOUT:
769 case CSR_BANDWIDTH_AVAILABLE:
770 return RCODE_TYPE_ERROR;
771
772 default:
773 return RCODE_ADDRESS_ERROR;
774 }
775 }
776
777 static int write_fcp(struct hpsb_host *host, int nodeid, int dest,
778 quadlet_t *data, u64 addr, size_t length, u16 flags)
779 {
780 int csraddr = addr - CSR_REGISTER_BASE;
781
782 if (length > 512)
783 return RCODE_TYPE_ERROR;
784
785 switch (csraddr) {
786 case CSR_FCP_COMMAND:
787 highlevel_fcp_request(host, nodeid, 0, (u8 *)data, length);
788 break;
789 case CSR_FCP_RESPONSE:
790 highlevel_fcp_request(host, nodeid, 1, (u8 *)data, length);
791 break;
792 default:
793 return RCODE_TYPE_ERROR;
794 }
795
796 return RCODE_COMPLETE;
797 }
798
799 static int read_config_rom(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
800 u64 addr, size_t length, u16 fl)
801 {
802 u32 offset = addr - CSR1212_REGISTER_SPACE_BASE;
803
804 if (csr1212_read(host->csr.rom, offset, buffer, length) == CSR1212_SUCCESS)
805 return RCODE_COMPLETE;
806 else
807 return RCODE_ADDRESS_ERROR;
808 }
809
810 static u64 allocate_addr_range(u64 size, u32 alignment, void *__host)
811 {
812 struct hpsb_host *host = (struct hpsb_host*)__host;
813
814 return hpsb_allocate_and_register_addrspace(&csr_highlevel,
815 host,
816 &config_rom_ops,
817 size, alignment,
818 CSR1212_UNITS_SPACE_BASE,
819 CSR1212_UNITS_SPACE_END);
820 }
821
822 static void release_addr_range(u64 addr, void *__host)
823 {
824 struct hpsb_host *host = (struct hpsb_host*)__host;
825 hpsb_unregister_addrspace(&csr_highlevel, host, addr);
826 }
827
828
829 int init_csr(void)
830 {
831 node_cap = csr1212_new_immediate(CSR1212_KV_ID_NODE_CAPABILITIES, 0x0083c0);
832 if (!node_cap) {
833 HPSB_ERR("Failed to allocate memory for Node Capabilties ConfigROM entry!");
834 return -ENOMEM;
835 }
836
837 hpsb_register_highlevel(&csr_highlevel);
838
839 return 0;
840 }
841
842 void cleanup_csr(void)
843 {
844 if (node_cap)
845 csr1212_release_keyval(node_cap);
846 hpsb_unregister_highlevel(&csr_highlevel);
847 }
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