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Merge tag 'v2.6.16.6' of git://www.kernel.org/pub/scm/linux/kernel/git/stable/linux...
[linux-2.6/linux-mips.git] / drivers / scsi / sata_mv.c
blobb00af0884e1ef7cd87916a15c196c85413883562
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
37 #include <asm/io.h>
38
39 #define DRV_NAME "sata_mv"
40 #define DRV_VERSION "0.5"
41
42 enum {
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50
51 MV_PCI_REG_BASE = 0,
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
53 MV_SATAHC0_REG_BASE = 0x20000,
54 MV_FLASH_CTL = 0x1046c,
55 MV_GPIO_PORT_CTL = 0x104f0,
56 MV_RESET_CFG = 0x180d8,
57
58 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
59 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
60 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
61 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
62
63 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
64
65 MV_MAX_Q_DEPTH = 32,
66 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
67
68 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
69 * CRPB needs alignment on a 256B boundary. Size == 256B
70 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
71 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
72 */
73 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
74 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
75 MV_MAX_SG_CT = 176,
76 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
77 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
78
79 MV_PORTS_PER_HC = 4,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 MV_PORT_HC_SHIFT = 2,
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
83 MV_PORT_MASK = 3,
84
85 /* Host Flags */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
88 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
89 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
90 ATA_FLAG_NO_ATAPI),
91 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
92
93 CRQB_FLAG_READ = (1 << 0),
94 CRQB_TAG_SHIFT = 1,
95 CRQB_CMD_ADDR_SHIFT = 8,
96 CRQB_CMD_CS = (0x2 << 11),
97 CRQB_CMD_LAST = (1 << 15),
98
99 CRPB_FLAG_STATUS_SHIFT = 8,
100
101 EPRD_FLAG_END_OF_TBL = (1 << 31),
102
103 /* PCI interface registers */
104
105 PCI_COMMAND_OFS = 0xc00,
106
107 PCI_MAIN_CMD_STS_OFS = 0xd30,
108 STOP_PCI_MASTER = (1 << 2),
109 PCI_MASTER_EMPTY = (1 << 3),
110 GLOB_SFT_RST = (1 << 4),
111
112 MV_PCI_MODE = 0xd00,
113 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
114 MV_PCI_DISC_TIMER = 0xd04,
115 MV_PCI_MSI_TRIGGER = 0xc38,
116 MV_PCI_SERR_MASK = 0xc28,
117 MV_PCI_XBAR_TMOUT = 0x1d04,
118 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
119 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
120 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
121 MV_PCI_ERR_COMMAND = 0x1d50,
122
123 PCI_IRQ_CAUSE_OFS = 0x1d58,
124 PCI_IRQ_MASK_OFS = 0x1d5c,
125 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
126
127 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
128 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
129 PORT0_ERR = (1 << 0), /* shift by port # */
130 PORT0_DONE = (1 << 1), /* shift by port # */
131 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
132 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
133 PCI_ERR = (1 << 18),
134 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
135 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
136 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
137 GPIO_INT = (1 << 22),
138 SELF_INT = (1 << 23),
139 TWSI_INT = (1 << 24),
140 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
141 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
142 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
143 HC_MAIN_RSVD),
144
145 /* SATAHC registers */
146 HC_CFG_OFS = 0,
147
148 HC_IRQ_CAUSE_OFS = 0x14,
149 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
150 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
151 DEV_IRQ = (1 << 8), /* shift by port # */
152
153 /* Shadow block registers */
154 SHD_BLK_OFS = 0x100,
155 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
156
157 /* SATA registers */
158 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
159 SATA_ACTIVE_OFS = 0x350,
160 PHY_MODE3 = 0x310,
161 PHY_MODE4 = 0x314,
162 PHY_MODE2 = 0x330,
163 MV5_PHY_MODE = 0x74,
164 MV5_LT_MODE = 0x30,
165 MV5_PHY_CTL = 0x0C,
166 SATA_INTERFACE_CTL = 0x050,
167
168 MV_M2_PREAMP_MASK = 0x7e0,
169
170 /* Port registers */
171 EDMA_CFG_OFS = 0,
172 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
173 EDMA_CFG_NCQ = (1 << 5),
174 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
175 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
176 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
177
178 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
179 EDMA_ERR_IRQ_MASK_OFS = 0xc,
180 EDMA_ERR_D_PAR = (1 << 0),
181 EDMA_ERR_PRD_PAR = (1 << 1),
182 EDMA_ERR_DEV = (1 << 2),
183 EDMA_ERR_DEV_DCON = (1 << 3),
184 EDMA_ERR_DEV_CON = (1 << 4),
185 EDMA_ERR_SERR = (1 << 5),
186 EDMA_ERR_SELF_DIS = (1 << 7),
187 EDMA_ERR_BIST_ASYNC = (1 << 8),
188 EDMA_ERR_CRBQ_PAR = (1 << 9),
189 EDMA_ERR_CRPB_PAR = (1 << 10),
190 EDMA_ERR_INTRL_PAR = (1 << 11),
191 EDMA_ERR_IORDY = (1 << 12),
192 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
193 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
194 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
195 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
196 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
197 EDMA_ERR_TRANS_PROTO = (1 << 31),
198 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
199 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
200 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
201 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
202 EDMA_ERR_LNK_DATA_RX |
203 EDMA_ERR_LNK_DATA_TX |
204 EDMA_ERR_TRANS_PROTO),
205
206 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
207 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
208
209 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
210 EDMA_REQ_Q_PTR_SHIFT = 5,
211
212 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
213 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
214 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
215 EDMA_RSP_Q_PTR_SHIFT = 3,
216
217 EDMA_CMD_OFS = 0x28,
218 EDMA_EN = (1 << 0),
219 EDMA_DS = (1 << 1),
220 ATA_RST = (1 << 2),
221
222 EDMA_IORDY_TMOUT = 0x34,
223 EDMA_ARB_CFG = 0x38,
224
225 /* Host private flags (hp_flags) */
226 MV_HP_FLAG_MSI = (1 << 0),
227 MV_HP_ERRATA_50XXB0 = (1 << 1),
228 MV_HP_ERRATA_50XXB2 = (1 << 2),
229 MV_HP_ERRATA_60X1B2 = (1 << 3),
230 MV_HP_ERRATA_60X1C0 = (1 << 4),
231 MV_HP_50XX = (1 << 5),
232
233 /* Port private flags (pp_flags) */
234 MV_PP_FLAG_EDMA_EN = (1 << 0),
235 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
236 };
237
238 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
239 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
240
241 enum {
242 /* Our DMA boundary is determined by an ePRD being unable to handle
243 * anything larger than 64KB
244 */
245 MV_DMA_BOUNDARY = 0xffffU,
246
247 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
248
249 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
250 };
251
252 enum chip_type {
253 chip_504x,
254 chip_508x,
255 chip_5080,
256 chip_604x,
257 chip_608x,
258 };
259
260 /* Command ReQuest Block: 32B */
261 struct mv_crqb {
262 u32 sg_addr;
263 u32 sg_addr_hi;
264 u16 ctrl_flags;
265 u16 ata_cmd[11];
266 };
267
268 /* Command ResPonse Block: 8B */
269 struct mv_crpb {
270 u16 id;
271 u16 flags;
272 u32 tmstmp;
273 };
274
275 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
276 struct mv_sg {
277 u32 addr;
278 u32 flags_size;
279 u32 addr_hi;
280 u32 reserved;
281 };
282
283 struct mv_port_priv {
284 struct mv_crqb *crqb;
285 dma_addr_t crqb_dma;
286 struct mv_crpb *crpb;
287 dma_addr_t crpb_dma;
288 struct mv_sg *sg_tbl;
289 dma_addr_t sg_tbl_dma;
290
291 unsigned req_producer; /* cp of req_in_ptr */
292 unsigned rsp_consumer; /* cp of rsp_out_ptr */
293 u32 pp_flags;
294 };
295
296 struct mv_port_signal {
297 u32 amps;
298 u32 pre;
299 };
300
301 struct mv_host_priv;
302 struct mv_hw_ops {
303 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
304 unsigned int port);
305 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
306 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
307 void __iomem *mmio);
308 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
309 unsigned int n_hc);
310 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
311 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
312 };
313
314 struct mv_host_priv {
315 u32 hp_flags;
316 struct mv_port_signal signal[8];
317 const struct mv_hw_ops *ops;
318 };
319
320 static void mv_irq_clear(struct ata_port *ap);
321 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
322 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
323 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
324 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
325 static void mv_phy_reset(struct ata_port *ap);
326 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
327 static void mv_host_stop(struct ata_host_set *host_set);
328 static int mv_port_start(struct ata_port *ap);
329 static void mv_port_stop(struct ata_port *ap);
330 static void mv_qc_prep(struct ata_queued_cmd *qc);
331 static int mv_qc_issue(struct ata_queued_cmd *qc);
332 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
333 struct pt_regs *regs);
334 static void mv_eng_timeout(struct ata_port *ap);
335 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
336
337 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
338 unsigned int port);
339 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
340 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
341 void __iomem *mmio);
342 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
343 unsigned int n_hc);
344 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
345 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
346
347 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
348 unsigned int port);
349 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
350 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
351 void __iomem *mmio);
352 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
353 unsigned int n_hc);
354 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
355 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
356 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
357 unsigned int port_no);
358 static void mv_stop_and_reset(struct ata_port *ap);
359
360 static struct scsi_host_template mv_sht = {
361 .module = THIS_MODULE,
362 .name = DRV_NAME,
363 .ioctl = ata_scsi_ioctl,
364 .queuecommand = ata_scsi_queuecmd,
365 .eh_strategy_handler = ata_scsi_error,
366 .can_queue = MV_USE_Q_DEPTH,
367 .this_id = ATA_SHT_THIS_ID,
368 .sg_tablesize = MV_MAX_SG_CT / 2,
369 .max_sectors = ATA_MAX_SECTORS,
370 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
371 .emulated = ATA_SHT_EMULATED,
372 .use_clustering = ATA_SHT_USE_CLUSTERING,
373 .proc_name = DRV_NAME,
374 .dma_boundary = MV_DMA_BOUNDARY,
375 .slave_configure = ata_scsi_slave_config,
376 .bios_param = ata_std_bios_param,
377 };
378
379 static const struct ata_port_operations mv5_ops = {
380 .port_disable = ata_port_disable,
381
382 .tf_load = ata_tf_load,
383 .tf_read = ata_tf_read,
384 .check_status = ata_check_status,
385 .exec_command = ata_exec_command,
386 .dev_select = ata_std_dev_select,
387
388 .phy_reset = mv_phy_reset,
389
390 .qc_prep = mv_qc_prep,
391 .qc_issue = mv_qc_issue,
392
393 .eng_timeout = mv_eng_timeout,
394
395 .irq_handler = mv_interrupt,
396 .irq_clear = mv_irq_clear,
397
398 .scr_read = mv5_scr_read,
399 .scr_write = mv5_scr_write,
400
401 .port_start = mv_port_start,
402 .port_stop = mv_port_stop,
403 .host_stop = mv_host_stop,
404 };
405
406 static const struct ata_port_operations mv6_ops = {
407 .port_disable = ata_port_disable,
408
409 .tf_load = ata_tf_load,
410 .tf_read = ata_tf_read,
411 .check_status = ata_check_status,
412 .exec_command = ata_exec_command,
413 .dev_select = ata_std_dev_select,
414
415 .phy_reset = mv_phy_reset,
416
417 .qc_prep = mv_qc_prep,
418 .qc_issue = mv_qc_issue,
419
420 .eng_timeout = mv_eng_timeout,
421
422 .irq_handler = mv_interrupt,
423 .irq_clear = mv_irq_clear,
424
425 .scr_read = mv_scr_read,
426 .scr_write = mv_scr_write,
427
428 .port_start = mv_port_start,
429 .port_stop = mv_port_stop,
430 .host_stop = mv_host_stop,
431 };
432
433 static const struct ata_port_info mv_port_info[] = {
434 { /* chip_504x */
435 .sht = &mv_sht,
436 .host_flags = MV_COMMON_FLAGS,
437 .pio_mask = 0x1f, /* pio0-4 */
438 .udma_mask = 0x7f, /* udma0-6 */
439 .port_ops = &mv5_ops,
440 },
441 { /* chip_508x */
442 .sht = &mv_sht,
443 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
444 .pio_mask = 0x1f, /* pio0-4 */
445 .udma_mask = 0x7f, /* udma0-6 */
446 .port_ops = &mv5_ops,
447 },
448 { /* chip_5080 */
449 .sht = &mv_sht,
450 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
451 .pio_mask = 0x1f, /* pio0-4 */
452 .udma_mask = 0x7f, /* udma0-6 */
453 .port_ops = &mv5_ops,
454 },
455 { /* chip_604x */
456 .sht = &mv_sht,
457 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
458 .pio_mask = 0x1f, /* pio0-4 */
459 .udma_mask = 0x7f, /* udma0-6 */
460 .port_ops = &mv6_ops,
461 },
462 { /* chip_608x */
463 .sht = &mv_sht,
464 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
465 MV_FLAG_DUAL_HC),
466 .pio_mask = 0x1f, /* pio0-4 */
467 .udma_mask = 0x7f, /* udma0-6 */
468 .port_ops = &mv6_ops,
469 },
470 };
471
472 static const struct pci_device_id mv_pci_tbl[] = {
473 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
474 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
475 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
476 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
477
478 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
479 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
480 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
481 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
482
483 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
484 {} /* terminate list */
485 };
486
487 static struct pci_driver mv_pci_driver = {
488 .name = DRV_NAME,
489 .id_table = mv_pci_tbl,
490 .probe = mv_init_one,
491 .remove = ata_pci_remove_one,
492 };
493
494 static const struct mv_hw_ops mv5xxx_ops = {
495 .phy_errata = mv5_phy_errata,
496 .enable_leds = mv5_enable_leds,
497 .read_preamp = mv5_read_preamp,
498 .reset_hc = mv5_reset_hc,
499 .reset_flash = mv5_reset_flash,
500 .reset_bus = mv5_reset_bus,
501 };
502
503 static const struct mv_hw_ops mv6xxx_ops = {
504 .phy_errata = mv6_phy_errata,
505 .enable_leds = mv6_enable_leds,
506 .read_preamp = mv6_read_preamp,
507 .reset_hc = mv6_reset_hc,
508 .reset_flash = mv6_reset_flash,
509 .reset_bus = mv_reset_pci_bus,
510 };
511
512 /*
513 * module options
514 */
515 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
516
517
518 /*
519 * Functions
520 */
521
522 static inline void writelfl(unsigned long data, void __iomem *addr)
523 {
524 writel(data, addr);
525 (void) readl(addr); /* flush to avoid PCI posted write */
526 }
527
528 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
529 {
530 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
531 }
532
533 static inline unsigned int mv_hc_from_port(unsigned int port)
534 {
535 return port >> MV_PORT_HC_SHIFT;
536 }
537
538 static inline unsigned int mv_hardport_from_port(unsigned int port)
539 {
540 return port & MV_PORT_MASK;
541 }
542
543 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
544 unsigned int port)
545 {
546 return mv_hc_base(base, mv_hc_from_port(port));
547 }
548
549 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
550 {
551 return mv_hc_base_from_port(base, port) +
552 MV_SATAHC_ARBTR_REG_SZ +
553 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
554 }
555
556 static inline void __iomem *mv_ap_base(struct ata_port *ap)
557 {
558 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
559 }
560
561 static inline int mv_get_hc_count(unsigned long host_flags)
562 {
563 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
564 }
565
566 static void mv_irq_clear(struct ata_port *ap)
567 {
568 }
569
570 /**
571 * mv_start_dma - Enable eDMA engine
572 * @base: port base address
573 * @pp: port private data
574 *
575 * Verify the local cache of the eDMA state is accurate with an
576 * assert.
577 *
578 * LOCKING:
579 * Inherited from caller.
580 */
581 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
582 {
583 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
584 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
585 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
586 }
587 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
588 }
589
590 /**
591 * mv_stop_dma - Disable eDMA engine
592 * @ap: ATA channel to manipulate
593 *
594 * Verify the local cache of the eDMA state is accurate with an
595 * assert.
596 *
597 * LOCKING:
598 * Inherited from caller.
599 */
600 static void mv_stop_dma(struct ata_port *ap)
601 {
602 void __iomem *port_mmio = mv_ap_base(ap);
603 struct mv_port_priv *pp = ap->private_data;
604 u32 reg;
605 int i;
606
607 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
608 /* Disable EDMA if active. The disable bit auto clears.
609 */
610 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
611 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
612 } else {
613 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
614 }
615
616 /* now properly wait for the eDMA to stop */
617 for (i = 1000; i > 0; i--) {
618 reg = readl(port_mmio + EDMA_CMD_OFS);
619 if (!(EDMA_EN & reg)) {
620 break;
621 }
622 udelay(100);
623 }
624
625 if (EDMA_EN & reg) {
626 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
627 /* FIXME: Consider doing a reset here to recover */
628 }
629 }
630
631 #ifdef ATA_DEBUG
632 static void mv_dump_mem(void __iomem *start, unsigned bytes)
633 {
634 int b, w;
635 for (b = 0; b < bytes; ) {
636 DPRINTK("%p: ", start + b);
637 for (w = 0; b < bytes && w < 4; w++) {
638 printk("%08x ",readl(start + b));
639 b += sizeof(u32);
640 }
641 printk("\n");
642 }
643 }
644 #endif
645
646 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
647 {
648 #ifdef ATA_DEBUG
649 int b, w;
650 u32 dw;
651 for (b = 0; b < bytes; ) {
652 DPRINTK("%02x: ", b);
653 for (w = 0; b < bytes && w < 4; w++) {
654 (void) pci_read_config_dword(pdev,b,&dw);
655 printk("%08x ",dw);
656 b += sizeof(u32);
657 }
658 printk("\n");
659 }
660 #endif
661 }
662 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
663 struct pci_dev *pdev)
664 {
665 #ifdef ATA_DEBUG
666 void __iomem *hc_base = mv_hc_base(mmio_base,
667 port >> MV_PORT_HC_SHIFT);
668 void __iomem *port_base;
669 int start_port, num_ports, p, start_hc, num_hcs, hc;
670
671 if (0 > port) {
672 start_hc = start_port = 0;
673 num_ports = 8; /* shld be benign for 4 port devs */
674 num_hcs = 2;
675 } else {
676 start_hc = port >> MV_PORT_HC_SHIFT;
677 start_port = port;
678 num_ports = num_hcs = 1;
679 }
680 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
681 num_ports > 1 ? num_ports - 1 : start_port);
682
683 if (NULL != pdev) {
684 DPRINTK("PCI config space regs:\n");
685 mv_dump_pci_cfg(pdev, 0x68);
686 }
687 DPRINTK("PCI regs:\n");
688 mv_dump_mem(mmio_base+0xc00, 0x3c);
689 mv_dump_mem(mmio_base+0xd00, 0x34);
690 mv_dump_mem(mmio_base+0xf00, 0x4);
691 mv_dump_mem(mmio_base+0x1d00, 0x6c);
692 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
693 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
694 DPRINTK("HC regs (HC %i):\n", hc);
695 mv_dump_mem(hc_base, 0x1c);
696 }
697 for (p = start_port; p < start_port + num_ports; p++) {
698 port_base = mv_port_base(mmio_base, p);
699 DPRINTK("EDMA regs (port %i):\n",p);
700 mv_dump_mem(port_base, 0x54);
701 DPRINTK("SATA regs (port %i):\n",p);
702 mv_dump_mem(port_base+0x300, 0x60);
703 }
704 #endif
705 }
706
707 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
708 {
709 unsigned int ofs;
710
711 switch (sc_reg_in) {
712 case SCR_STATUS:
713 case SCR_CONTROL:
714 case SCR_ERROR:
715 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
716 break;
717 case SCR_ACTIVE:
718 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
719 break;
720 default:
721 ofs = 0xffffffffU;
722 break;
723 }
724 return ofs;
725 }
726
727 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
728 {
729 unsigned int ofs = mv_scr_offset(sc_reg_in);
730
731 if (0xffffffffU != ofs) {
732 return readl(mv_ap_base(ap) + ofs);
733 } else {
734 return (u32) ofs;
735 }
736 }
737
738 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
739 {
740 unsigned int ofs = mv_scr_offset(sc_reg_in);
741
742 if (0xffffffffU != ofs) {
743 writelfl(val, mv_ap_base(ap) + ofs);
744 }
745 }
746
747 /**
748 * mv_host_stop - Host specific cleanup/stop routine.
749 * @host_set: host data structure
750 *
751 * Disable ints, cleanup host memory, call general purpose
752 * host_stop.
753 *
754 * LOCKING:
755 * Inherited from caller.
756 */
757 static void mv_host_stop(struct ata_host_set *host_set)
758 {
759 struct mv_host_priv *hpriv = host_set->private_data;
760 struct pci_dev *pdev = to_pci_dev(host_set->dev);
761
762 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
763 pci_disable_msi(pdev);
764 } else {
765 pci_intx(pdev, 0);
766 }
767 kfree(hpriv);
768 ata_host_stop(host_set);
769 }
770
771 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
772 {
773 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
774 }
775
776 /**
777 * mv_port_start - Port specific init/start routine.
778 * @ap: ATA channel to manipulate
779 *
780 * Allocate and point to DMA memory, init port private memory,
781 * zero indices.
782 *
783 * LOCKING:
784 * Inherited from caller.
785 */
786 static int mv_port_start(struct ata_port *ap)
787 {
788 struct device *dev = ap->host_set->dev;
789 struct mv_port_priv *pp;
790 void __iomem *port_mmio = mv_ap_base(ap);
791 void *mem;
792 dma_addr_t mem_dma;
793 int rc = -ENOMEM;
794
795 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
796 if (!pp)
797 goto err_out;
798 memset(pp, 0, sizeof(*pp));
799
800 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
801 GFP_KERNEL);
802 if (!mem)
803 goto err_out_pp;
804 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
805
806 rc = ata_pad_alloc(ap, dev);
807 if (rc)
808 goto err_out_priv;
809
810 /* First item in chunk of DMA memory:
811 * 32-slot command request table (CRQB), 32 bytes each in size
812 */
813 pp->crqb = mem;
814 pp->crqb_dma = mem_dma;
815 mem += MV_CRQB_Q_SZ;
816 mem_dma += MV_CRQB_Q_SZ;
817
818 /* Second item:
819 * 32-slot command response table (CRPB), 8 bytes each in size
820 */
821 pp->crpb = mem;
822 pp->crpb_dma = mem_dma;
823 mem += MV_CRPB_Q_SZ;
824 mem_dma += MV_CRPB_Q_SZ;
825
826 /* Third item:
827 * Table of scatter-gather descriptors (ePRD), 16 bytes each
828 */
829 pp->sg_tbl = mem;
830 pp->sg_tbl_dma = mem_dma;
831
832 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
833 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
834
835 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
836 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
837 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
838
839 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
840 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
841
842 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
843 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
844 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
845
846 pp->req_producer = pp->rsp_consumer = 0;
847
848 /* Don't turn on EDMA here...do it before DMA commands only. Else
849 * we'll be unable to send non-data, PIO, etc due to restricted access
850 * to shadow regs.
851 */
852 ap->private_data = pp;
853 return 0;
854
855 err_out_priv:
856 mv_priv_free(pp, dev);
857 err_out_pp:
858 kfree(pp);
859 err_out:
860 return rc;
861 }
862
863 /**
864 * mv_port_stop - Port specific cleanup/stop routine.
865 * @ap: ATA channel to manipulate
866 *
867 * Stop DMA, cleanup port memory.
868 *
869 * LOCKING:
870 * This routine uses the host_set lock to protect the DMA stop.
871 */
872 static void mv_port_stop(struct ata_port *ap)
873 {
874 struct device *dev = ap->host_set->dev;
875 struct mv_port_priv *pp = ap->private_data;
876 unsigned long flags;
877
878 spin_lock_irqsave(&ap->host_set->lock, flags);
879 mv_stop_dma(ap);
880 spin_unlock_irqrestore(&ap->host_set->lock, flags);
881
882 ap->private_data = NULL;
883 ata_pad_free(ap, dev);
884 mv_priv_free(pp, dev);
885 kfree(pp);
886 }
887
888 /**
889 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
890 * @qc: queued command whose SG list to source from
891 *
892 * Populate the SG list and mark the last entry.
893 *
894 * LOCKING:
895 * Inherited from caller.
896 */
897 static void mv_fill_sg(struct ata_queued_cmd *qc)
898 {
899 struct mv_port_priv *pp = qc->ap->private_data;
900 unsigned int i = 0;
901 struct scatterlist *sg;
902
903 ata_for_each_sg(sg, qc) {
904 dma_addr_t addr;
905 u32 sg_len, len, offset;
906
907 addr = sg_dma_address(sg);
908 sg_len = sg_dma_len(sg);
909
910 while (sg_len) {
911 offset = addr & MV_DMA_BOUNDARY;
912 len = sg_len;
913 if ((offset + sg_len) > 0x10000)
914 len = 0x10000 - offset;
915
916 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
917 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
918 pp->sg_tbl[i].flags_size = cpu_to_le32(len);
919
920 sg_len -= len;
921 addr += len;
922
923 if (!sg_len && ata_sg_is_last(sg, qc))
924 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
925
926 i++;
927 }
928 }
929 }
930
931 static inline unsigned mv_inc_q_index(unsigned *index)
932 {
933 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
934 return *index;
935 }
936
937 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
938 {
939 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
940 (last ? CRQB_CMD_LAST : 0);
941 }
942
943 /**
944 * mv_qc_prep - Host specific command preparation.
945 * @qc: queued command to prepare
946 *
947 * This routine simply redirects to the general purpose routine
948 * if command is not DMA. Else, it handles prep of the CRQB
949 * (command request block), does some sanity checking, and calls
950 * the SG load routine.
951 *
952 * LOCKING:
953 * Inherited from caller.
954 */
955 static void mv_qc_prep(struct ata_queued_cmd *qc)
956 {
957 struct ata_port *ap = qc->ap;
958 struct mv_port_priv *pp = ap->private_data;
959 u16 *cw;
960 struct ata_taskfile *tf;
961 u16 flags = 0;
962
963 if (ATA_PROT_DMA != qc->tf.protocol) {
964 return;
965 }
966
967 /* the req producer index should be the same as we remember it */
968 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
969 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
970 pp->req_producer);
971
972 /* Fill in command request block
973 */
974 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
975 flags |= CRQB_FLAG_READ;
976 }
977 assert(MV_MAX_Q_DEPTH > qc->tag);
978 flags |= qc->tag << CRQB_TAG_SHIFT;
979
980 pp->crqb[pp->req_producer].sg_addr =
981 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
982 pp->crqb[pp->req_producer].sg_addr_hi =
983 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
984 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
985
986 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
987 tf = &qc->tf;
988
989 /* Sadly, the CRQB cannot accomodate all registers--there are
990 * only 11 bytes...so we must pick and choose required
991 * registers based on the command. So, we drop feature and
992 * hob_feature for [RW] DMA commands, but they are needed for
993 * NCQ. NCQ will drop hob_nsect.
994 */
995 switch (tf->command) {
996 case ATA_CMD_READ:
997 case ATA_CMD_READ_EXT:
998 case ATA_CMD_WRITE:
999 case ATA_CMD_WRITE_EXT:
1000 case ATA_CMD_WRITE_FUA_EXT:
1001 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1002 break;
1003 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1004 case ATA_CMD_FPDMA_READ:
1005 case ATA_CMD_FPDMA_WRITE:
1006 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1007 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1008 break;
1009 #endif /* FIXME: remove this line when NCQ added */
1010 default:
1011 /* The only other commands EDMA supports in non-queued and
1012 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1013 * of which are defined/used by Linux. If we get here, this
1014 * driver needs work.
1015 *
1016 * FIXME: modify libata to give qc_prep a return value and
1017 * return error here.
1018 */
1019 BUG_ON(tf->command);
1020 break;
1021 }
1022 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1023 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1024 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1025 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1026 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1027 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1028 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1029 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1030 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1031
1032 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
1033 return;
1034 }
1035 mv_fill_sg(qc);
1036 }
1037
1038 /**
1039 * mv_qc_issue - Initiate a command to the host
1040 * @qc: queued command to start
1041 *
1042 * This routine simply redirects to the general purpose routine
1043 * if command is not DMA. Else, it sanity checks our local
1044 * caches of the request producer/consumer indices then enables
1045 * DMA and bumps the request producer index.
1046 *
1047 * LOCKING:
1048 * Inherited from caller.
1049 */
1050 static int mv_qc_issue(struct ata_queued_cmd *qc)
1051 {
1052 void __iomem *port_mmio = mv_ap_base(qc->ap);
1053 struct mv_port_priv *pp = qc->ap->private_data;
1054 u32 in_ptr;
1055
1056 if (ATA_PROT_DMA != qc->tf.protocol) {
1057 /* We're about to send a non-EDMA capable command to the
1058 * port. Turn off EDMA so there won't be problems accessing
1059 * shadow block, etc registers.
1060 */
1061 mv_stop_dma(qc->ap);
1062 return ata_qc_issue_prot(qc);
1063 }
1064
1065 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1066
1067 /* the req producer index should be the same as we remember it */
1068 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1069 pp->req_producer);
1070 /* until we do queuing, the queue should be empty at this point */
1071 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1072 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
1073 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1074
1075 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
1076
1077 mv_start_dma(port_mmio, pp);
1078
1079 /* and write the request in pointer to kick the EDMA to life */
1080 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1081 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
1082 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1083
1084 return 0;
1085 }
1086
1087 /**
1088 * mv_get_crpb_status - get status from most recently completed cmd
1089 * @ap: ATA channel to manipulate
1090 *
1091 * This routine is for use when the port is in DMA mode, when it
1092 * will be using the CRPB (command response block) method of
1093 * returning command completion information. We assert indices
1094 * are good, grab status, and bump the response consumer index to
1095 * prove that we're up to date.
1096 *
1097 * LOCKING:
1098 * Inherited from caller.
1099 */
1100 static u8 mv_get_crpb_status(struct ata_port *ap)
1101 {
1102 void __iomem *port_mmio = mv_ap_base(ap);
1103 struct mv_port_priv *pp = ap->private_data;
1104 u32 out_ptr;
1105 u8 ata_status;
1106
1107 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1108
1109 /* the response consumer index should be the same as we remember it */
1110 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1111 pp->rsp_consumer);
1112
1113 ata_status = pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT;
1114
1115 /* increment our consumer index... */
1116 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1117
1118 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1119 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1120 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1121 pp->rsp_consumer);
1122
1123 /* write out our inc'd consumer index so EDMA knows we're caught up */
1124 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1125 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
1126 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1127
1128 /* Return ATA status register for completed CRPB */
1129 return ata_status;
1130 }
1131
1132 /**
1133 * mv_err_intr - Handle error interrupts on the port
1134 * @ap: ATA channel to manipulate
1135 *
1136 * In most cases, just clear the interrupt and move on. However,
1137 * some cases require an eDMA reset, which is done right before
1138 * the COMRESET in mv_phy_reset(). The SERR case requires a
1139 * clear of pending errors in the SATA SERROR register. Finally,
1140 * if the port disabled DMA, update our cached copy to match.
1141 *
1142 * LOCKING:
1143 * Inherited from caller.
1144 */
1145 static void mv_err_intr(struct ata_port *ap)
1146 {
1147 void __iomem *port_mmio = mv_ap_base(ap);
1148 u32 edma_err_cause, serr = 0;
1149
1150 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1151
1152 if (EDMA_ERR_SERR & edma_err_cause) {
1153 serr = scr_read(ap, SCR_ERROR);
1154 scr_write_flush(ap, SCR_ERROR, serr);
1155 }
1156 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1157 struct mv_port_priv *pp = ap->private_data;
1158 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1159 }
1160 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1161 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1162
1163 /* Clear EDMA now that SERR cleanup done */
1164 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1165
1166 /* check for fatal here and recover if needed */
1167 if (EDMA_ERR_FATAL & edma_err_cause) {
1168 mv_stop_and_reset(ap);
1169 }
1170 }
1171
1172 /**
1173 * mv_host_intr - Handle all interrupts on the given host controller
1174 * @host_set: host specific structure
1175 * @relevant: port error bits relevant to this host controller
1176 * @hc: which host controller we're to look at
1177 *
1178 * Read then write clear the HC interrupt status then walk each
1179 * port connected to the HC and see if it needs servicing. Port
1180 * success ints are reported in the HC interrupt status reg, the
1181 * port error ints are reported in the higher level main
1182 * interrupt status register and thus are passed in via the
1183 * 'relevant' argument.
1184 *
1185 * LOCKING:
1186 * Inherited from caller.
1187 */
1188 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1189 unsigned int hc)
1190 {
1191 void __iomem *mmio = host_set->mmio_base;
1192 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1193 struct ata_port *ap;
1194 struct ata_queued_cmd *qc;
1195 u32 hc_irq_cause;
1196 int shift, port, port0, hard_port, handled;
1197 unsigned int err_mask;
1198
1199 if (hc == 0) {
1200 port0 = 0;
1201 } else {
1202 port0 = MV_PORTS_PER_HC;
1203 }
1204
1205 /* we'll need the HC success int register in most cases */
1206 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1207 if (hc_irq_cause) {
1208 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1209 }
1210
1211 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1212 hc,relevant,hc_irq_cause);
1213
1214 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1215 u8 ata_status = 0;
1216 ap = host_set->ports[port];
1217 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1218 handled = 0; /* ensure ata_status is set if handled++ */
1219
1220 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1221 /* new CRPB on the queue; just one at a time until NCQ
1222 */
1223 ata_status = mv_get_crpb_status(ap);
1224 handled++;
1225 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1226 /* received ATA IRQ; read the status reg to clear INTRQ
1227 */
1228 ata_status = readb((void __iomem *)
1229 ap->ioaddr.status_addr);
1230 handled++;
1231 }
1232
1233 if (ap &&
1234 (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))
1235 continue;
1236
1237 err_mask = ac_err_mask(ata_status);
1238
1239 shift = port << 1; /* (port * 2) */
1240 if (port >= MV_PORTS_PER_HC) {
1241 shift++; /* skip bit 8 in the HC Main IRQ reg */
1242 }
1243 if ((PORT0_ERR << shift) & relevant) {
1244 mv_err_intr(ap);
1245 err_mask |= AC_ERR_OTHER;
1246 handled++;
1247 }
1248
1249 if (handled && ap) {
1250 qc = ata_qc_from_tag(ap, ap->active_tag);
1251 if (NULL != qc) {
1252 VPRINTK("port %u IRQ found for qc, "
1253 "ata_status 0x%x\n", port,ata_status);
1254 /* mark qc status appropriately */
1255 if (!(qc->tf.ctl & ATA_NIEN)) {
1256 qc->err_mask |= err_mask;
1257 ata_qc_complete(qc);
1258 }
1259 }
1260 }
1261 }
1262 VPRINTK("EXIT\n");
1263 }
1264
1265 /**
1266 * mv_interrupt -
1267 * @irq: unused
1268 * @dev_instance: private data; in this case the host structure
1269 * @regs: unused
1270 *
1271 * Read the read only register to determine if any host
1272 * controllers have pending interrupts. If so, call lower level
1273 * routine to handle. Also check for PCI errors which are only
1274 * reported here.
1275 *
1276 * LOCKING:
1277 * This routine holds the host_set lock while processing pending
1278 * interrupts.
1279 */
1280 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1281 struct pt_regs *regs)
1282 {
1283 struct ata_host_set *host_set = dev_instance;
1284 unsigned int hc, handled = 0, n_hcs;
1285 void __iomem *mmio = host_set->mmio_base;
1286 u32 irq_stat;
1287
1288 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1289
1290 /* check the cases where we either have nothing pending or have read
1291 * a bogus register value which can indicate HW removal or PCI fault
1292 */
1293 if (!irq_stat || (0xffffffffU == irq_stat)) {
1294 return IRQ_NONE;
1295 }
1296
1297 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1298 spin_lock(&host_set->lock);
1299
1300 for (hc = 0; hc < n_hcs; hc++) {
1301 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1302 if (relevant) {
1303 mv_host_intr(host_set, relevant, hc);
1304 handled++;
1305 }
1306 }
1307 if (PCI_ERR & irq_stat) {
1308 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1309 readl(mmio + PCI_IRQ_CAUSE_OFS));
1310
1311 DPRINTK("All regs @ PCI error\n");
1312 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1313
1314 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1315 handled++;
1316 }
1317 spin_unlock(&host_set->lock);
1318
1319 return IRQ_RETVAL(handled);
1320 }
1321
1322 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1323 {
1324 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1325 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1326
1327 return hc_mmio + ofs;
1328 }
1329
1330 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1331 {
1332 unsigned int ofs;
1333
1334 switch (sc_reg_in) {
1335 case SCR_STATUS:
1336 case SCR_ERROR:
1337 case SCR_CONTROL:
1338 ofs = sc_reg_in * sizeof(u32);
1339 break;
1340 default:
1341 ofs = 0xffffffffU;
1342 break;
1343 }
1344 return ofs;
1345 }
1346
1347 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1348 {
1349 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1350 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1351
1352 if (ofs != 0xffffffffU)
1353 return readl(mmio + ofs);
1354 else
1355 return (u32) ofs;
1356 }
1357
1358 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1359 {
1360 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1361 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1362
1363 if (ofs != 0xffffffffU)
1364 writelfl(val, mmio + ofs);
1365 }
1366
1367 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1368 {
1369 u8 rev_id;
1370 int early_5080;
1371
1372 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1373
1374 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1375
1376 if (!early_5080) {
1377 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1378 tmp |= (1 << 0);
1379 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1380 }
1381
1382 mv_reset_pci_bus(pdev, mmio);
1383 }
1384
1385 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1386 {
1387 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1388 }
1389
1390 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1391 void __iomem *mmio)
1392 {
1393 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1394 u32 tmp;
1395
1396 tmp = readl(phy_mmio + MV5_PHY_MODE);
1397
1398 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1399 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1400 }
1401
1402 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1403 {
1404 u32 tmp;
1405
1406 writel(0, mmio + MV_GPIO_PORT_CTL);
1407
1408 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1409
1410 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1411 tmp |= ~(1 << 0);
1412 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1413 }
1414
1415 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1416 unsigned int port)
1417 {
1418 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1419 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1420 u32 tmp;
1421 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1422
1423 if (fix_apm_sq) {
1424 tmp = readl(phy_mmio + MV5_LT_MODE);
1425 tmp |= (1 << 19);
1426 writel(tmp, phy_mmio + MV5_LT_MODE);
1427
1428 tmp = readl(phy_mmio + MV5_PHY_CTL);
1429 tmp &= ~0x3;
1430 tmp |= 0x1;
1431 writel(tmp, phy_mmio + MV5_PHY_CTL);
1432 }
1433
1434 tmp = readl(phy_mmio + MV5_PHY_MODE);
1435 tmp &= ~mask;
1436 tmp |= hpriv->signal[port].pre;
1437 tmp |= hpriv->signal[port].amps;
1438 writel(tmp, phy_mmio + MV5_PHY_MODE);
1439 }
1440
1441
1442 #undef ZERO
1443 #define ZERO(reg) writel(0, port_mmio + (reg))
1444 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1445 unsigned int port)
1446 {
1447 void __iomem *port_mmio = mv_port_base(mmio, port);
1448
1449 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1450
1451 mv_channel_reset(hpriv, mmio, port);
1452
1453 ZERO(0x028); /* command */
1454 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1455 ZERO(0x004); /* timer */
1456 ZERO(0x008); /* irq err cause */
1457 ZERO(0x00c); /* irq err mask */
1458 ZERO(0x010); /* rq bah */
1459 ZERO(0x014); /* rq inp */
1460 ZERO(0x018); /* rq outp */
1461 ZERO(0x01c); /* respq bah */
1462 ZERO(0x024); /* respq outp */
1463 ZERO(0x020); /* respq inp */
1464 ZERO(0x02c); /* test control */
1465 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1466 }
1467 #undef ZERO
1468
1469 #define ZERO(reg) writel(0, hc_mmio + (reg))
1470 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1471 unsigned int hc)
1472 {
1473 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1474 u32 tmp;
1475
1476 ZERO(0x00c);
1477 ZERO(0x010);
1478 ZERO(0x014);
1479 ZERO(0x018);
1480
1481 tmp = readl(hc_mmio + 0x20);
1482 tmp &= 0x1c1c1c1c;
1483 tmp |= 0x03030303;
1484 writel(tmp, hc_mmio + 0x20);
1485 }
1486 #undef ZERO
1487
1488 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1489 unsigned int n_hc)
1490 {
1491 unsigned int hc, port;
1492
1493 for (hc = 0; hc < n_hc; hc++) {
1494 for (port = 0; port < MV_PORTS_PER_HC; port++)
1495 mv5_reset_hc_port(hpriv, mmio,
1496 (hc * MV_PORTS_PER_HC) + port);
1497
1498 mv5_reset_one_hc(hpriv, mmio, hc);
1499 }
1500
1501 return 0;
1502 }
1503
1504 #undef ZERO
1505 #define ZERO(reg) writel(0, mmio + (reg))
1506 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1507 {
1508 u32 tmp;
1509
1510 tmp = readl(mmio + MV_PCI_MODE);
1511 tmp &= 0xff00ffff;
1512 writel(tmp, mmio + MV_PCI_MODE);
1513
1514 ZERO(MV_PCI_DISC_TIMER);
1515 ZERO(MV_PCI_MSI_TRIGGER);
1516 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1517 ZERO(HC_MAIN_IRQ_MASK_OFS);
1518 ZERO(MV_PCI_SERR_MASK);
1519 ZERO(PCI_IRQ_CAUSE_OFS);
1520 ZERO(PCI_IRQ_MASK_OFS);
1521 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1522 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1523 ZERO(MV_PCI_ERR_ATTRIBUTE);
1524 ZERO(MV_PCI_ERR_COMMAND);
1525 }
1526 #undef ZERO
1527
1528 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1529 {
1530 u32 tmp;
1531
1532 mv5_reset_flash(hpriv, mmio);
1533
1534 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1535 tmp &= 0x3;
1536 tmp |= (1 << 5) | (1 << 6);
1537 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1538 }
1539
1540 /**
1541 * mv6_reset_hc - Perform the 6xxx global soft reset
1542 * @mmio: base address of the HBA
1543 *
1544 * This routine only applies to 6xxx parts.
1545 *
1546 * LOCKING:
1547 * Inherited from caller.
1548 */
1549 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1550 unsigned int n_hc)
1551 {
1552 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1553 int i, rc = 0;
1554 u32 t;
1555
1556 /* Following procedure defined in PCI "main command and status
1557 * register" table.
1558 */
1559 t = readl(reg);
1560 writel(t | STOP_PCI_MASTER, reg);
1561
1562 for (i = 0; i < 1000; i++) {
1563 udelay(1);
1564 t = readl(reg);
1565 if (PCI_MASTER_EMPTY & t) {
1566 break;
1567 }
1568 }
1569 if (!(PCI_MASTER_EMPTY & t)) {
1570 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1571 rc = 1;
1572 goto done;
1573 }
1574
1575 /* set reset */
1576 i = 5;
1577 do {
1578 writel(t | GLOB_SFT_RST, reg);
1579 t = readl(reg);
1580 udelay(1);
1581 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1582
1583 if (!(GLOB_SFT_RST & t)) {
1584 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1585 rc = 1;
1586 goto done;
1587 }
1588
1589 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1590 i = 5;
1591 do {
1592 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1593 t = readl(reg);
1594 udelay(1);
1595 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1596
1597 if (GLOB_SFT_RST & t) {
1598 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1599 rc = 1;
1600 }
1601 done:
1602 return rc;
1603 }
1604
1605 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1606 void __iomem *mmio)
1607 {
1608 void __iomem *port_mmio;
1609 u32 tmp;
1610
1611 tmp = readl(mmio + MV_RESET_CFG);
1612 if ((tmp & (1 << 0)) == 0) {
1613 hpriv->signal[idx].amps = 0x7 << 8;
1614 hpriv->signal[idx].pre = 0x1 << 5;
1615 return;
1616 }
1617
1618 port_mmio = mv_port_base(mmio, idx);
1619 tmp = readl(port_mmio + PHY_MODE2);
1620
1621 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1622 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1623 }
1624
1625 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1626 {
1627 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1628 }
1629
1630 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1631 unsigned int port)
1632 {
1633 void __iomem *port_mmio = mv_port_base(mmio, port);
1634
1635 u32 hp_flags = hpriv->hp_flags;
1636 int fix_phy_mode2 =
1637 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1638 int fix_phy_mode4 =
1639 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1640 u32 m2, tmp;
1641
1642 if (fix_phy_mode2) {
1643 m2 = readl(port_mmio + PHY_MODE2);
1644 m2 &= ~(1 << 16);
1645 m2 |= (1 << 31);
1646 writel(m2, port_mmio + PHY_MODE2);
1647
1648 udelay(200);
1649
1650 m2 = readl(port_mmio + PHY_MODE2);
1651 m2 &= ~((1 << 16) | (1 << 31));
1652 writel(m2, port_mmio + PHY_MODE2);
1653
1654 udelay(200);
1655 }
1656
1657 /* who knows what this magic does */
1658 tmp = readl(port_mmio + PHY_MODE3);
1659 tmp &= ~0x7F800000;
1660 tmp |= 0x2A800000;
1661 writel(tmp, port_mmio + PHY_MODE3);
1662
1663 if (fix_phy_mode4) {
1664 u32 m4;
1665
1666 m4 = readl(port_mmio + PHY_MODE4);
1667
1668 if (hp_flags & MV_HP_ERRATA_60X1B2)
1669 tmp = readl(port_mmio + 0x310);
1670
1671 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1672
1673 writel(m4, port_mmio + PHY_MODE4);
1674
1675 if (hp_flags & MV_HP_ERRATA_60X1B2)
1676 writel(tmp, port_mmio + 0x310);
1677 }
1678
1679 /* Revert values of pre-emphasis and signal amps to the saved ones */
1680 m2 = readl(port_mmio + PHY_MODE2);
1681
1682 m2 &= ~MV_M2_PREAMP_MASK;
1683 m2 |= hpriv->signal[port].amps;
1684 m2 |= hpriv->signal[port].pre;
1685 m2 &= ~(1 << 16);
1686
1687 writel(m2, port_mmio + PHY_MODE2);
1688 }
1689
1690 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1691 unsigned int port_no)
1692 {
1693 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1694
1695 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1696
1697 if (IS_60XX(hpriv)) {
1698 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1699 ifctl |= (1 << 12) | (1 << 7);
1700 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1701 }
1702
1703 udelay(25); /* allow reset propagation */
1704
1705 /* Spec never mentions clearing the bit. Marvell's driver does
1706 * clear the bit, however.
1707 */
1708 writelfl(0, port_mmio + EDMA_CMD_OFS);
1709
1710 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1711
1712 if (IS_50XX(hpriv))
1713 mdelay(1);
1714 }
1715
1716 static void mv_stop_and_reset(struct ata_port *ap)
1717 {
1718 struct mv_host_priv *hpriv = ap->host_set->private_data;
1719 void __iomem *mmio = ap->host_set->mmio_base;
1720
1721 mv_stop_dma(ap);
1722
1723 mv_channel_reset(hpriv, mmio, ap->port_no);
1724
1725 __mv_phy_reset(ap, 0);
1726 }
1727
1728 static inline void __msleep(unsigned int msec, int can_sleep)
1729 {
1730 if (can_sleep)
1731 msleep(msec);
1732 else
1733 mdelay(msec);
1734 }
1735
1736 /**
1737 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1738 * @ap: ATA channel to manipulate
1739 *
1740 * Part of this is taken from __sata_phy_reset and modified to
1741 * not sleep since this routine gets called from interrupt level.
1742 *
1743 * LOCKING:
1744 * Inherited from caller. This is coded to safe to call at
1745 * interrupt level, i.e. it does not sleep.
1746 */
1747 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1748 {
1749 struct mv_port_priv *pp = ap->private_data;
1750 struct mv_host_priv *hpriv = ap->host_set->private_data;
1751 void __iomem *port_mmio = mv_ap_base(ap);
1752 struct ata_taskfile tf;
1753 struct ata_device *dev = &ap->device[0];
1754 unsigned long timeout;
1755 int retry = 5;
1756 u32 sstatus;
1757
1758 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1759
1760 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1761 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1762 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1763
1764 /* Issue COMRESET via SControl */
1765 comreset_retry:
1766 scr_write_flush(ap, SCR_CONTROL, 0x301);
1767 __msleep(1, can_sleep);
1768
1769 scr_write_flush(ap, SCR_CONTROL, 0x300);
1770 __msleep(20, can_sleep);
1771
1772 timeout = jiffies + msecs_to_jiffies(200);
1773 do {
1774 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1775 if ((sstatus == 3) || (sstatus == 0))
1776 break;
1777
1778 __msleep(1, can_sleep);
1779 } while (time_before(jiffies, timeout));
1780
1781 /* work around errata */
1782 if (IS_60XX(hpriv) &&
1783 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1784 (retry-- > 0))
1785 goto comreset_retry;
1786
1787 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1788 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1789 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1790
1791 if (sata_dev_present(ap)) {
1792 ata_port_probe(ap);
1793 } else {
1794 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1795 ap->id, scr_read(ap, SCR_STATUS));
1796 ata_port_disable(ap);
1797 return;
1798 }
1799 ap->cbl = ATA_CBL_SATA;
1800
1801 /* even after SStatus reflects that device is ready,
1802 * it seems to take a while for link to be fully
1803 * established (and thus Status no longer 0x80/0x7F),
1804 * so we poll a bit for that, here.
1805 */
1806 retry = 20;
1807 while (1) {
1808 u8 drv_stat = ata_check_status(ap);
1809 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1810 break;
1811 __msleep(500, can_sleep);
1812 if (retry-- <= 0)
1813 break;
1814 }
1815
1816 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1817 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1818 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1819 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1820
1821 dev->class = ata_dev_classify(&tf);
1822 if (!ata_dev_present(dev)) {
1823 VPRINTK("Port disabled post-sig: No device present.\n");
1824 ata_port_disable(ap);
1825 }
1826
1827 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1828
1829 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1830
1831 VPRINTK("EXIT\n");
1832 }
1833
1834 static void mv_phy_reset(struct ata_port *ap)
1835 {
1836 __mv_phy_reset(ap, 1);
1837 }
1838
1839 /**
1840 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1841 * @ap: ATA channel to manipulate
1842 *
1843 * Intent is to clear all pending error conditions, reset the
1844 * chip/bus, fail the command, and move on.
1845 *
1846 * LOCKING:
1847 * This routine holds the host_set lock while failing the command.
1848 */
1849 static void mv_eng_timeout(struct ata_port *ap)
1850 {
1851 struct ata_queued_cmd *qc;
1852 unsigned long flags;
1853
1854 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1855 DPRINTK("All regs @ start of eng_timeout\n");
1856 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1857 to_pci_dev(ap->host_set->dev));
1858
1859 qc = ata_qc_from_tag(ap, ap->active_tag);
1860 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1861 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1862 &qc->scsicmd->cmnd);
1863
1864 mv_err_intr(ap);
1865 mv_stop_and_reset(ap);
1866
1867 if (!qc) {
1868 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1869 ap->id);
1870 } else {
1871 /* hack alert! We cannot use the supplied completion
1872 * function from inside the ->eh_strategy_handler() thread.
1873 * libata is the only user of ->eh_strategy_handler() in
1874 * any kernel, so the default scsi_done() assumes it is
1875 * not being called from the SCSI EH.
1876 */
1877 spin_lock_irqsave(&ap->host_set->lock, flags);
1878 qc->scsidone = scsi_finish_command;
1879 qc->err_mask |= AC_ERR_OTHER;
1880 ata_qc_complete(qc);
1881 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1882 }
1883 }
1884
1885 /**
1886 * mv_port_init - Perform some early initialization on a single port.
1887 * @port: libata data structure storing shadow register addresses
1888 * @port_mmio: base address of the port
1889 *
1890 * Initialize shadow register mmio addresses, clear outstanding
1891 * interrupts on the port, and unmask interrupts for the future
1892 * start of the port.
1893 *
1894 * LOCKING:
1895 * Inherited from caller.
1896 */
1897 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1898 {
1899 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1900 unsigned serr_ofs;
1901
1902 /* PIO related setup
1903 */
1904 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1905 port->error_addr =
1906 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1907 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1908 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1909 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1910 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1911 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1912 port->status_addr =
1913 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1914 /* special case: control/altstatus doesn't have ATA_REG_ address */
1915 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1916
1917 /* unused: */
1918 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1919
1920 /* Clear any currently outstanding port interrupt conditions */
1921 serr_ofs = mv_scr_offset(SCR_ERROR);
1922 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1923 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1924
1925 /* unmask all EDMA error interrupts */
1926 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1927
1928 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1929 readl(port_mmio + EDMA_CFG_OFS),
1930 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1931 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1932 }
1933
1934 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
1935 unsigned int board_idx)
1936 {
1937 u8 rev_id;
1938 u32 hp_flags = hpriv->hp_flags;
1939
1940 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1941
1942 switch(board_idx) {
1943 case chip_5080:
1944 hpriv->ops = &mv5xxx_ops;
1945 hp_flags |= MV_HP_50XX;
1946
1947 switch (rev_id) {
1948 case 0x1:
1949 hp_flags |= MV_HP_ERRATA_50XXB0;
1950 break;
1951 case 0x3:
1952 hp_flags |= MV_HP_ERRATA_50XXB2;
1953 break;
1954 default:
1955 dev_printk(KERN_WARNING, &pdev->dev,
1956 "Applying 50XXB2 workarounds to unknown rev\n");
1957 hp_flags |= MV_HP_ERRATA_50XXB2;
1958 break;
1959 }
1960 break;
1961
1962 case chip_504x:
1963 case chip_508x:
1964 hpriv->ops = &mv5xxx_ops;
1965 hp_flags |= MV_HP_50XX;
1966
1967 switch (rev_id) {
1968 case 0x0:
1969 hp_flags |= MV_HP_ERRATA_50XXB0;
1970 break;
1971 case 0x3:
1972 hp_flags |= MV_HP_ERRATA_50XXB2;
1973 break;
1974 default:
1975 dev_printk(KERN_WARNING, &pdev->dev,
1976 "Applying B2 workarounds to unknown rev\n");
1977 hp_flags |= MV_HP_ERRATA_50XXB2;
1978 break;
1979 }
1980 break;
1981
1982 case chip_604x:
1983 case chip_608x:
1984 hpriv->ops = &mv6xxx_ops;
1985
1986 switch (rev_id) {
1987 case 0x7:
1988 hp_flags |= MV_HP_ERRATA_60X1B2;
1989 break;
1990 case 0x9:
1991 hp_flags |= MV_HP_ERRATA_60X1C0;
1992 break;
1993 default:
1994 dev_printk(KERN_WARNING, &pdev->dev,
1995 "Applying B2 workarounds to unknown rev\n");
1996 hp_flags |= MV_HP_ERRATA_60X1B2;
1997 break;
1998 }
1999 break;
2000
2001 default:
2002 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2003 return 1;
2004 }
2005
2006 hpriv->hp_flags = hp_flags;
2007
2008 return 0;
2009 }
2010
2011 /**
2012 * mv_init_host - Perform some early initialization of the host.
2013 * @pdev: host PCI device
2014 * @probe_ent: early data struct representing the host
2015 *
2016 * If possible, do an early global reset of the host. Then do
2017 * our port init and clear/unmask all/relevant host interrupts.
2018 *
2019 * LOCKING:
2020 * Inherited from caller.
2021 */
2022 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2023 unsigned int board_idx)
2024 {
2025 int rc = 0, n_hc, port, hc;
2026 void __iomem *mmio = probe_ent->mmio_base;
2027 struct mv_host_priv *hpriv = probe_ent->private_data;
2028
2029 /* global interrupt mask */
2030 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2031
2032 rc = mv_chip_id(pdev, hpriv, board_idx);
2033 if (rc)
2034 goto done;
2035
2036 n_hc = mv_get_hc_count(probe_ent->host_flags);
2037 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2038
2039 for (port = 0; port < probe_ent->n_ports; port++)
2040 hpriv->ops->read_preamp(hpriv, port, mmio);
2041
2042 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2043 if (rc)
2044 goto done;
2045
2046 hpriv->ops->reset_flash(hpriv, mmio);
2047 hpriv->ops->reset_bus(pdev, mmio);
2048 hpriv->ops->enable_leds(hpriv, mmio);
2049
2050 for (port = 0; port < probe_ent->n_ports; port++) {
2051 if (IS_60XX(hpriv)) {
2052 void __iomem *port_mmio = mv_port_base(mmio, port);
2053
2054 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2055 ifctl |= (1 << 12);
2056 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2057 }
2058
2059 hpriv->ops->phy_errata(hpriv, mmio, port);
2060 }
2061
2062 for (port = 0; port < probe_ent->n_ports; port++) {
2063 void __iomem *port_mmio = mv_port_base(mmio, port);
2064 mv_port_init(&probe_ent->port[port], port_mmio);
2065 }
2066
2067 for (hc = 0; hc < n_hc; hc++) {
2068 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2069
2070 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2071 "(before clear)=0x%08x\n", hc,
2072 readl(hc_mmio + HC_CFG_OFS),
2073 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2074
2075 /* Clear any currently outstanding hc interrupt conditions */
2076 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2077 }
2078
2079 /* Clear any currently outstanding host interrupt conditions */
2080 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2081
2082 /* and unmask interrupt generation for host regs */
2083 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2084 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2085
2086 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2087 "PCI int cause/mask=0x%08x/0x%08x\n",
2088 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2089 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2090 readl(mmio + PCI_IRQ_CAUSE_OFS),
2091 readl(mmio + PCI_IRQ_MASK_OFS));
2092
2093 done:
2094 return rc;
2095 }
2096
2097 /**
2098 * mv_print_info - Dump key info to kernel log for perusal.
2099 * @probe_ent: early data struct representing the host
2100 *
2101 * FIXME: complete this.
2102 *
2103 * LOCKING:
2104 * Inherited from caller.
2105 */
2106 static void mv_print_info(struct ata_probe_ent *probe_ent)
2107 {
2108 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2109 struct mv_host_priv *hpriv = probe_ent->private_data;
2110 u8 rev_id, scc;
2111 const char *scc_s;
2112
2113 /* Use this to determine the HW stepping of the chip so we know
2114 * what errata to workaround
2115 */
2116 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2117
2118 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2119 if (scc == 0)
2120 scc_s = "SCSI";
2121 else if (scc == 0x01)
2122 scc_s = "RAID";
2123 else
2124 scc_s = "unknown";
2125
2126 dev_printk(KERN_INFO, &pdev->dev,
2127 "%u slots %u ports %s mode IRQ via %s\n",
2128 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2129 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2130 }
2131
2132 /**
2133 * mv_init_one - handle a positive probe of a Marvell host
2134 * @pdev: PCI device found
2135 * @ent: PCI device ID entry for the matched host
2136 *
2137 * LOCKING:
2138 * Inherited from caller.
2139 */
2140 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2141 {
2142 static int printed_version = 0;
2143 struct ata_probe_ent *probe_ent = NULL;
2144 struct mv_host_priv *hpriv;
2145 unsigned int board_idx = (unsigned int)ent->driver_data;
2146 void __iomem *mmio_base;
2147 int pci_dev_busy = 0, rc;
2148
2149 if (!printed_version++)
2150 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2151
2152 rc = pci_enable_device(pdev);
2153 if (rc) {
2154 return rc;
2155 }
2156
2157 rc = pci_request_regions(pdev, DRV_NAME);
2158 if (rc) {
2159 pci_dev_busy = 1;
2160 goto err_out;
2161 }
2162
2163 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2164 if (probe_ent == NULL) {
2165 rc = -ENOMEM;
2166 goto err_out_regions;
2167 }
2168
2169 memset(probe_ent, 0, sizeof(*probe_ent));
2170 probe_ent->dev = pci_dev_to_dev(pdev);
2171 INIT_LIST_HEAD(&probe_ent->node);
2172
2173 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2174 if (mmio_base == NULL) {
2175 rc = -ENOMEM;
2176 goto err_out_free_ent;
2177 }
2178
2179 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2180 if (!hpriv) {
2181 rc = -ENOMEM;
2182 goto err_out_iounmap;
2183 }
2184 memset(hpriv, 0, sizeof(*hpriv));
2185
2186 probe_ent->sht = mv_port_info[board_idx].sht;
2187 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2188 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2189 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2190 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2191
2192 probe_ent->irq = pdev->irq;
2193 probe_ent->irq_flags = SA_SHIRQ;
2194 probe_ent->mmio_base = mmio_base;
2195 probe_ent->private_data = hpriv;
2196
2197 /* initialize adapter */
2198 rc = mv_init_host(pdev, probe_ent, board_idx);
2199 if (rc) {
2200 goto err_out_hpriv;
2201 }
2202
2203 /* Enable interrupts */
2204 if (msi && pci_enable_msi(pdev) == 0) {
2205 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2206 } else {
2207 pci_intx(pdev, 1);
2208 }
2209
2210 mv_dump_pci_cfg(pdev, 0x68);
2211 mv_print_info(probe_ent);
2212
2213 if (ata_device_add(probe_ent) == 0) {
2214 rc = -ENODEV; /* No devices discovered */
2215 goto err_out_dev_add;
2216 }
2217
2218 kfree(probe_ent);
2219 return 0;
2220
2221 err_out_dev_add:
2222 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2223 pci_disable_msi(pdev);
2224 } else {
2225 pci_intx(pdev, 0);
2226 }
2227 err_out_hpriv:
2228 kfree(hpriv);
2229 err_out_iounmap:
2230 pci_iounmap(pdev, mmio_base);
2231 err_out_free_ent:
2232 kfree(probe_ent);
2233 err_out_regions:
2234 pci_release_regions(pdev);
2235 err_out:
2236 if (!pci_dev_busy) {
2237 pci_disable_device(pdev);
2238 }
2239
2240 return rc;
2241 }
2242
2243 static int __init mv_init(void)
2244 {
2245 return pci_module_init(&mv_pci_driver);
2246 }
2247
2248 static void __exit mv_exit(void)
2249 {
2250 pci_unregister_driver(&mv_pci_driver);
2251 }
2252
2253 MODULE_AUTHOR("Brett Russ");
2254 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2255 MODULE_LICENSE("GPL");
2256 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2257 MODULE_VERSION(DRV_VERSION);
2258
2259 module_param(msi, int, 0444);
2260 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2261
2262 module_init(mv_init);
2263 module_exit(mv_exit);
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