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[MIPS] Oprofile: Reset all performance registers for MIPS_MT_SMP configs
[linux-2.6/linux-mips.git] / drivers / net / chelsio / subr.c
blobc2522cdfab3759fbc3638d9a690062e53b288c42
1 /*****************************************************************************
2 * *
3 * File: subr.c *
4 * $Revision: 1.27 $ *
5 * $Date: 2005/06/22 01:08:36 $ *
6 * Description: *
7 * Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40 #include "common.h"
41 #include "elmer0.h"
42 #include "regs.h"
43 #include "gmac.h"
44 #include "cphy.h"
45 #include "sge.h"
46 #include "tp.h"
47 #include "espi.h"
48
49 /**
50 * t1_wait_op_done - wait until an operation is completed
51 * @adapter: the adapter performing the operation
52 * @reg: the register to check for completion
53 * @mask: a single-bit field within @reg that indicates completion
54 * @polarity: the value of the field when the operation is completed
55 * @attempts: number of check iterations
56 * @delay: delay in usecs between iterations
57 *
58 * Wait until an operation is completed by checking a bit in a register
59 * up to @attempts times. Returns %0 if the operation completes and %1
60 * otherwise.
61 */
62 static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
63 int attempts, int delay)
64 {
65 while (1) {
66 u32 val = readl(adapter->regs + reg) & mask;
67
68 if (!!val == polarity)
69 return 0;
70 if (--attempts == 0)
71 return 1;
72 if (delay)
73 udelay(delay);
74 }
75 }
76
77 #define TPI_ATTEMPTS 50
78
79 /*
80 * Write a register over the TPI interface (unlocked and locked versions).
81 */
82 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
83 {
84 int tpi_busy;
85
86 writel(addr, adapter->regs + A_TPI_ADDR);
87 writel(value, adapter->regs + A_TPI_WR_DATA);
88 writel(F_TPIWR, adapter->regs + A_TPI_CSR);
89
90 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
91 TPI_ATTEMPTS, 3);
92 if (tpi_busy)
93 CH_ALERT("%s: TPI write to 0x%x failed\n",
94 adapter->name, addr);
95 return tpi_busy;
96 }
97
98 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
99 {
100 int ret;
101
102 spin_lock(&adapter->tpi_lock);
103 ret = __t1_tpi_write(adapter, addr, value);
104 spin_unlock(&adapter->tpi_lock);
105 return ret;
106 }
107
108 /*
109 * Read a register over the TPI interface (unlocked and locked versions).
110 */
111 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
112 {
113 int tpi_busy;
114
115 writel(addr, adapter->regs + A_TPI_ADDR);
116 writel(0, adapter->regs + A_TPI_CSR);
117
118 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
119 TPI_ATTEMPTS, 3);
120 if (tpi_busy)
121 CH_ALERT("%s: TPI read from 0x%x failed\n",
122 adapter->name, addr);
123 else
124 *valp = readl(adapter->regs + A_TPI_RD_DATA);
125 return tpi_busy;
126 }
127
128 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
129 {
130 int ret;
131
132 spin_lock(&adapter->tpi_lock);
133 ret = __t1_tpi_read(adapter, addr, valp);
134 spin_unlock(&adapter->tpi_lock);
135 return ret;
136 }
137
138 /*
139 * Set a TPI parameter.
140 */
141 static void t1_tpi_par(adapter_t *adapter, u32 value)
142 {
143 writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
144 }
145
146 /*
147 * Called when a port's link settings change to propagate the new values to the
148 * associated PHY and MAC. After performing the common tasks it invokes an
149 * OS-specific handler.
150 */
151 void t1_link_changed(adapter_t *adapter, int port_id)
152 {
153 int link_ok, speed, duplex, fc;
154 struct cphy *phy = adapter->port[port_id].phy;
155 struct link_config *lc = &adapter->port[port_id].link_config;
156
157 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
158
159 lc->speed = speed < 0 ? SPEED_INVALID : speed;
160 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
161 if (!(lc->requested_fc & PAUSE_AUTONEG))
162 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
163
164 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
165 /* Set MAC speed, duplex, and flow control to match PHY. */
166 struct cmac *mac = adapter->port[port_id].mac;
167
168 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
169 lc->fc = (unsigned char)fc;
170 }
171 t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
172 }
173
174 static int t1_pci_intr_handler(adapter_t *adapter)
175 {
176 u32 pcix_cause;
177
178 pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
179
180 if (pcix_cause) {
181 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
182 pcix_cause);
183 t1_fatal_err(adapter); /* PCI errors are fatal */
184 }
185 return 0;
186 }
187
188 #ifdef CONFIG_CHELSIO_T1_COUGAR
189 #include "cspi.h"
190 #endif
191 #ifdef CONFIG_CHELSIO_T1_1G
192 #include "fpga_defs.h"
193
194 /*
195 * PHY interrupt handler for FPGA boards.
196 */
197 static int fpga_phy_intr_handler(adapter_t *adapter)
198 {
199 int p;
200 u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
201
202 for_each_port(adapter, p)
203 if (cause & (1 << p)) {
204 struct cphy *phy = adapter->port[p].phy;
205 int phy_cause = phy->ops->interrupt_handler(phy);
206
207 if (phy_cause & cphy_cause_link_change)
208 t1_link_changed(adapter, p);
209 }
210 writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
211 return 0;
212 }
213
214 /*
215 * Slow path interrupt handler for FPGAs.
216 */
217 static int fpga_slow_intr(adapter_t *adapter)
218 {
219 u32 cause = readl(adapter->regs + A_PL_CAUSE);
220
221 cause &= ~F_PL_INTR_SGE_DATA;
222 if (cause & F_PL_INTR_SGE_ERR)
223 t1_sge_intr_error_handler(adapter->sge);
224
225 if (cause & FPGA_PCIX_INTERRUPT_GMAC)
226 fpga_phy_intr_handler(adapter);
227
228 if (cause & FPGA_PCIX_INTERRUPT_TP) {
229 /*
230 * FPGA doesn't support MC4 interrupts and it requires
231 * this odd layer of indirection for MC5.
232 */
233 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
234
235 /* Clear TP interrupt */
236 writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
237 }
238 if (cause & FPGA_PCIX_INTERRUPT_PCIX)
239 t1_pci_intr_handler(adapter);
240
241 /* Clear the interrupts just processed. */
242 if (cause)
243 writel(cause, adapter->regs + A_PL_CAUSE);
244
245 return cause != 0;
246 }
247 #endif
248
249 /*
250 * Wait until Elmer's MI1 interface is ready for new operations.
251 */
252 static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
253 {
254 int attempts = 100, busy;
255
256 do {
257 u32 val;
258
259 __t1_tpi_read(adapter, mi1_reg, &val);
260 busy = val & F_MI1_OP_BUSY;
261 if (busy)
262 udelay(10);
263 } while (busy && --attempts);
264 if (busy)
265 CH_ALERT("%s: MDIO operation timed out\n", adapter->name);
266 return busy;
267 }
268
269 /*
270 * MI1 MDIO initialization.
271 */
272 static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
273 {
274 u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
275 u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
276 V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
277
278 if (!(bi->caps & SUPPORTED_10000baseT_Full))
279 val |= V_MI1_SOF(1);
280 t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
281 }
282
283 #if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
284 /*
285 * Elmer MI1 MDIO read/write operations.
286 */
287 static int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr,
288 int reg_addr, unsigned int *valp)
289 {
290 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
291
292 if (mmd_addr)
293 return -EINVAL;
294
295 spin_lock(&adapter->tpi_lock);
296 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
297 __t1_tpi_write(adapter,
298 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
299 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
300 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
301 spin_unlock(&adapter->tpi_lock);
302 return 0;
303 }
304
305 static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
306 int reg_addr, unsigned int val)
307 {
308 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
309
310 if (mmd_addr)
311 return -EINVAL;
312
313 spin_lock(&adapter->tpi_lock);
314 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
315 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
316 __t1_tpi_write(adapter,
317 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE);
318 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
319 spin_unlock(&adapter->tpi_lock);
320 return 0;
321 }
322
323 #if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
324 static struct mdio_ops mi1_mdio_ops = {
325 mi1_mdio_init,
326 mi1_mdio_read,
327 mi1_mdio_write
328 };
329 #endif
330
331 #endif
332
333 static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
334 int reg_addr, unsigned int *valp)
335 {
336 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
337
338 spin_lock(&adapter->tpi_lock);
339
340 /* Write the address we want. */
341 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
342 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
343 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
344 MI1_OP_INDIRECT_ADDRESS);
345 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
346
347 /* Write the operation we want. */
348 __t1_tpi_write(adapter,
349 A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
350 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
351
352 /* Read the data. */
353 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
354 spin_unlock(&adapter->tpi_lock);
355 return 0;
356 }
357
358 static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
359 int reg_addr, unsigned int val)
360 {
361 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
362
363 spin_lock(&adapter->tpi_lock);
364
365 /* Write the address we want. */
366 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
367 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
368 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
369 MI1_OP_INDIRECT_ADDRESS);
370 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
371
372 /* Write the data. */
373 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
374 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
375 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
376 spin_unlock(&adapter->tpi_lock);
377 return 0;
378 }
379
380 static struct mdio_ops mi1_mdio_ext_ops = {
381 mi1_mdio_init,
382 mi1_mdio_ext_read,
383 mi1_mdio_ext_write
384 };
385
386 enum {
387 CH_BRD_T110_1CU,
388 CH_BRD_N110_1F,
389 CH_BRD_N210_1F,
390 CH_BRD_T210_1F,
391 CH_BRD_T210_1CU,
392 CH_BRD_N204_4CU,
393 };
394
395 static struct board_info t1_board[] = {
396
397 { CHBT_BOARD_CHT110, 1/*ports#*/,
398 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T1,
399 CHBT_MAC_PM3393, CHBT_PHY_MY3126,
400 125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
401 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
402 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
403 &t1_my3126_ops, &mi1_mdio_ext_ops,
404 "Chelsio T110 1x10GBase-CX4 TOE" },
405
406 { CHBT_BOARD_N110, 1/*ports#*/,
407 SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
408 CHBT_MAC_PM3393, CHBT_PHY_88X2010,
409 125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
410 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
411 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
412 &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
413 "Chelsio N110 1x10GBaseX NIC" },
414
415 { CHBT_BOARD_N210, 1/*ports#*/,
416 SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T2,
417 CHBT_MAC_PM3393, CHBT_PHY_88X2010,
418 125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
419 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
420 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
421 &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
422 "Chelsio N210 1x10GBaseX NIC" },
423
424 { CHBT_BOARD_CHT210, 1/*ports#*/,
425 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
426 CHBT_MAC_PM3393, CHBT_PHY_88X2010,
427 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
428 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
429 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
430 &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
431 "Chelsio T210 1x10GBaseX TOE" },
432
433 { CHBT_BOARD_CHT210, 1/*ports#*/,
434 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
435 CHBT_MAC_PM3393, CHBT_PHY_MY3126,
436 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
437 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
438 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
439 &t1_my3126_ops, &mi1_mdio_ext_ops,
440 "Chelsio T210 1x10GBase-CX4 TOE" },
441
442 #ifdef CONFIG_CHELSIO_T1_1G
443 { CHBT_BOARD_CHN204, 4/*ports#*/,
444 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
445 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
446 SUPPORTED_PAUSE | SUPPORTED_TP /*caps*/, CHBT_TERM_T2, CHBT_MAC_VSC7321, CHBT_PHY_88E1111,
447 100000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
448 4/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
449 0/*mdiinv*/, 1/*mdc*/, 4/*phybaseaddr*/, &t1_vsc7326_ops,
450 &t1_mv88e1xxx_ops, &mi1_mdio_ops,
451 "Chelsio N204 4x100/1000BaseT NIC" },
452 #endif
453
454 };
455
456 struct pci_device_id t1_pci_tbl[] = {
457 CH_DEVICE(8, 0, CH_BRD_T110_1CU),
458 CH_DEVICE(8, 1, CH_BRD_T110_1CU),
459 CH_DEVICE(7, 0, CH_BRD_N110_1F),
460 CH_DEVICE(10, 1, CH_BRD_N210_1F),
461 CH_DEVICE(11, 1, CH_BRD_T210_1F),
462 CH_DEVICE(14, 1, CH_BRD_T210_1CU),
463 CH_DEVICE(16, 1, CH_BRD_N204_4CU),
464 { 0 }
465 };
466
467 MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
468
469 /*
470 * Return the board_info structure with a given index. Out-of-range indices
471 * return NULL.
472 */
473 const struct board_info *t1_get_board_info(unsigned int board_id)
474 {
475 return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
476 }
477
478 struct chelsio_vpd_t {
479 u32 format_version;
480 u8 serial_number[16];
481 u8 mac_base_address[6];
482 u8 pad[2]; /* make multiple-of-4 size requirement explicit */
483 };
484
485 #define EEPROMSIZE (8 * 1024)
486 #define EEPROM_MAX_POLL 4
487
488 /*
489 * Read SEEPROM. A zero is written to the flag register when the addres is
490 * written to the Control register. The hardware device will set the flag to a
491 * one when 4B have been transferred to the Data register.
492 */
493 int t1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data)
494 {
495 int i = EEPROM_MAX_POLL;
496 u16 val;
497
498 if (addr >= EEPROMSIZE || (addr & 3))
499 return -EINVAL;
500
501 pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
502 do {
503 udelay(50);
504 pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
505 } while (!(val & F_VPD_OP_FLAG) && --i);
506
507 if (!(val & F_VPD_OP_FLAG)) {
508 CH_ERR("%s: reading EEPROM address 0x%x failed\n",
509 adapter->name, addr);
510 return -EIO;
511 }
512 pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, data);
513 *data = le32_to_cpu(*data);
514 return 0;
515 }
516
517 static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
518 {
519 int addr, ret = 0;
520
521 for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
522 ret = t1_seeprom_read(adapter, addr,
523 (u32 *)((u8 *)vpd + addr));
524
525 return ret;
526 }
527
528 /*
529 * Read a port's MAC address from the VPD ROM.
530 */
531 static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
532 {
533 struct chelsio_vpd_t vpd;
534
535 if (t1_eeprom_vpd_get(adapter, &vpd))
536 return 1;
537 memcpy(mac_addr, vpd.mac_base_address, 5);
538 mac_addr[5] = vpd.mac_base_address[5] + index;
539 return 0;
540 }
541
542 /*
543 * Set up the MAC/PHY according to the requested link settings.
544 *
545 * If the PHY can auto-negotiate first decide what to advertise, then
546 * enable/disable auto-negotiation as desired and reset.
547 *
548 * If the PHY does not auto-negotiate we just reset it.
549 *
550 * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
551 * otherwise do it later based on the outcome of auto-negotiation.
552 */
553 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
554 {
555 unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
556
557 if (lc->supported & SUPPORTED_Autoneg) {
558 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
559 if (fc) {
560 if (fc == ((PAUSE_RX | PAUSE_TX) &
561 (mac->adapter->params.nports < 2)))
562 lc->advertising |= ADVERTISED_PAUSE;
563 else {
564 lc->advertising |= ADVERTISED_ASYM_PAUSE;
565 if (fc == PAUSE_RX)
566 lc->advertising |= ADVERTISED_PAUSE;
567 }
568 }
569 phy->ops->advertise(phy, lc->advertising);
570
571 if (lc->autoneg == AUTONEG_DISABLE) {
572 lc->speed = lc->requested_speed;
573 lc->duplex = lc->requested_duplex;
574 lc->fc = (unsigned char)fc;
575 mac->ops->set_speed_duplex_fc(mac, lc->speed,
576 lc->duplex, fc);
577 /* Also disables autoneg */
578 phy->state = PHY_AUTONEG_RDY;
579 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
580 phy->ops->reset(phy, 0);
581 } else {
582 phy->state = PHY_AUTONEG_EN;
583 phy->ops->autoneg_enable(phy); /* also resets PHY */
584 }
585 } else {
586 phy->state = PHY_AUTONEG_RDY;
587 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
588 lc->fc = (unsigned char)fc;
589 phy->ops->reset(phy, 0);
590 }
591 return 0;
592 }
593
594 /*
595 * External interrupt handler for boards using elmer0.
596 */
597 int t1_elmer0_ext_intr_handler(adapter_t *adapter)
598 {
599 struct cphy *phy;
600 int phy_cause;
601 u32 cause;
602
603 t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
604
605 switch (board_info(adapter)->board) {
606 #ifdef CONFIG_CHELSIO_T1_1G
607 case CHBT_BOARD_CHT204:
608 case CHBT_BOARD_CHT204E:
609 case CHBT_BOARD_CHN204:
610 case CHBT_BOARD_CHT204V: {
611 int i, port_bit;
612 for_each_port(adapter, i) {
613 port_bit = i + 1;
614 if (!(cause & (1 << port_bit)))
615 continue;
616
617 phy = adapter->port[i].phy;
618 phy_cause = phy->ops->interrupt_handler(phy);
619 if (phy_cause & cphy_cause_link_change)
620 t1_link_changed(adapter, i);
621 }
622 break;
623 }
624 case CHBT_BOARD_CHT101:
625 if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
626 phy = adapter->port[0].phy;
627 phy_cause = phy->ops->interrupt_handler(phy);
628 if (phy_cause & cphy_cause_link_change)
629 t1_link_changed(adapter, 0);
630 }
631 break;
632 case CHBT_BOARD_7500: {
633 int p;
634 /*
635 * Elmer0's interrupt cause isn't useful here because there is
636 * only one bit that can be set for all 4 ports. This means
637 * we are forced to check every PHY's interrupt status
638 * register to see who initiated the interrupt.
639 */
640 for_each_port(adapter, p) {
641 phy = adapter->port[p].phy;
642 phy_cause = phy->ops->interrupt_handler(phy);
643 if (phy_cause & cphy_cause_link_change)
644 t1_link_changed(adapter, p);
645 }
646 break;
647 }
648 #endif
649 case CHBT_BOARD_CHT210:
650 case CHBT_BOARD_N210:
651 case CHBT_BOARD_N110:
652 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
653 phy = adapter->port[0].phy;
654 phy_cause = phy->ops->interrupt_handler(phy);
655 if (phy_cause & cphy_cause_link_change)
656 t1_link_changed(adapter, 0);
657 }
658 break;
659 case CHBT_BOARD_8000:
660 case CHBT_BOARD_CHT110:
661 CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n",
662 cause);
663 if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */
664 struct cmac *mac = adapter->port[0].mac;
665
666 mac->ops->interrupt_handler(mac);
667 }
668 if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
669 u32 mod_detect;
670
671 t1_tpi_read(adapter,
672 A_ELMER0_GPI_STAT, &mod_detect);
673 CH_MSG(adapter, INFO, LINK, "XPAK %s\n",
674 mod_detect ? "removed" : "inserted");
675 }
676 break;
677 #ifdef CONFIG_CHELSIO_T1_COUGAR
678 case CHBT_BOARD_COUGAR:
679 if (adapter->params.nports == 1) {
680 if (cause & ELMER0_GP_BIT1) { /* Vitesse MAC */
681 struct cmac *mac = adapter->port[0].mac;
682 mac->ops->interrupt_handler(mac);
683 }
684 if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
685 }
686 } else {
687 int i, port_bit;
688
689 for_each_port(adapter, i) {
690 port_bit = i ? i + 1 : 0;
691 if (!(cause & (1 << port_bit)))
692 continue;
693
694 phy = adapter->port[i].phy;
695 phy_cause = phy->ops->interrupt_handler(phy);
696 if (phy_cause & cphy_cause_link_change)
697 t1_link_changed(adapter, i);
698 }
699 }
700 break;
701 #endif
702 }
703 t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
704 return 0;
705 }
706
707 /* Enables all interrupts. */
708 void t1_interrupts_enable(adapter_t *adapter)
709 {
710 unsigned int i;
711
712 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
713
714 t1_sge_intr_enable(adapter->sge);
715 t1_tp_intr_enable(adapter->tp);
716 if (adapter->espi) {
717 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
718 t1_espi_intr_enable(adapter->espi);
719 }
720
721 /* Enable MAC/PHY interrupts for each port. */
722 for_each_port(adapter, i) {
723 adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
724 adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
725 }
726
727 /* Enable PCIX & external chip interrupts on ASIC boards. */
728 if (t1_is_asic(adapter)) {
729 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
730
731 /* PCI-X interrupts */
732 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
733 0xffffffff);
734
735 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
736 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
737 writel(pl_intr, adapter->regs + A_PL_ENABLE);
738 }
739 }
740
741 /* Disables all interrupts. */
742 void t1_interrupts_disable(adapter_t* adapter)
743 {
744 unsigned int i;
745
746 t1_sge_intr_disable(adapter->sge);
747 t1_tp_intr_disable(adapter->tp);
748 if (adapter->espi)
749 t1_espi_intr_disable(adapter->espi);
750
751 /* Disable MAC/PHY interrupts for each port. */
752 for_each_port(adapter, i) {
753 adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
754 adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
755 }
756
757 /* Disable PCIX & external chip interrupts. */
758 if (t1_is_asic(adapter))
759 writel(0, adapter->regs + A_PL_ENABLE);
760
761 /* PCI-X interrupts */
762 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
763
764 adapter->slow_intr_mask = 0;
765 }
766
767 /* Clears all interrupts */
768 void t1_interrupts_clear(adapter_t* adapter)
769 {
770 unsigned int i;
771
772 t1_sge_intr_clear(adapter->sge);
773 t1_tp_intr_clear(adapter->tp);
774 if (adapter->espi)
775 t1_espi_intr_clear(adapter->espi);
776
777 /* Clear MAC/PHY interrupts for each port. */
778 for_each_port(adapter, i) {
779 adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
780 adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
781 }
782
783 /* Enable interrupts for external devices. */
784 if (t1_is_asic(adapter)) {
785 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
786
787 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
788 adapter->regs + A_PL_CAUSE);
789 }
790
791 /* PCI-X interrupts */
792 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
793 }
794
795 /*
796 * Slow path interrupt handler for ASICs.
797 */
798 static int asic_slow_intr(adapter_t *adapter)
799 {
800 u32 cause = readl(adapter->regs + A_PL_CAUSE);
801
802 cause &= adapter->slow_intr_mask;
803 if (!cause)
804 return 0;
805 if (cause & F_PL_INTR_SGE_ERR)
806 t1_sge_intr_error_handler(adapter->sge);
807 if (cause & F_PL_INTR_TP)
808 t1_tp_intr_handler(adapter->tp);
809 if (cause & F_PL_INTR_ESPI)
810 t1_espi_intr_handler(adapter->espi);
811 if (cause & F_PL_INTR_PCIX)
812 t1_pci_intr_handler(adapter);
813 if (cause & F_PL_INTR_EXT)
814 t1_elmer0_ext_intr_handler(adapter);
815
816 /* Clear the interrupts just processed. */
817 writel(cause, adapter->regs + A_PL_CAUSE);
818 readl(adapter->regs + A_PL_CAUSE); /* flush writes */
819 return 1;
820 }
821
822 int t1_slow_intr_handler(adapter_t *adapter)
823 {
824 #ifdef CONFIG_CHELSIO_T1_1G
825 if (!t1_is_asic(adapter))
826 return fpga_slow_intr(adapter);
827 #endif
828 return asic_slow_intr(adapter);
829 }
830
831 /* Power sequencing is a work-around for Intel's XPAKs. */
832 static void power_sequence_xpak(adapter_t* adapter)
833 {
834 u32 mod_detect;
835 u32 gpo;
836
837 /* Check for XPAK */
838 t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
839 if (!(ELMER0_GP_BIT5 & mod_detect)) {
840 /* XPAK is present */
841 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
842 gpo |= ELMER0_GP_BIT18;
843 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
844 }
845 }
846
847 int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
848 struct adapter_params *p)
849 {
850 p->chip_version = bi->chip_term;
851 p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
852 if (p->chip_version == CHBT_TERM_T1 ||
853 p->chip_version == CHBT_TERM_T2 ||
854 p->chip_version == CHBT_TERM_FPGA) {
855 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
856
857 val = G_TP_PC_REV(val);
858 if (val == 2)
859 p->chip_revision = TERM_T1B;
860 else if (val == 3)
861 p->chip_revision = TERM_T2;
862 else
863 return -1;
864 } else
865 return -1;
866 return 0;
867 }
868
869 /*
870 * Enable board components other than the Chelsio chip, such as external MAC
871 * and PHY.
872 */
873 static int board_init(adapter_t *adapter, const struct board_info *bi)
874 {
875 switch (bi->board) {
876 case CHBT_BOARD_8000:
877 case CHBT_BOARD_N110:
878 case CHBT_BOARD_N210:
879 case CHBT_BOARD_CHT210:
880 case CHBT_BOARD_COUGAR:
881 t1_tpi_par(adapter, 0xf);
882 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
883 break;
884 case CHBT_BOARD_CHT110:
885 t1_tpi_par(adapter, 0xf);
886 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
887
888 /* TBD XXX Might not need. This fixes a problem
889 * described in the Intel SR XPAK errata.
890 */
891 power_sequence_xpak(adapter);
892 break;
893 #ifdef CONFIG_CHELSIO_T1_1G
894 case CHBT_BOARD_CHT204E:
895 /* add config space write here */
896 case CHBT_BOARD_CHT204:
897 case CHBT_BOARD_CHT204V:
898 case CHBT_BOARD_CHN204:
899 t1_tpi_par(adapter, 0xf);
900 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
901 break;
902 case CHBT_BOARD_CHT101:
903 case CHBT_BOARD_7500:
904 t1_tpi_par(adapter, 0xf);
905 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
906 break;
907 #endif
908 }
909 return 0;
910 }
911
912 /*
913 * Initialize and configure the Terminator HW modules. Note that external
914 * MAC and PHYs are initialized separately.
915 */
916 int t1_init_hw_modules(adapter_t *adapter)
917 {
918 int err = -EIO;
919 const struct board_info *bi = board_info(adapter);
920
921 if (!bi->clock_mc4) {
922 u32 val = readl(adapter->regs + A_MC4_CFG);
923
924 writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
925 writel(F_M_BUS_ENABLE | F_TCAM_RESET,
926 adapter->regs + A_MC5_CONFIG);
927 }
928
929 #ifdef CONFIG_CHELSIO_T1_COUGAR
930 if (adapter->cspi && t1_cspi_init(adapter->cspi))
931 goto out_err;
932 #endif
933 if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
934 bi->espi_nports))
935 goto out_err;
936
937 if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
938 goto out_err;
939
940 err = t1_sge_configure(adapter->sge, &adapter->params.sge);
941 if (err)
942 goto out_err;
943
944 err = 0;
945 out_err:
946 return err;
947 }
948
949 /*
950 * Determine a card's PCI mode.
951 */
952 static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
953 {
954 static const unsigned short speed_map[] = { 33, 66, 100, 133 };
955 u32 pci_mode;
956
957 pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
958 p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
959 p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
960 p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
961 }
962
963 /*
964 * Release the structures holding the SW per-Terminator-HW-module state.
965 */
966 void t1_free_sw_modules(adapter_t *adapter)
967 {
968 unsigned int i;
969
970 for_each_port(adapter, i) {
971 struct cmac *mac = adapter->port[i].mac;
972 struct cphy *phy = adapter->port[i].phy;
973
974 if (mac)
975 mac->ops->destroy(mac);
976 if (phy)
977 phy->ops->destroy(phy);
978 }
979
980 if (adapter->sge)
981 t1_sge_destroy(adapter->sge);
982 if (adapter->tp)
983 t1_tp_destroy(adapter->tp);
984 if (adapter->espi)
985 t1_espi_destroy(adapter->espi);
986 #ifdef CONFIG_CHELSIO_T1_COUGAR
987 if (adapter->cspi)
988 t1_cspi_destroy(adapter->cspi);
989 #endif
990 }
991
992 static void __devinit init_link_config(struct link_config *lc,
993 const struct board_info *bi)
994 {
995 lc->supported = bi->caps;
996 lc->requested_speed = lc->speed = SPEED_INVALID;
997 lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
998 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
999 if (lc->supported & SUPPORTED_Autoneg) {
1000 lc->advertising = lc->supported;
1001 lc->autoneg = AUTONEG_ENABLE;
1002 lc->requested_fc |= PAUSE_AUTONEG;
1003 } else {
1004 lc->advertising = 0;
1005 lc->autoneg = AUTONEG_DISABLE;
1006 }
1007 }
1008
1009 #ifdef CONFIG_CHELSIO_T1_COUGAR
1010 if (bi->clock_cspi && !(adapter->cspi = t1_cspi_create(adapter))) {
1011 CH_ERR("%s: CSPI initialization failed\n",
1012 adapter->name);
1013 goto error;
1014 }
1015 #endif
1016
1017 /*
1018 * Allocate and initialize the data structures that hold the SW state of
1019 * the Terminator HW modules.
1020 */
1021 int __devinit t1_init_sw_modules(adapter_t *adapter,
1022 const struct board_info *bi)
1023 {
1024 unsigned int i;
1025
1026 adapter->params.brd_info = bi;
1027 adapter->params.nports = bi->port_number;
1028 adapter->params.stats_update_period = bi->gmac->stats_update_period;
1029
1030 adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
1031 if (!adapter->sge) {
1032 CH_ERR("%s: SGE initialization failed\n",
1033 adapter->name);
1034 goto error;
1035 }
1036
1037 if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
1038 CH_ERR("%s: ESPI initialization failed\n",
1039 adapter->name);
1040 goto error;
1041 }
1042
1043 adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1044 if (!adapter->tp) {
1045 CH_ERR("%s: TP initialization failed\n",
1046 adapter->name);
1047 goto error;
1048 }
1049
1050 board_init(adapter, bi);
1051 bi->mdio_ops->init(adapter, bi);
1052 if (bi->gphy->reset)
1053 bi->gphy->reset(adapter);
1054 if (bi->gmac->reset)
1055 bi->gmac->reset(adapter);
1056
1057 for_each_port(adapter, i) {
1058 u8 hw_addr[6];
1059 struct cmac *mac;
1060 int phy_addr = bi->mdio_phybaseaddr + i;
1061
1062 adapter->port[i].phy = bi->gphy->create(adapter, phy_addr,
1063 bi->mdio_ops);
1064 if (!adapter->port[i].phy) {
1065 CH_ERR("%s: PHY %d initialization failed\n",
1066 adapter->name, i);
1067 goto error;
1068 }
1069
1070 adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1071 if (!mac) {
1072 CH_ERR("%s: MAC %d initialization failed\n",
1073 adapter->name, i);
1074 goto error;
1075 }
1076
1077 /*
1078 * Get the port's MAC addresses either from the EEPROM if one
1079 * exists or the one hardcoded in the MAC.
1080 */
1081 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1082 mac->ops->macaddress_get(mac, hw_addr);
1083 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
1084 CH_ERR("%s: could not read MAC address from VPD ROM\n",
1085 adapter->port[i].dev->name);
1086 goto error;
1087 }
1088 memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
1089 init_link_config(&adapter->port[i].link_config, bi);
1090 }
1091
1092 get_pci_mode(adapter, &adapter->params.pci);
1093 t1_interrupts_clear(adapter);
1094 return 0;
1095
1096 error:
1097 t1_free_sw_modules(adapter);
1098 return -1;
1099 }
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