drivers/ide/icside.c

   1 /*
   2  * linux/drivers/block/icside.c
   3  *
   4  * Copyright (c) 1996,1997 Russell King.
   5  *
   6  * Changelog:
   7  *  08-Jun-1996 RMK     Created
   8  *  12-Sep-1997 RMK     Added interrupt enable/disable
   9  *  17-Apr-1999 RMK     Added support for V6 EASI
  10  *  22-May-1999 RMK     Added support for V6 DMA
  11  */
  12
  13 #include <linux/config.h>
  14 #include <linux/string.h>
  15 #include <linux/module.h>
  16 #include <linux/ioport.h>
  17 #include <linux/malloc.h>
  18 #include <linux/blkdev.h>
  19 #include <linux/errno.h>
  20 #include <linux/hdreg.h>
  21 #include <linux/ide.h>
  22
  23 #include <asm/dma.h>
  24 #include <asm/ecard.h>
  25 #include <asm/io.h>
  26
  27 extern char *ide_xfer_verbose (byte xfer_rate);
  28
  29 /*
  30  * Maximum number of interfaces per card
  31  */
  32 #define MAX_IFS 2
  33
  34 #define ICS_IDENT_OFFSET                0x8a0
  35
  36 #define ICS_ARCIN_V5_INTRSTAT           0x000
  37 #define ICS_ARCIN_V5_INTROFFSET         0x001
  38 #define ICS_ARCIN_V5_IDEOFFSET          0xa00
  39 #define ICS_ARCIN_V5_IDEALTOFFSET       0xae0
  40 #define ICS_ARCIN_V5_IDESTEPPING        4
  41
  42 #define ICS_ARCIN_V6_IDEOFFSET_1        0x800
  43 #define ICS_ARCIN_V6_INTROFFSET_1       0x880
  44 #define ICS_ARCIN_V6_INTRSTAT_1         0x8a4
  45 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x8e0
  46 #define ICS_ARCIN_V6_IDEOFFSET_2        0xc00
  47 #define ICS_ARCIN_V6_INTROFFSET_2       0xc80
  48 #define ICS_ARCIN_V6_INTRSTAT_2         0xca4
  49 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0xce0
  50 #define ICS_ARCIN_V6_IDESTEPPING        4
  51
  52 struct cardinfo {
  53         unsigned int dataoffset;
  54         unsigned int ctrloffset;
  55         unsigned int stepping;
  56 };
  57
  58 static struct cardinfo icside_cardinfo_v5 = {
  59         ICS_ARCIN_V5_IDEOFFSET,
  60         ICS_ARCIN_V5_IDEALTOFFSET,
  61         ICS_ARCIN_V5_IDESTEPPING
  62 };
  63
  64 static struct cardinfo icside_cardinfo_v6_1 = {
  65         ICS_ARCIN_V6_IDEOFFSET_1,
  66         ICS_ARCIN_V6_IDEALTOFFSET_1,
  67         ICS_ARCIN_V6_IDESTEPPING
  68 };
  69
  70 static struct cardinfo icside_cardinfo_v6_2 = {
  71         ICS_ARCIN_V6_IDEOFFSET_2,
  72         ICS_ARCIN_V6_IDEALTOFFSET_2,
  73         ICS_ARCIN_V6_IDESTEPPING
  74 };
  75
  76 static const card_ids icside_cids[] = {
  77         { MANU_ICS,  PROD_ICS_IDE  },
  78         { MANU_ICS2, PROD_ICS2_IDE },
  79         { 0xffff, 0xffff }
  80 };
  81
  82 typedef enum {
  83         ics_if_unknown,
  84         ics_if_arcin_v5,
  85         ics_if_arcin_v6
  86 } iftype_t;
  87
  88 /* ---------------- Version 5 PCB Support Functions --------------------- */
  89 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  90  * Purpose  : enable interrupts from card
  91  */
  92 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  93 {
  94         unsigned int memc_port = (unsigned int)ec->irq_data;
  95         outb (0, memc_port + ICS_ARCIN_V5_INTROFFSET);
  96 }
  97
  98 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  99  * Purpose  : disable interrupts from card
 100  */
 101 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 102 {
 103         unsigned int memc_port = (unsigned int)ec->irq_data;
 104         inb (memc_port + ICS_ARCIN_V5_INTROFFSET);
 105 }
 106
 107 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 108         icside_irqenable_arcin_v5,
 109         icside_irqdisable_arcin_v5,
 110         NULL,
 111         NULL,
 112         NULL,
 113         NULL
 114 };
 115
 116
 117 /* ---------------- Version 6 PCB Support Functions --------------------- */
 118 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 119  * Purpose  : enable interrupts from card
 120  */
 121 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 122 {
 123         unsigned int ide_base_port = (unsigned int)ec->irq_data;
 124
 125         outb (0, ide_base_port + ICS_ARCIN_V6_INTROFFSET_1);
 126         outb (0, ide_base_port + ICS_ARCIN_V6_INTROFFSET_2);
 127 }
 128
 129 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 130  * Purpose  : disable interrupts from card
 131  */
 132 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 133 {
 134         unsigned int ide_base_port = (unsigned int)ec->irq_data;
 135
 136         inb (ide_base_port + ICS_ARCIN_V6_INTROFFSET_1);
 137         inb (ide_base_port + ICS_ARCIN_V6_INTROFFSET_2);
 138 }
 139
 140 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 141  * Purpose  : detect an active interrupt from card
 142  */
 143 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 144 {
 145         unsigned int ide_base_port = (unsigned int)ec->irq_data;
 146
 147         return inb(ide_base_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 148                inb(ide_base_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 149 }
 150
 151 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 152         icside_irqenable_arcin_v6,
 153         icside_irqdisable_arcin_v6,
 154         icside_irqpending_arcin_v6,
 155         NULL,
 156         NULL,
 157         NULL
 158 };
 159
 160 /* Prototype: icside_identifyif (struct expansion_card *ec)
 161  * Purpose  : identify IDE interface type
 162  * Notes    : checks the description string
 163  */
 164 static iftype_t icside_identifyif (struct expansion_card *ec)
 165 {
 166         unsigned int addr;
 167         iftype_t iftype;
 168         int id = 0;
 169
 170         iftype = ics_if_unknown;
 171
 172         addr = ecard_address (ec, ECARD_IOC, ECARD_FAST) + ICS_IDENT_OFFSET;
 173
 174         id = inb (addr) & 1;
 175         id |= (inb (addr + 1) & 1) << 1;
 176         id |= (inb (addr + 2) & 1) << 2;
 177         id |= (inb (addr + 3) & 1) << 3;
 178
 179         switch (id) {
 180         case 0: /* A3IN */
 181                 printk("icside: A3IN unsupported\n");
 182                 break;
 183
 184         case 1: /* A3USER */
 185                 printk("icside: A3USER unsupported\n");
 186                 break;
 187
 188         case 3: /* ARCIN V6 */
 189                 printk(KERN_DEBUG "icside: detected ARCIN V6 in slot %d\n", ec->slot_no);
 190                 iftype = ics_if_arcin_v6;
 191                 break;
 192
 193         case 15:/* ARCIN V5 (no id) */
 194                 printk(KERN_DEBUG "icside: detected ARCIN V5 in slot %d\n", ec->slot_no);
 195                 iftype = ics_if_arcin_v5;
 196                 break;
 197
 198         default:/* we don't know - complain very loudly */
 199                 printk("icside: ***********************************\n");
 200                 printk("icside: *** UNKNOWN ICS INTERFACE id=%d ***\n", id);
 201                 printk("icside: ***********************************\n");
 202                 printk("icside: please report this to linux@arm.linux.org.uk\n");
 203                 printk("icside: defaulting to ARCIN V5\n");
 204                 iftype = ics_if_arcin_v5;
 205                 break;
 206         }
 207
 208         return iftype;
 209 }
 210
 211 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 212 /*
 213  * SG-DMA support.
 214  *
 215  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 216  * There is only one DMA controller per card, which means that only
 217  * one drive can be accessed at one time.  NOTE! We do not enforce that
 218  * here, but we rely on the main IDE driver spotting that both
 219  * interfaces use the same IRQ, which should guarantee this.
 220  */
 221 #define TABLE_SIZE 2048
 222
 223 static int
 224 icside_build_dmatable(ide_drive_t *drive, int reading)
 225 {
 226         struct request *rq = HWGROUP(drive)->rq;
 227         struct buffer_head *bh = rq->bh;
 228         unsigned long addr, size;
 229         unsigned char *virt_addr;
 230         unsigned int count = 0;
 231         dmasg_t *sg = (dmasg_t *)HWIF(drive)->dmatable_cpu;
 232
 233         do {
 234                 if (bh == NULL) {
 235                         /* paging requests have (rq->bh == NULL) */
 236                         virt_addr = rq->buffer;
 237                         addr = virt_to_bus (virt_addr);
 238                         size = rq->nr_sectors << 9;
 239                 } else {
 240                         /* group sequential buffers into one large buffer */
 241                         virt_addr = bh->b_data;
 242                         addr = virt_to_bus (virt_addr);
 243                         size = bh->b_size;
 244                         while ((bh = bh->b_reqnext) != NULL) {
 245                                 if ((addr + size) != virt_to_bus (bh->b_data))
 246                                         break;
 247                                 size += bh->b_size;
 248                         }
 249                 }
 250
 251                 if (addr & 3) {
 252                         printk("%s: misaligned DMA buffer\n", drive->name);
 253                         return 0;
 254                 }
 255
 256                 if (size) {
 257                         if (reading)
 258                                 dma_cache_inv((unsigned int)virt_addr, size);
 259                         else
 260                                 dma_cache_wback((unsigned int)virt_addr, size);
 261                 }
 262
 263                 sg[count].address = addr;
 264                 sg[count].length = size;
 265                 if (++count >= (TABLE_SIZE / sizeof(dmasg_t))) {
 266                         printk("%s: DMA table too small\n", drive->name);
 267                         return 0;
 268                 }
 269         } while (bh != NULL);
 270
 271         if (!count)
 272                 printk("%s: empty DMA table?\n", drive->name);
 273
 274         return count;
 275 }
 276
 277 static int
 278 icside_config_if(ide_drive_t *drive, int xfer_mode)
 279 {
 280         int func = ide_dma_off;
 281
 282         switch (xfer_mode) {
 283         case XFER_MW_DMA_2:
 284                 /*
 285                  * The cycle time is limited to 250ns by the r/w
 286                  * pulse width (90ns), however we should still
 287                  * have a maximum burst transfer rate of 8MB/s.
 288                  */
 289                 drive->drive_data = 250;
 290                 break;
 291
 292         case XFER_MW_DMA_1:
 293                 drive->drive_data = 250;
 294                 break;
 295
 296         case XFER_MW_DMA_0:
 297                 drive->drive_data = 480;
 298                 break;
 299
 300         default:
 301                 drive->drive_data = 0;
 302                 break;
 303         }
 304
 305         if (drive->drive_data &&
 306             ide_config_drive_speed(drive, (byte) xfer_mode) == 0)
 307                 func = ide_dma_on;
 308         else
 309                 drive->drive_data = 480;
 310
 311         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 312                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 313
 314         return func;
 315 }
 316
 317 static int
 318 icside_dma_check(ide_drive_t *drive)
 319 {
 320         struct hd_driveid *id = drive->id;
 321         ide_hwif_t *hwif = HWIF(drive);
 322         int autodma = hwif->autodma;
 323         int xfer_mode = XFER_PIO_2;
 324         int func = ide_dma_off_quietly;
 325
 326         if (!id || !(id->capability & 1) || !autodma)
 327                 goto out;
 328
 329         /*
 330          * Consult the list of known "bad" drives
 331          */
 332         if (ide_dmaproc(ide_dma_bad_drive, drive)) {
 333                 func = ide_dma_off;
 334                 goto out;
 335         }
 336
 337         /*
 338          * Enable DMA on any drive that has multiword DMA
 339          */
 340         if (id->field_valid & 2) {
 341                 if (id->dma_mword & 4) {
 342                         xfer_mode = XFER_MW_DMA_2;
 343                         func = ide_dma_on;
 344                 } else if (id->dma_mword & 2) {
 345                         xfer_mode = XFER_MW_DMA_1;
 346                         func = ide_dma_on;
 347                 } else if (id->dma_mword & 1) {
 348                         xfer_mode = XFER_MW_DMA_0;
 349                         func = ide_dma_on;
 350                 }
 351                 goto out;
 352         }
 353
 354         /*
 355          * Consult the list of known "good" drives
 356          */
 357         if (ide_dmaproc(ide_dma_good_drive, drive)) {
 358                 if (id->eide_dma_time > 150)
 359                         goto out;
 360                 xfer_mode = XFER_MW_DMA_1;
 361                 func = ide_dma_on;
 362         }
 363
 364 out:
 365         func = icside_config_if(drive, xfer_mode);
 366
 367         return hwif->dmaproc(func, drive);
 368 }
 369
 370 static int
 371 icside_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
 372 {
 373         ide_hwif_t *hwif = HWIF(drive);
 374         int count, reading = 0;
 375
 376         switch (func) {
 377         case ide_dma_check:
 378                 return icside_dma_check(drive);
 379
 380         case ide_dma_read:
 381                 reading = 1;
 382         case ide_dma_write:
 383                 count = icside_build_dmatable(drive, reading);
 384                 if (!count)
 385                         return 1;
 386                 disable_dma(hwif->hw.dma);
 387
 388                 /* Route the DMA signals to
 389                  * to the correct interface.
 390                  */
 391                 outb(hwif->select_data, hwif->config_data);
 392
 393                 /* Select the correct timing
 394                  * for this drive
 395                  */
 396                 set_dma_speed(hwif->hw.dma, drive->drive_data);
 397
 398                 set_dma_sg(hwif->hw.dma, (dmasg_t *)hwif->dmatable_cpu, count);
 399                 set_dma_mode(hwif->hw.dma, reading ? DMA_MODE_READ
 400                              : DMA_MODE_WRITE);
 401
 402                 drive->waiting_for_dma = 1;
 403                 if (drive->media != ide_disk)
 404                         return 0;
 405
 406                 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
 407                 OUT_BYTE(reading ? WIN_READDMA : WIN_WRITEDMA,
 408                          IDE_COMMAND_REG);
 409
 410         case ide_dma_begin:
 411                 enable_dma(hwif->hw.dma);
 412                 return 0;
 413
 414         case ide_dma_end:
 415                 drive->waiting_for_dma = 0;
 416                 disable_dma(hwif->hw.dma);
 417                 return get_dma_residue(hwif->hw.dma) != 0;
 418
 419         case ide_dma_test_irq:
 420                 return inb((unsigned long)hwif->hw.priv) & 1;
 421
 422         default:
 423                 return ide_dmaproc(func, drive);
 424         }
 425 }
 426
 427 static unsigned long
 428 icside_alloc_dmatable(void)
 429 {
 430         static unsigned long dmatable;
 431         static unsigned int leftover;
 432         unsigned long table;
 433
 434         if (leftover < TABLE_SIZE) {
 435 #if PAGE_SIZE == TABLE_SIZE * 2
 436                 dmatable = __get_free_pages(GFP_KERNEL, 1);
 437                 leftover = PAGE_SIZE;
 438 #else
 439                 dmatable = kmalloc(TABLE_SIZE, GFP_KERNEL);
 440                 leftover = TABLE_SIZE;
 441 #endif
 442         }
 443
 444         table = dmatable;
 445         if (table) {
 446                 dmatable += TABLE_SIZE;
 447                 leftover -= TABLE_SIZE;
 448         }
 449
 450         return table;
 451 }
 452
 453 static int
 454 icside_setup_dma(ide_hwif_t *hwif, int autodma)
 455 {
 456         unsigned long table = icside_alloc_dmatable();
 457
 458         printk("    %s: SG-DMA", hwif->name);
 459
 460         if (!table)
 461                 printk(" -- ERROR, unable to allocate DMA table\n");
 462         else {
 463                 hwif->dmatable_cpu = (void *)table;
 464                 hwif->dmaproc = icside_dmaproc;
 465                 hwif->autodma = autodma;
 466
 467                 printk(" capable%s\n", autodma ?
 468                         ", auto-enable" : "");
 469         }
 470
 471         return hwif->dmatable_cpu != NULL;
 472 }
 473 #endif
 474
 475 static ide_hwif_t *
 476 icside_find_hwif(unsigned long dataport)
 477 {
 478         ide_hwif_t *hwif;
 479         int index;
 480
 481         for (index = 0; index < MAX_HWIFS; ++index) {
 482                 hwif = &ide_hwifs[index];
 483                 if (hwif->hw.io_ports[IDE_DATA_OFFSET] == (ide_ioreg_t)dataport)
 484                         goto found;
 485         }
 486
 487         for (index = 0; index < MAX_HWIFS; ++index) {
 488                 hwif = &ide_hwifs[index];
 489                 if (!hwif->hw.io_ports[IDE_DATA_OFFSET])
 490                         goto found;
 491         }
 492
 493         return NULL;
 494 found:
 495         return hwif;
 496 }
 497
 498 static ide_hwif_t *
 499 icside_setup(unsigned long base, struct cardinfo *info, int irq)
 500 {
 501         unsigned long port = base + info->dataoffset;
 502         ide_hwif_t *hwif;
 503
 504         hwif = icside_find_hwif(base);
 505         if (hwif) {
 506                 int i;
 507
 508                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
 509
 510                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 511                         hwif->hw.io_ports[i] = (ide_ioreg_t)port;
 512                         port += 1 << info->stepping;
 513                 }
 514                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = base + info->ctrloffset;
 515                 hwif->hw.irq  = irq;
 516                 hwif->hw.dma  = NO_DMA;
 517                 hwif->noprobe = 0;
 518                 hwif->chipset = ide_acorn;
 519         }
 520
 521         return hwif;
 522 }
 523
 524 static int icside_register_v5(struct expansion_card *ec, int autodma)
 525 {
 526         unsigned long slot_port;
 527         ide_hwif_t *hwif;
 528
 529         slot_port = ecard_address(ec, ECARD_MEMC, 0);
 530
 531         ec->irqaddr  = (unsigned char *)ioaddr(slot_port + ICS_ARCIN_V5_INTRSTAT);
 532         ec->irqmask  = 1;
 533         ec->irq_data = (void *)slot_port;
 534         ec->ops      = (expansioncard_ops_t *)&icside_ops_arcin_v5;
 535
 536         /*
 537          * Be on the safe side - disable interrupts
 538          */
 539         inb(slot_port + ICS_ARCIN_V5_INTROFFSET);
 540
 541         hwif = icside_setup(slot_port, &icside_cardinfo_v5, ec->irq);
 542
 543         return hwif ? 0 : -1;
 544 }
 545
 546 static int icside_register_v6(struct expansion_card *ec, int autodma)
 547 {
 548         unsigned long slot_port, port;
 549         ide_hwif_t *hwif, *mate;
 550         int sel = 0;
 551
 552         slot_port = ecard_address(ec, ECARD_IOC, ECARD_FAST);
 553         port      = ecard_address(ec, ECARD_EASI, ECARD_FAST);
 554
 555         if (port == 0)
 556                 port = slot_port;
 557         else
 558                 sel = 1 << 5;
 559
 560         outb(sel, slot_port);
 561
 562         ec->irq_data = (void *)port;
 563         ec->ops      = (expansioncard_ops_t *)&icside_ops_arcin_v6;
 564
 565         /*
 566          * Be on the safe side - disable interrupts
 567          */
 568         inb(port + ICS_ARCIN_V6_INTROFFSET_1);
 569         inb(port + ICS_ARCIN_V6_INTROFFSET_2);
 570
 571         hwif = icside_setup(port, &icside_cardinfo_v6_1, ec->irq);
 572         mate = icside_setup(port, &icside_cardinfo_v6_2, ec->irq);
 573
 574 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 575         if (ec->dma != NO_DMA) {
 576                 if (request_dma(ec->dma, hwif->name))
 577                         goto no_dma;
 578
 579                 if (hwif) {
 580                         hwif->config_data = slot_port;
 581                         hwif->select_data = sel;
 582                         hwif->hw.dma  = ec->dma;
 583                         hwif->hw.priv = (void *)
 584                                         (port + ICS_ARCIN_V6_INTRSTAT_1);
 585                         hwif->channel = 0;
 586                         icside_setup_dma(hwif, autodma);
 587                 }
 588                 if (mate) {
 589                         mate->config_data = slot_port;
 590                         mate->select_data = sel | 1;
 591                         mate->hw.dma  = ec->dma;
 592                         mate->hw.priv = (void *)
 593                                         (port + ICS_ARCIN_V6_INTRSTAT_2);
 594                         mate->channel = 1;
 595                         icside_setup_dma(mate, autodma);
 596                 }
 597         }
 598 #endif
 599
 600 no_dma:
 601         return hwif || mate ? 0 : -1;
 602 }
 603
 604 int icside_init(void)
 605 {
 606         int autodma = 0;
 607
 608 #ifdef CONFIG_IDEDMA_ICS_AUTO
 609         autodma = 1;
 610 #endif
 611
 612         ecard_startfind ();
 613
 614         do {
 615                 struct expansion_card *ec;
 616                 int result;
 617
 618                 ec = ecard_find(0, icside_cids);
 619                 if (ec == NULL)
 620                         break;
 621
 622                 ecard_claim(ec);
 623
 624                 switch (icside_identifyif(ec)) {
 625                 case ics_if_arcin_v5:
 626                         result = icside_register_v5(ec, autodma);
 627                         break;
 628
 629                 case ics_if_arcin_v6:
 630                         result = icside_register_v6(ec, autodma);
 631                         break;
 632
 633                 default:
 634                         result = -1;
 635                         break;
 636                 }
 637
 638                 if (result)
 639                         ecard_release(ec);
 640         } while (1);
 641
 642         return 0;
 643 }