[MIPS] Alchemy: Fix PCI-memory access
[linux-2.6/linux-mips.git] / include / asm-sparc / msi.h
blobff72cbd946a4462df51ddf4e19b22b468f7f8bc4
1 /* $Id: msi.h,v 1.3 1996/08/29 09:48:25 davem Exp $
2 * msi.h: Defines specific to the MBus - Sbus - Interface.
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 */
8 #ifndef _SPARC_MSI_H
9 #define _SPARC_MSI_H
12 * Locations of MSI Registers.
14 #define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
17 * Useful bits in the MSI Registers.
19 #define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
22 static inline void msi_set_sync(void)
24 __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
25 "andn %%g3, %2, %%g3\n\t"
26 "sta %%g3, [%0] %1\n\t" : :
27 "r" (MSI_MBUS_ARBEN),
28 "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
31 #endif /* !(_SPARC_MSI_H) */