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Merge with 2.3.48.
[linux-2.6/linux-mips.git] / drivers / sound / es1371.c
blob95158296aea440b181d97e76a58f00d0740016cb
1 /*****************************************************************************/
2
3 /*
4 * es1371.c -- Creative Ensoniq ES1371.
5 *
6 * Copyright (C) 1998-2000 Thomas Sailer (sailer@ife.ee.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Special thanks to Ensoniq
23 *
24 *
25 * Module command line parameters:
26 * joystick must be set to the base I/O-Port to be used for
27 * the gameport. Legal values are 0x200, 0x208, 0x210 and 0x218.
28 * The gameport is mirrored eight times.
29 *
30 * Supported devices:
31 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
32 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
33 * /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
34 * /dev/midi simple MIDI UART interface, no ioctl
35 *
36 * NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
37 * to be done in software. That is what /dev/dac is for. By now (Q2 1998)
38 * there are several MIDI to PCM (WAV) packages, one of them is timidity.
39 *
40 * Revision history
41 * 04.06.1998 0.1 Initial release
42 * Mixer stuff should be overhauled; especially optional AC97 mixer bits
43 * should be detected. This results in strange behaviour of some mixer
44 * settings, like master volume and mic.
45 * 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice
46 * 03.08.1998 0.3 Do not include modversions.h
47 * Now mixer behaviour can basically be selected between
48 * "OSS documented" and "OSS actual" behaviour
49 * 31.08.1998 0.4 Fix realplayer problems - dac.count issues
50 * 27.10.1998 0.5 Fix joystick support
51 * -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
52 * 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA
53 * 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs
54 * Don't wake up app until there are fragsize bytes to read/write
55 * 06.01.1999 0.8 remove the silly SA_INTERRUPT flag.
56 * hopefully killed the egcs section type conflict
57 * 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl.
58 * reported by Johan Maes <joma@telindus.be>
59 * 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK
60 * read/write cannot be executed
61 * 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE,
62 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
63 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
64 * Another Alpha fix (wait_src_ready in init routine)
65 * reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
66 * Note: joystick address handling might still be wrong on archs
67 * other than i386
68 * 15.06.1999 0.12 Fix bad allocation bug.
69 * Thanks to Deti Fliegl <fliegl@in.tum.de>
70 * 28.06.1999 0.13 Add pci_set_master
71 * 03.08.1999 0.14 adapt to Linus' new __setup/__initcall
72 * added kernel command line option "es1371=joystickaddr"
73 * removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
74 * 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4.
75 * Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
76 * module_init/__setup fixes
77 * 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com>
78 * Added detection for ES1371 revision ID so that we can
79 * detect the ES1373 and later parts.
80 * added AC97 #defines for readability
81 * added a /proc file system for dumping hardware state
82 * updated SRC and CODEC w/r functions to accomodate bugs
83 * in some versions of the ES137x chips.
84 * 31.08.1999 0.17 add spin_lock_init
85 * __initlocaldata to fix gcc 2.7.x problems
86 * replaced current->state = x with set_current_state(x)
87 * 03.09.1999 0.18 change read semantics for MIDI to match
88 * OSS more closely; remove possible wakeup race
89 * 21.10.1999 0.19 Round sampling rates, requested by
90 * Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
91 * 27.10.1999 0.20 Added SigmaTel 3D enhancement string
92 * Codec ID printing changes
93 * 28.10.1999 0.21 More waitqueue races fixed
94 * Joe Cotellese <joec@ensoniq.com>
95 * Changed PCI detection routine so we can more easily
96 * detect ES137x chip and derivatives.
97 * 05.01.2000 0.22 Should now work with rev7 boards; patch by
98 * Eric Lemar, elemar@cs.washington.edu
99 * 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun;
100 * Tim Janik's BSE (Bedevilled Sound Engine) found this
101 * 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver
102 * 07.02.2000 0.25 Use ac97_codec
103 */
104
105 /*****************************************************************************/
106
107 #include <linux/version.h>
108 #include <linux/module.h>
109 #include <linux/string.h>
110 #include <linux/ioport.h>
111 #include <linux/sched.h>
112 #include <linux/delay.h>
113 #include <linux/sound.h>
114 #include <linux/malloc.h>
115 #include <linux/soundcard.h>
116 #include <linux/pci.h>
117 #include <linux/init.h>
118 #include <linux/poll.h>
119 #include <linux/bitops.h>
120 #include <linux/proc_fs.h>
121 #include <linux/spinlock.h>
122 #include <linux/ac97_codec.h>
123 #include <asm/io.h>
124 #include <asm/dma.h>
125 #include <asm/uaccess.h>
126 #include <asm/hardirq.h>
127
128 /* --------------------------------------------------------------------- */
129
130 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
131 #define ES1371_DEBUG
132 #define DBG(x) {}
133 /*#define DBG(x) {x}*/
134
135 /* --------------------------------------------------------------------- */
136
137 #ifndef PCI_VENDOR_ID_ENSONIQ
138 #define PCI_VENDOR_ID_ENSONIQ 0x1274
139 #endif
140
141 #ifndef PCI_VENDOR_ID_ECTIVA
142 #define PCI_VENDOR_ID_ECTIVA 0x1102
143 #endif
144
145 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
146 #define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
147 #endif
148
149 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
150 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
151 #endif
152
153 #ifndef PCI_DEVICE_ID_ECTIVA_EV1938
154 #define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
155 #endif
156
157 /* ES1371 chip ID */
158 /* This is a little confusing because all ES1371 compatible chips have the
159 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
160 This is only significant if you want to enable features on the later parts.
161 Yes, I know it's stupid and why didn't we use the sub IDs?
162 */
163 #define ES1371REV_ES1373_A 0x04
164 #define ES1371REV_ES1373_B 0x06
165 #define ES1371REV_CT5880_A 0x07
166 #define CT5880REV_CT5880_C 0x02
167 #define ES1371REV_ES1371_B 0x09
168 #define EV1938REV_EV1938_A 0x00
169
170 #define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
171
172 #define ES1371_EXTENT 0x40
173 #define JOY_EXTENT 8
174
175 #define ES1371_REG_CONTROL 0x00
176 #define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */
177 #define ES1371_REG_UART_DATA 0x08
178 #define ES1371_REG_UART_STATUS 0x09
179 #define ES1371_REG_UART_CONTROL 0x09
180 #define ES1371_REG_UART_TEST 0x0a
181 #define ES1371_REG_MEMPAGE 0x0c
182 #define ES1371_REG_SRCONV 0x10
183 #define ES1371_REG_CODEC 0x14
184 #define ES1371_REG_LEGACY 0x18
185 #define ES1371_REG_SERIAL_CONTROL 0x20
186 #define ES1371_REG_DAC1_SCOUNT 0x24
187 #define ES1371_REG_DAC2_SCOUNT 0x28
188 #define ES1371_REG_ADC_SCOUNT 0x2c
189
190 #define ES1371_REG_DAC1_FRAMEADR 0xc30
191 #define ES1371_REG_DAC1_FRAMECNT 0xc34
192 #define ES1371_REG_DAC2_FRAMEADR 0xc38
193 #define ES1371_REG_DAC2_FRAMECNT 0xc3c
194 #define ES1371_REG_ADC_FRAMEADR 0xd30
195 #define ES1371_REG_ADC_FRAMECNT 0xd34
196
197 #define ES1371_FMT_U8_MONO 0
198 #define ES1371_FMT_U8_STEREO 1
199 #define ES1371_FMT_S16_MONO 2
200 #define ES1371_FMT_S16_STEREO 3
201 #define ES1371_FMT_STEREO 1
202 #define ES1371_FMT_S16 2
203 #define ES1371_FMT_MASK 3
204
205 static const unsigned sample_size[] = { 1, 2, 2, 4 };
206 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
207
208 #define CTRL_SPDIFEN_B 0x04000000
209 #define CTRL_JOY_SHIFT 24
210 #define CTRL_JOY_MASK 3
211 #define CTRL_JOY_200 0x00000000 /* joystick base address */
212 #define CTRL_JOY_208 0x01000000
213 #define CTRL_JOY_210 0x02000000
214 #define CTRL_JOY_218 0x03000000
215 #define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */
216 #define CTRL_GPIO_IN1 0x00200000
217 #define CTRL_GPIO_IN2 0x00400000
218 #define CTRL_GPIO_IN3 0x00800000
219 #define CTRL_GPIO_OUT0 0x00010000
220 #define CTRL_GPIO_OUT1 0x00020000
221 #define CTRL_GPIO_OUT2 0x00040000
222 #define CTRL_GPIO_OUT3 0x00080000
223 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
224 #define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */
225 #define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */
226 #define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */
227 #define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */
228 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
229 #define CTRL_PDLEV0 0x00000000 /* power down level */
230 #define CTRL_PDLEV1 0x00000100
231 #define CTRL_PDLEV2 0x00000200
232 #define CTRL_PDLEV3 0x00000300
233 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
234 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
235 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
236 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
237 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
238 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */
239 #define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */
240 #define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */
241
242
243 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
244 #define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
245 #define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */
246 #define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */
247 #define STAT_TESTMODE 0x00010000 /* test ASIC */
248 #define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */
249 #define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
250 #define STAT_SH_VC 6
251 #define STAT_MPWR 0x00000020 /* power level interrupt */
252 #define STAT_MCCB 0x00000010 /* CCB int pending */
253 #define STAT_UART 0x00000008 /* UART int pending */
254 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
255 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
256 #define STAT_ADC 0x00000001 /* ADC int pending */
257
258 #define USTAT_RXINT 0x80 /* UART rx int pending */
259 #define USTAT_TXINT 0x04 /* UART tx int pending */
260 #define USTAT_TXRDY 0x02 /* UART tx ready */
261 #define USTAT_RXRDY 0x01 /* UART rx ready */
262
263 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
264 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
265 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
266 #define UCTRL_CNTRL 0x03 /* control field */
267 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
268
269 /* sample rate converter */
270 #define SRC_OKSTATE 1
271
272 #define SRC_RAMADDR_MASK 0xfe000000
273 #define SRC_RAMADDR_SHIFT 25
274 #define SRC_DAC1FREEZE (1UL << 21)
275 #define SRC_DAC2FREEZE (1UL << 20)
276 #define SRC_ADCFREEZE (1UL << 19)
277
278
279 #define SRC_WE 0x01000000 /* read/write control for SRC RAM */
280 #define SRC_BUSY 0x00800000 /* SRC busy */
281 #define SRC_DIS 0x00400000 /* 1 = disable SRC */
282 #define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */
283 #define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */
284 #define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */
285 #define SRC_CTLMASK 0x00780000
286 #define SRC_RAMDATA_MASK 0x0000ffff
287 #define SRC_RAMDATA_SHIFT 0
288
289 #define SRCREG_ADC 0x78
290 #define SRCREG_DAC1 0x70
291 #define SRCREG_DAC2 0x74
292 #define SRCREG_VOL_ADC 0x6c
293 #define SRCREG_VOL_DAC1 0x7c
294 #define SRCREG_VOL_DAC2 0x7e
295
296 #define SRCREG_TRUNC_N 0x00
297 #define SRCREG_INT_REGS 0x01
298 #define SRCREG_ACCUM_FRAC 0x02
299 #define SRCREG_VFREQ_FRAC 0x03
300
301 #define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
302 #define CODEC_PIADD_MASK 0x007f0000
303 #define CODEC_PIADD_SHIFT 16
304 #define CODEC_PIDAT_MASK 0x0000ffff
305 #define CODEC_PIDAT_SHIFT 0
306
307 #define CODEC_RDY 0x80000000 /* AC97 read data valid */
308 #define CODEC_WIP 0x40000000 /* AC97 write in progress */
309 #define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
310 #define CODEC_POADD_MASK 0x007f0000
311 #define CODEC_POADD_SHIFT 16
312 #define CODEC_PODAT_MASK 0x0000ffff
313 #define CODEC_PODAT_SHIFT 0
314
315
316 #define LEGACY_JFAST 0x80000000 /* fast joystick timing */
317 #define LEGACY_FIRQ 0x01000000 /* force IRQ */
318
319 #define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */
320 #define SCTRL_P2ENDINC 0x00380000 /* */
321 #define SCTRL_SH_P2ENDINC 19
322 #define SCTRL_P2STINC 0x00070000 /* */
323 #define SCTRL_SH_P2STINC 16
324 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
325 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
326 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
327 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
328 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
329 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
330 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
331 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
332 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
333 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
334 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
335 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
336 #define SCTRL_R1FMT 0x00000030 /* format mask */
337 #define SCTRL_SH_R1FMT 4
338 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
339 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
340 #define SCTRL_P2FMT 0x0000000c /* format mask */
341 #define SCTRL_SH_P2FMT 2
342 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
343 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
344 #define SCTRL_P1FMT 0x00000003 /* format mask */
345 #define SCTRL_SH_P1FMT 0
346
347 /* codec constants */
348
349 #define CODEC_ID_DEDICATEDMIC 0x001
350 #define CODEC_ID_MODEMCODEC 0x002
351 #define CODEC_ID_BASSTREBLE 0x004
352 #define CODEC_ID_SIMULATEDSTEREO 0x008
353 #define CODEC_ID_HEADPHONEOUT 0x010
354 #define CODEC_ID_LOUDNESS 0x020
355 #define CODEC_ID_18BITDAC 0x040
356 #define CODEC_ID_20BITDAC 0x080
357 #define CODEC_ID_18BITADC 0x100
358 #define CODEC_ID_20BITADC 0x200
359
360 #define CODEC_ID_SESHIFT 10
361 #define CODEC_ID_SEMASK 0x1f
362
363
364 /* misc stuff */
365 #define POLL_COUNT 0x1000
366 #define FMODE_DAC 4 /* slight misuse of mode_t */
367
368 /* MIDI buffer sizes */
369
370 #define MIDIINBUF 256
371 #define MIDIOUTBUF 256
372
373 #define FMODE_MIDI_SHIFT 3
374 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
375 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
376
377 #define SND_DEV_DSP16 5
378
379 #define ES1371_MODULE_NAME "es1371"
380 #define PFX ES1371_MODULE_NAME ": "
381
382 /* --------------------------------------------------------------------- */
383
384 struct es1371_state {
385 /* magic */
386 unsigned int magic;
387
388 /* list of es1371 devices */
389 struct list_head devs;
390
391 /* the corresponding pci_dev structure */
392 struct pci_dev *dev;
393
394 /* soundcore stuff */
395 int dev_audio;
396 int dev_dac;
397 int dev_midi;
398
399 /* hardware resources */
400 unsigned long io; /* long for SPARC */
401 unsigned int irq;
402
403 /* PCI ID's */
404 u16 vendor;
405 u16 device;
406 u8 rev; /* the chip revision */
407
408 #ifdef ES1371_DEBUG
409 /* debug /proc entry */
410 struct proc_dir_entry *ps;
411 #endif /* ES1371_DEBUG */
412
413 struct ac97_codec codec;
414
415 /* wave stuff */
416 unsigned ctrl;
417 unsigned sctrl;
418 unsigned dac1rate, dac2rate, adcrate;
419
420 spinlock_t lock;
421 struct semaphore open_sem;
422 mode_t open_mode;
423 wait_queue_head_t open_wait;
424
425 struct dmabuf {
426 void *rawbuf;
427 dma_addr_t dmaaddr;
428 unsigned buforder;
429 unsigned numfrag;
430 unsigned fragshift;
431 unsigned hwptr, swptr;
432 unsigned total_bytes;
433 int count;
434 unsigned error; /* over/underrun */
435 wait_queue_head_t wait;
436 /* redundant, but makes calculations easier */
437 unsigned fragsize;
438 unsigned dmasize;
439 unsigned fragsamples;
440 /* OSS stuff */
441 unsigned mapped:1;
442 unsigned ready:1;
443 unsigned endcleared:1;
444 unsigned ossfragshift;
445 int ossmaxfrags;
446 unsigned subdivision;
447 } dma_dac1, dma_dac2, dma_adc;
448
449 /* midi stuff */
450 struct {
451 unsigned ird, iwr, icnt;
452 unsigned ord, owr, ocnt;
453 wait_queue_head_t iwait;
454 wait_queue_head_t owait;
455 unsigned char ibuf[MIDIINBUF];
456 unsigned char obuf[MIDIOUTBUF];
457 } midi;
458 };
459
460 /* --------------------------------------------------------------------- */
461
462 static LIST_HEAD(devs);
463
464 /* --------------------------------------------------------------------- */
465
466 extern inline unsigned ld2(unsigned int x)
467 {
468 unsigned r = 0;
469
470 if (x >= 0x10000) {
471 x >>= 16;
472 r += 16;
473 }
474 if (x >= 0x100) {
475 x >>= 8;
476 r += 8;
477 }
478 if (x >= 0x10) {
479 x >>= 4;
480 r += 4;
481 }
482 if (x >= 4) {
483 x >>= 2;
484 r += 2;
485 }
486 if (x >= 2)
487 r++;
488 return r;
489 }
490
491 /* --------------------------------------------------------------------- */
492
493 static unsigned wait_src_ready(struct es1371_state *s)
494 {
495 unsigned int t, r;
496
497 for (t = 0; t < POLL_COUNT; t++) {
498 if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
499 return r;
500 udelay(1);
501 }
502 printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
503 return r;
504 }
505
506 static unsigned src_read(struct es1371_state *s, unsigned reg)
507 {
508 unsigned int temp,i,orig;
509
510 /* wait for ready */
511 temp = wait_src_ready (s);
512
513 /* we can only access the SRC at certain times, make sure
514 we're allowed to before we read */
515
516 orig = temp;
517 /* expose the SRC state bits */
518 outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
519 s->io + ES1371_REG_SRCONV);
520
521 /* now, wait for busy and the correct time to read */
522 temp = wait_src_ready (s);
523
524 if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
525 /* wait for the right state */
526 for (i=0; i<POLL_COUNT; i++){
527 temp = inl (s->io + ES1371_REG_SRCONV);
528 if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
529 break;
530 }
531 }
532
533 /* hide the state bits */
534 outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
535 return temp;
536
537
538 }
539
540 static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
541 {
542
543 unsigned int r;
544
545 r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
546 r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
547 r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
548 outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
549
550 }
551
552 /* --------------------------------------------------------------------- */
553
554 /* most of the following here is black magic */
555 static void set_adc_rate(struct es1371_state *s, unsigned rate)
556 {
557 unsigned long flags;
558 unsigned int n, truncm, freq;
559
560 if (rate > 48000)
561 rate = 48000;
562 if (rate < 4000)
563 rate = 4000;
564 n = rate / 3000;
565 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
566 n--;
567 truncm = (21 * n - 1) | 1;
568 freq = ((48000UL << 15) / rate) * n;
569 s->adcrate = (48000UL << 15) / (freq / n);
570 spin_lock_irqsave(&s->lock, flags);
571 if (rate >= 24000) {
572 if (truncm > 239)
573 truncm = 239;
574 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
575 (((239 - truncm) >> 1) << 9) | (n << 4));
576 } else {
577 if (truncm > 119)
578 truncm = 119;
579 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
580 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
581 }
582 src_write(s, SRCREG_ADC+SRCREG_INT_REGS,
583 (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
584 ((freq >> 5) & 0xfc00));
585 src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
586 src_write(s, SRCREG_VOL_ADC, n << 8);
587 src_write(s, SRCREG_VOL_ADC+1, n << 8);
588 spin_unlock_irqrestore(&s->lock, flags);
589 }
590
591
592 static void set_dac1_rate(struct es1371_state *s, unsigned rate)
593 {
594 unsigned long flags;
595 unsigned int freq, r;
596
597 if (rate > 48000)
598 rate = 48000;
599 if (rate < 4000)
600 rate = 4000;
601 freq = ((rate << 15) + 1500) / 3000;
602 s->dac1rate = (freq * 3000 + 16384) >> 15;
603 spin_lock_irqsave(&s->lock, flags);
604 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
605 outl(r, s->io + ES1371_REG_SRCONV);
606 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS,
607 (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
608 ((freq >> 5) & 0xfc00));
609 src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
610 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
611 outl(r, s->io + ES1371_REG_SRCONV);
612 spin_unlock_irqrestore(&s->lock, flags);
613 }
614
615 static void set_dac2_rate(struct es1371_state *s, unsigned rate)
616 {
617 unsigned long flags;
618 unsigned int freq, r;
619
620 if (rate > 48000)
621 rate = 48000;
622 if (rate < 4000)
623 rate = 4000;
624 freq = ((rate << 15) + 1500) / 3000;
625 s->dac2rate = (freq * 3000 + 16384) >> 15;
626 spin_lock_irqsave(&s->lock, flags);
627 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
628 outl(r, s->io + ES1371_REG_SRCONV);
629 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS,
630 (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
631 ((freq >> 5) & 0xfc00));
632 src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
633 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
634 outl(r, s->io + ES1371_REG_SRCONV);
635 spin_unlock_irqrestore(&s->lock, flags);
636 }
637
638 /* --------------------------------------------------------------------- */
639
640 static void __init src_init(struct es1371_state *s)
641 {
642 unsigned int i;
643
644 /* before we enable or disable the SRC we need
645 to wait for it to become ready */
646 wait_src_ready(s);
647
648 outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
649
650 for (i = 0; i < 0x80; i++)
651 src_write(s, i, 0);
652
653 src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
654 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
655 src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
656 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
657 src_write(s, SRCREG_VOL_ADC, 1 << 12);
658 src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
659 src_write(s, SRCREG_VOL_DAC1, 1 << 12);
660 src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
661 src_write(s, SRCREG_VOL_DAC2, 1 << 12);
662 src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
663 set_adc_rate(s, 22050);
664 set_dac1_rate(s, 22050);
665 set_dac2_rate(s, 22050);
666
667 /* WARNING:
668 * enabling the sample rate converter without properly programming
669 * its parameters causes the chip to lock up (the SRC busy bit will
670 * be stuck high, and I've found no way to rectify this other than
671 * power cycle)
672 */
673 wait_src_ready(s);
674 outl(0, s->io+ES1371_REG_SRCONV);
675 }
676
677 /* --------------------------------------------------------------------- */
678
679 static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
680 {
681 struct es1371_state *s = (struct es1371_state *)codec->private_data;
682 unsigned long flags;
683 unsigned t, x;
684
685 for (t = 0; t < POLL_COUNT; t++)
686 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
687 break;
688 spin_lock_irqsave(&s->lock, flags);
689
690 /* save the current state for later */
691 x = wait_src_ready(s);
692
693 /* enable SRC state data in SRC mux */
694 outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
695 s->io+ES1371_REG_SRCONV);
696
697 /* wait for not busy (state 0) first to avoid
698 transition states */
699 for (t=0; t<POLL_COUNT; t++){
700 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
701 break;
702 udelay(1);
703 }
704
705 /* wait for a SAFE time to write addr/data and then do it, dammit */
706 for (t=0; t<POLL_COUNT; t++){
707 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
708 break;
709 udelay(1);
710 }
711
712 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
713 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
714
715 /* restore SRC reg */
716 wait_src_ready(s);
717 outl(x, s->io+ES1371_REG_SRCONV);
718 spin_unlock_irqrestore(&s->lock, flags);
719 }
720
721 static u16 rdcodec(struct ac97_codec *codec, u8 addr)
722 {
723 struct es1371_state *s = (struct es1371_state *)codec->private_data;
724 unsigned long flags;
725 unsigned t, x;
726
727 /* wait for WIP to go away */
728 for (t = 0; t < 0x1000; t++)
729 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
730 break;
731 spin_lock_irqsave(&s->lock, flags);
732
733 /* save the current state for later */
734 x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
735
736 /* enable SRC state data in SRC mux */
737 outl( x | 0x00010000,
738 s->io+ES1371_REG_SRCONV);
739
740 /* wait for not busy (state 0) first to avoid
741 transition states */
742 for (t=0; t<POLL_COUNT; t++){
743 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
744 break;
745 udelay(1);
746 }
747
748 /* wait for a SAFE time to write addr/data and then do it, dammit */
749 for (t=0; t<POLL_COUNT; t++){
750 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
751 break;
752 udelay(1);
753 }
754
755 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
756 /* restore SRC reg */
757 wait_src_ready(s);
758 outl(x, s->io+ES1371_REG_SRCONV);
759 spin_unlock_irqrestore(&s->lock, flags);
760
761 /* wait for WIP again */
762 for (t = 0; t < 0x1000; t++)
763 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
764 break;
765
766 /* now wait for the stinkin' data (RDY) */
767 for (t = 0; t < POLL_COUNT; t++)
768 if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
769 break;
770
771 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
772 }
773
774 /* --------------------------------------------------------------------- */
775
776 extern inline void stop_adc(struct es1371_state *s)
777 {
778 unsigned long flags;
779
780 spin_lock_irqsave(&s->lock, flags);
781 s->ctrl &= ~CTRL_ADC_EN;
782 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
783 spin_unlock_irqrestore(&s->lock, flags);
784 }
785
786 extern inline void stop_dac1(struct es1371_state *s)
787 {
788 unsigned long flags;
789
790 spin_lock_irqsave(&s->lock, flags);
791 s->ctrl &= ~CTRL_DAC1_EN;
792 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
793 spin_unlock_irqrestore(&s->lock, flags);
794 }
795
796 extern inline void stop_dac2(struct es1371_state *s)
797 {
798 unsigned long flags;
799
800 spin_lock_irqsave(&s->lock, flags);
801 s->ctrl &= ~CTRL_DAC2_EN;
802 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
803 spin_unlock_irqrestore(&s->lock, flags);
804 }
805
806 static void start_dac1(struct es1371_state *s)
807 {
808 unsigned long flags;
809 unsigned fragremain, fshift;
810
811 spin_lock_irqsave(&s->lock, flags);
812 if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
813 && s->dma_dac1.ready) {
814 s->ctrl |= CTRL_DAC1_EN;
815 s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
816 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
817 fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
818 fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
819 if (fragremain < 2*fshift)
820 fragremain = s->dma_dac1.fragsize;
821 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
822 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
823 outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
824 }
825 spin_unlock_irqrestore(&s->lock, flags);
826 }
827
828 static void start_dac2(struct es1371_state *s)
829 {
830 unsigned long flags;
831 unsigned fragremain, fshift;
832
833 spin_lock_irqsave(&s->lock, flags);
834 if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
835 && s->dma_dac2.ready) {
836 s->ctrl |= CTRL_DAC2_EN;
837 s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN |
838 SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
839 (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) |
840 (0 << SCTRL_SH_P2STINC);
841 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
842 fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
843 fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
844 if (fragremain < 2*fshift)
845 fragremain = s->dma_dac2.fragsize;
846 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
847 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
848 outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
849 }
850 spin_unlock_irqrestore(&s->lock, flags);
851 }
852
853 static void start_adc(struct es1371_state *s)
854 {
855 unsigned long flags;
856 unsigned fragremain, fshift;
857
858 spin_lock_irqsave(&s->lock, flags);
859 if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
860 && s->dma_adc.ready) {
861 s->ctrl |= CTRL_ADC_EN;
862 s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
863 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
864 fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
865 fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
866 if (fragremain < 2*fshift)
867 fragremain = s->dma_adc.fragsize;
868 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
869 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
870 outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
871 }
872 spin_unlock_irqrestore(&s->lock, flags);
873 }
874
875 /* --------------------------------------------------------------------- */
876
877 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
878 #define DMABUF_MINORDER 1
879
880
881 extern inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
882 {
883 unsigned long map, mapend;
884
885 if (db->rawbuf) {
886 /* undo marking the pages as reserved */
887 mapend = MAP_NR(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
888 for (map = MAP_NR(db->rawbuf); map <= mapend; map++)
889 clear_bit(PG_reserved, &mem_map[map].flags);
890 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
891 }
892 db->rawbuf = NULL;
893 db->mapped = db->ready = 0;
894 }
895
896 static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
897 {
898 int order;
899 unsigned bytepersec;
900 unsigned bufs;
901 unsigned long map, mapend;
902
903 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
904 if (!db->rawbuf) {
905 db->ready = db->mapped = 0;
906 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
907 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
908 break;
909 if (!db->rawbuf)
910 return -ENOMEM;
911 db->buforder = order;
912 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
913 mapend = MAP_NR(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
914 for (map = MAP_NR(db->rawbuf); map <= mapend; map++)
915 set_bit(PG_reserved, &mem_map[map].flags);
916 }
917 fmt &= ES1371_FMT_MASK;
918 bytepersec = rate << sample_shift[fmt];
919 bufs = PAGE_SIZE << db->buforder;
920 if (db->ossfragshift) {
921 if ((1000 << db->ossfragshift) < bytepersec)
922 db->fragshift = ld2(bytepersec/1000);
923 else
924 db->fragshift = db->ossfragshift;
925 } else {
926 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
927 if (db->fragshift < 3)
928 db->fragshift = 3;
929 }
930 db->numfrag = bufs >> db->fragshift;
931 while (db->numfrag < 4 && db->fragshift > 3) {
932 db->fragshift--;
933 db->numfrag = bufs >> db->fragshift;
934 }
935 db->fragsize = 1 << db->fragshift;
936 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
937 db->numfrag = db->ossmaxfrags;
938 db->fragsamples = db->fragsize >> sample_shift[fmt];
939 db->dmasize = db->numfrag << db->fragshift;
940 memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
941 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
942 outl(db->dmaaddr, s->io+(reg & 0xff));
943 outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
944 db->ready = 1;
945 return 0;
946 }
947
948 extern inline int prog_dmabuf_adc(struct es1371_state *s)
949 {
950 stop_adc(s);
951 return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK,
952 ES1371_REG_ADC_FRAMEADR);
953 }
954
955 extern inline int prog_dmabuf_dac2(struct es1371_state *s)
956 {
957 stop_dac2(s);
958 return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK,
959 ES1371_REG_DAC2_FRAMEADR);
960 }
961
962 extern inline int prog_dmabuf_dac1(struct es1371_state *s)
963 {
964 stop_dac1(s);
965 return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
966 ES1371_REG_DAC1_FRAMEADR);
967 }
968
969 extern inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
970 {
971 unsigned hwptr, diff;
972
973 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
974 hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
975 diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
976 db->hwptr = hwptr;
977 return diff;
978 }
979
980 extern inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
981 {
982 if (bptr + len > bsize) {
983 unsigned x = bsize - bptr;
984 memset(((char *)buf) + bptr, c, x);
985 bptr = 0;
986 len -= x;
987 }
988 memset(((char *)buf) + bptr, c, len);
989 }
990
991 /* call with spinlock held! */
992 static void es1371_update_ptr(struct es1371_state *s)
993 {
994 int diff;
995
996 /* update ADC pointer */
997 if (s->ctrl & CTRL_ADC_EN) {
998 diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);
999 s->dma_adc.total_bytes += diff;
1000 s->dma_adc.count += diff;
1001 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1002 wake_up(&s->dma_adc.wait);
1003 if (!s->dma_adc.mapped) {
1004 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1005 s->ctrl &= ~CTRL_ADC_EN;
1006 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1007 s->dma_adc.error++;
1008 }
1009 }
1010 }
1011 /* update DAC1 pointer */
1012 if (s->ctrl & CTRL_DAC1_EN) {
1013 diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT);
1014 s->dma_dac1.total_bytes += diff;
1015 if (s->dma_dac1.mapped) {
1016 s->dma_dac1.count += diff;
1017 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
1018 wake_up(&s->dma_dac1.wait);
1019 } else {
1020 s->dma_dac1.count -= diff;
1021 if (s->dma_dac1.count <= 0) {
1022 s->ctrl &= ~CTRL_DAC1_EN;
1023 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1024 s->dma_dac1.error++;
1025 } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) {
1026 clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr,
1027 s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80);
1028 s->dma_dac1.endcleared = 1;
1029 }
1030 if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize)
1031 wake_up(&s->dma_dac1.wait);
1032 }
1033 }
1034 /* update DAC2 pointer */
1035 if (s->ctrl & CTRL_DAC2_EN) {
1036 diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT);
1037 s->dma_dac2.total_bytes += diff;
1038 if (s->dma_dac2.mapped) {
1039 s->dma_dac2.count += diff;
1040 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1041 wake_up(&s->dma_dac2.wait);
1042 } else {
1043 s->dma_dac2.count -= diff;
1044 if (s->dma_dac2.count <= 0) {
1045 s->ctrl &= ~CTRL_DAC2_EN;
1046 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1047 s->dma_dac2.error++;
1048 } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) {
1049 clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr,
1050 s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80);
1051 s->dma_dac2.endcleared = 1;
1052 }
1053 if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize)
1054 wake_up(&s->dma_dac2.wait);
1055 }
1056 }
1057 }
1058
1059 /* hold spinlock for the following! */
1060 static void es1371_handle_midi(struct es1371_state *s)
1061 {
1062 unsigned char ch;
1063 int wake;
1064
1065 if (!(s->ctrl & CTRL_UART_EN))
1066 return;
1067 wake = 0;
1068 while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) {
1069 ch = inb(s->io+ES1371_REG_UART_DATA);
1070 if (s->midi.icnt < MIDIINBUF) {
1071 s->midi.ibuf[s->midi.iwr] = ch;
1072 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1073 s->midi.icnt++;
1074 }
1075 wake = 1;
1076 }
1077 if (wake)
1078 wake_up(&s->midi.iwait);
1079 wake = 0;
1080 while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) {
1081 outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA);
1082 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1083 s->midi.ocnt--;
1084 if (s->midi.ocnt < MIDIOUTBUF-16)
1085 wake = 1;
1086 }
1087 if (wake)
1088 wake_up(&s->midi.owait);
1089 outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL);
1090 }
1091
1092 static void es1371_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1093 {
1094 struct es1371_state *s = (struct es1371_state *)dev_id;
1095 unsigned int intsrc, sctl;
1096
1097 /* fastpath out, to ease interrupt sharing */
1098 intsrc = inl(s->io+ES1371_REG_STATUS);
1099 if (!(intsrc & 0x80000000))
1100 return;
1101 spin_lock(&s->lock);
1102 /* clear audio interrupts first */
1103 sctl = s->sctrl;
1104 if (intsrc & STAT_ADC)
1105 sctl &= ~SCTRL_R1INTEN;
1106 if (intsrc & STAT_DAC1)
1107 sctl &= ~SCTRL_P1INTEN;
1108 if (intsrc & STAT_DAC2)
1109 sctl &= ~SCTRL_P2INTEN;
1110 outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL);
1111 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1112 es1371_update_ptr(s);
1113 es1371_handle_midi(s);
1114 spin_unlock(&s->lock);
1115 }
1116
1117 /* --------------------------------------------------------------------- */
1118
1119 static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
1120
1121 #define VALIDATE_STATE(s) \
1122 ({ \
1123 if (!(s) || (s)->magic != ES1371_MAGIC) { \
1124 printk(invalid_magic); \
1125 return -ENXIO; \
1126 } \
1127 })
1128
1129 /* --------------------------------------------------------------------- */
1130
1131 static loff_t es1371_llseek(struct file *file, loff_t offset, int origin)
1132 {
1133 return -ESPIPE;
1134 }
1135
1136 /* --------------------------------------------------------------------- */
1137
1138 /*
1139 * AC97 Mixer Register to Connections mapping of the Concert 97 board
1140 *
1141 * AC97_MASTER_VOL_STEREO Line Out
1142 * AC97_MASTER_VOL_MONO TAD Output
1143 * AC97_PCBEEP_VOL none
1144 * AC97_PHONE_VOL TAD Input (mono)
1145 * AC97_MIC_VOL MIC Input (mono)
1146 * AC97_LINEIN_VOL Line Input (stereo)
1147 * AC97_CD_VOL CD Input (stereo)
1148 * AC97_VIDEO_VOL none
1149 * AC97_AUX_VOL Aux Input (stereo)
1150 * AC97_PCMOUT_VOL Wave Output (stereo)
1151 */
1152
1153 static int es1371_open_mixdev(struct inode *inode, struct file *file)
1154 {
1155 int minor = MINOR(inode->i_rdev);
1156 struct list_head *list;
1157 struct es1371_state *s;
1158
1159 for (list = devs.next; ; list = list->next) {
1160 if (list == &devs)
1161 return -ENODEV;
1162 s = list_entry(list, struct es1371_state, devs);
1163 if (s->codec.dev_mixer == minor)
1164 break;
1165 }
1166 VALIDATE_STATE(s);
1167 file->private_data = s;
1168 MOD_INC_USE_COUNT;
1169 return 0;
1170 }
1171
1172 static int es1371_release_mixdev(struct inode *inode, struct file *file)
1173 {
1174 struct es1371_state *s = (struct es1371_state *)file->private_data;
1175
1176 VALIDATE_STATE(s);
1177 MOD_DEC_USE_COUNT;
1178 return 0;
1179 }
1180
1181 static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1182 {
1183 struct ac97_codec *codec = &((struct es1371_state *)file->private_data)->codec;
1184 return codec->mixer_ioctl(codec, cmd, arg);
1185 }
1186
1187 static /*const*/ struct file_operations es1371_mixer_fops = {
1188 llseek: es1371_llseek,
1189 ioctl: es1371_ioctl_mixdev,
1190 open: es1371_open_mixdev,
1191 release: es1371_release_mixdev,
1192 };
1193
1194 /* --------------------------------------------------------------------- */
1195
1196 static int drain_dac1(struct es1371_state *s, int nonblock)
1197 {
1198 DECLARE_WAITQUEUE(wait, current);
1199 unsigned long flags;
1200 int count, tmo;
1201
1202 if (s->dma_dac1.mapped || !s->dma_dac1.ready)
1203 return 0;
1204 add_wait_queue(&s->dma_dac1.wait, &wait);
1205 for (;;) {
1206 __set_current_state(TASK_INTERRUPTIBLE);
1207 spin_lock_irqsave(&s->lock, flags);
1208 count = s->dma_dac1.count;
1209 spin_unlock_irqrestore(&s->lock, flags);
1210 if (count <= 0)
1211 break;
1212 if (signal_pending(current))
1213 break;
1214 if (nonblock) {
1215 remove_wait_queue(&s->dma_dac1.wait, &wait);
1216 set_current_state(TASK_RUNNING);
1217 return -EBUSY;
1218 }
1219 tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate;
1220 tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
1221 if (!schedule_timeout(tmo + 1))
1222 DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");)
1223 }
1224 remove_wait_queue(&s->dma_dac1.wait, &wait);
1225 set_current_state(TASK_RUNNING);
1226 if (signal_pending(current))
1227 return -ERESTARTSYS;
1228 return 0;
1229 }
1230
1231 static int drain_dac2(struct es1371_state *s, int nonblock)
1232 {
1233 DECLARE_WAITQUEUE(wait, current);
1234 unsigned long flags;
1235 int count, tmo;
1236
1237 if (s->dma_dac2.mapped || !s->dma_dac2.ready)
1238 return 0;
1239 add_wait_queue(&s->dma_dac2.wait, &wait);
1240 for (;;) {
1241 __set_current_state(TASK_UNINTERRUPTIBLE);
1242 spin_lock_irqsave(&s->lock, flags);
1243 count = s->dma_dac2.count;
1244 spin_unlock_irqrestore(&s->lock, flags);
1245 if (count <= 0)
1246 break;
1247 if (signal_pending(current))
1248 break;
1249 if (nonblock) {
1250 remove_wait_queue(&s->dma_dac2.wait, &wait);
1251 set_current_state(TASK_RUNNING);
1252 return -EBUSY;
1253 }
1254 tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate;
1255 tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
1256 if (!schedule_timeout(tmo + 1))
1257 DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");)
1258 }
1259 remove_wait_queue(&s->dma_dac2.wait, &wait);
1260 set_current_state(TASK_RUNNING);
1261 if (signal_pending(current))
1262 return -ERESTARTSYS;
1263 return 0;
1264 }
1265
1266 /* --------------------------------------------------------------------- */
1267
1268 static ssize_t es1371_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1269 {
1270 struct es1371_state *s = (struct es1371_state *)file->private_data;
1271 DECLARE_WAITQUEUE(wait, current);
1272 ssize_t ret;
1273 unsigned long flags;
1274 unsigned swptr;
1275 int cnt;
1276
1277 VALIDATE_STATE(s);
1278 if (ppos != &file->f_pos)
1279 return -ESPIPE;
1280 if (s->dma_adc.mapped)
1281 return -ENXIO;
1282 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1283 return ret;
1284 if (!access_ok(VERIFY_WRITE, buffer, count))
1285 return -EFAULT;
1286 ret = 0;
1287 add_wait_queue(&s->dma_adc.wait, &wait);
1288 while (count > 0) {
1289 spin_lock_irqsave(&s->lock, flags);
1290 swptr = s->dma_adc.swptr;
1291 cnt = s->dma_adc.dmasize-swptr;
1292 if (s->dma_adc.count < cnt)
1293 cnt = s->dma_adc.count;
1294 if (cnt <= 0)
1295 __set_current_state(TASK_INTERRUPTIBLE);
1296 spin_unlock_irqrestore(&s->lock, flags);
1297 if (cnt > count)
1298 cnt = count;
1299 if (cnt <= 0) {
1300 start_adc(s);
1301 if (file->f_flags & O_NONBLOCK) {
1302 if (!ret)
1303 ret = -EAGAIN;
1304 break;
1305 }
1306 schedule();
1307 if (signal_pending(current)) {
1308 if (!ret)
1309 ret = -ERESTARTSYS;
1310 break;
1311 }
1312 continue;
1313 }
1314 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1315 if (!ret)
1316 ret = -EFAULT;
1317 break;
1318 }
1319 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1320 spin_lock_irqsave(&s->lock, flags);
1321 s->dma_adc.swptr = swptr;
1322 s->dma_adc.count -= cnt;
1323 spin_unlock_irqrestore(&s->lock, flags);
1324 count -= cnt;
1325 buffer += cnt;
1326 ret += cnt;
1327 start_adc(s);
1328 }
1329 remove_wait_queue(&s->dma_adc.wait, &wait);
1330 set_current_state(TASK_RUNNING);
1331 return ret;
1332 }
1333
1334 static ssize_t es1371_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1335 {
1336 struct es1371_state *s = (struct es1371_state *)file->private_data;
1337 DECLARE_WAITQUEUE(wait, current);
1338 ssize_t ret;
1339 unsigned long flags;
1340 unsigned swptr;
1341 int cnt;
1342
1343 VALIDATE_STATE(s);
1344 if (ppos != &file->f_pos)
1345 return -ESPIPE;
1346 if (s->dma_dac2.mapped)
1347 return -ENXIO;
1348 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1349 return ret;
1350 if (!access_ok(VERIFY_READ, buffer, count))
1351 return -EFAULT;
1352 ret = 0;
1353 add_wait_queue(&s->dma_dac2.wait, &wait);
1354 while (count > 0) {
1355 spin_lock_irqsave(&s->lock, flags);
1356 if (s->dma_dac2.count < 0) {
1357 s->dma_dac2.count = 0;
1358 s->dma_dac2.swptr = s->dma_dac2.hwptr;
1359 }
1360 swptr = s->dma_dac2.swptr;
1361 cnt = s->dma_dac2.dmasize-swptr;
1362 if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize)
1363 cnt = s->dma_dac2.dmasize - s->dma_dac2.count;
1364 if (cnt <= 0)
1365 __set_current_state(TASK_INTERRUPTIBLE);
1366 spin_unlock_irqrestore(&s->lock, flags);
1367 if (cnt > count)
1368 cnt = count;
1369 if (cnt <= 0) {
1370 start_dac2(s);
1371 if (file->f_flags & O_NONBLOCK) {
1372 if (!ret)
1373 ret = -EAGAIN;
1374 break;
1375 }
1376 schedule();
1377 if (signal_pending(current)) {
1378 if (!ret)
1379 ret = -ERESTARTSYS;
1380 break;
1381 }
1382 continue;
1383 }
1384 if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) {
1385 if (!ret)
1386 ret = -EFAULT;
1387 break;
1388 }
1389 swptr = (swptr + cnt) % s->dma_dac2.dmasize;
1390 spin_lock_irqsave(&s->lock, flags);
1391 s->dma_dac2.swptr = swptr;
1392 s->dma_dac2.count += cnt;
1393 s->dma_dac2.endcleared = 0;
1394 spin_unlock_irqrestore(&s->lock, flags);
1395 count -= cnt;
1396 buffer += cnt;
1397 ret += cnt;
1398 start_dac2(s);
1399 }
1400 remove_wait_queue(&s->dma_dac2.wait, &wait);
1401 set_current_state(TASK_RUNNING);
1402 return ret;
1403 }
1404
1405 static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait)
1406 {
1407 struct es1371_state *s = (struct es1371_state *)file->private_data;
1408 unsigned long flags;
1409 unsigned int mask = 0;
1410
1411 VALIDATE_STATE(s);
1412 if (file->f_mode & FMODE_WRITE)
1413 poll_wait(file, &s->dma_dac2.wait, wait);
1414 if (file->f_mode & FMODE_READ)
1415 poll_wait(file, &s->dma_adc.wait, wait);
1416 spin_lock_irqsave(&s->lock, flags);
1417 es1371_update_ptr(s);
1418 if (file->f_mode & FMODE_READ) {
1419 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1420 mask |= POLLIN | POLLRDNORM;
1421 }
1422 if (file->f_mode & FMODE_WRITE) {
1423 if (s->dma_dac2.mapped) {
1424 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1425 mask |= POLLOUT | POLLWRNORM;
1426 } else {
1427 if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize)
1428 mask |= POLLOUT | POLLWRNORM;
1429 }
1430 }
1431 spin_unlock_irqrestore(&s->lock, flags);
1432 return mask;
1433 }
1434
1435 static int es1371_mmap(struct file *file, struct vm_area_struct *vma)
1436 {
1437 struct es1371_state *s = (struct es1371_state *)file->private_data;
1438 struct dmabuf *db;
1439 int ret;
1440 unsigned long size;
1441
1442 VALIDATE_STATE(s);
1443 if (vma->vm_flags & VM_WRITE) {
1444 if ((ret = prog_dmabuf_dac2(s)) != 0)
1445 return ret;
1446 db = &s->dma_dac2;
1447 } else if (vma->vm_flags & VM_READ) {
1448 if ((ret = prog_dmabuf_adc(s)) != 0)
1449 return ret;
1450 db = &s->dma_adc;
1451 } else
1452 return -EINVAL;
1453 if (vma->vm_pgoff != 0)
1454 return -EINVAL;
1455 size = vma->vm_end - vma->vm_start;
1456 if (size > (PAGE_SIZE << db->buforder))
1457 return -EINVAL;
1458 if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
1459 return -EAGAIN;
1460 db->mapped = 1;
1461 return 0;
1462 }
1463
1464 static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1465 {
1466 struct es1371_state *s = (struct es1371_state *)file->private_data;
1467 unsigned long flags;
1468 audio_buf_info abinfo;
1469 count_info cinfo;
1470 int count;
1471 int val, mapped, ret;
1472
1473 VALIDATE_STATE(s);
1474 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) ||
1475 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1476 switch (cmd) {
1477 case OSS_GETVERSION:
1478 return put_user(SOUND_VERSION, (int *)arg);
1479
1480 case SNDCTL_DSP_SYNC:
1481 if (file->f_mode & FMODE_WRITE)
1482 return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/);
1483 return 0;
1484
1485 case SNDCTL_DSP_SETDUPLEX:
1486 return 0;
1487
1488 case SNDCTL_DSP_GETCAPS:
1489 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1490
1491 case SNDCTL_DSP_RESET:
1492 if (file->f_mode & FMODE_WRITE) {
1493 stop_dac2(s);
1494 synchronize_irq();
1495 s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0;
1496 }
1497 if (file->f_mode & FMODE_READ) {
1498 stop_adc(s);
1499 synchronize_irq();
1500 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1501 }
1502 return 0;
1503
1504 case SNDCTL_DSP_SPEED:
1505 get_user_ret(val, (int *)arg, -EFAULT);
1506 if (val >= 0) {
1507 if (file->f_mode & FMODE_READ) {
1508 stop_adc(s);
1509 s->dma_adc.ready = 0;
1510 set_adc_rate(s, val);
1511 }
1512 if (file->f_mode & FMODE_WRITE) {
1513 stop_dac2(s);
1514 s->dma_dac2.ready = 0;
1515 set_dac2_rate(s, val);
1516 }
1517 }
1518 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, (int *)arg);
1519
1520 case SNDCTL_DSP_STEREO:
1521 get_user_ret(val, (int *)arg, -EFAULT);
1522 if (file->f_mode & FMODE_READ) {
1523 stop_adc(s);
1524 s->dma_adc.ready = 0;
1525 spin_lock_irqsave(&s->lock, flags);
1526 if (val)
1527 s->sctrl |= SCTRL_R1SMB;
1528 else
1529 s->sctrl &= ~SCTRL_R1SMB;
1530 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1531 spin_unlock_irqrestore(&s->lock, flags);
1532 }
1533 if (file->f_mode & FMODE_WRITE) {
1534 stop_dac2(s);
1535 s->dma_dac2.ready = 0;
1536 spin_lock_irqsave(&s->lock, flags);
1537 if (val)
1538 s->sctrl |= SCTRL_P2SMB;
1539 else
1540 s->sctrl &= ~SCTRL_P2SMB;
1541 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1542 spin_unlock_irqrestore(&s->lock, flags);
1543 }
1544 return 0;
1545
1546 case SNDCTL_DSP_CHANNELS:
1547 get_user_ret(val, (int *)arg, -EFAULT);
1548 if (val != 0) {
1549 if (file->f_mode & FMODE_READ) {
1550 stop_adc(s);
1551 s->dma_adc.ready = 0;
1552 spin_lock_irqsave(&s->lock, flags);
1553 if (val >= 2)
1554 s->sctrl |= SCTRL_R1SMB;
1555 else
1556 s->sctrl &= ~SCTRL_R1SMB;
1557 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1558 spin_unlock_irqrestore(&s->lock, flags);
1559 }
1560 if (file->f_mode & FMODE_WRITE) {
1561 stop_dac2(s);
1562 s->dma_dac2.ready = 0;
1563 spin_lock_irqsave(&s->lock, flags);
1564 if (val >= 2)
1565 s->sctrl |= SCTRL_P2SMB;
1566 else
1567 s->sctrl &= ~SCTRL_P2SMB;
1568 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1569 spin_unlock_irqrestore(&s->lock, flags);
1570 }
1571 }
1572 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, (int *)arg);
1573
1574 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1575 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
1576
1577 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1578 get_user_ret(val, (int *)arg, -EFAULT);
1579 if (val != AFMT_QUERY) {
1580 if (file->f_mode & FMODE_READ) {
1581 stop_adc(s);
1582 s->dma_adc.ready = 0;
1583 spin_lock_irqsave(&s->lock, flags);
1584 if (val == AFMT_S16_LE)
1585 s->sctrl |= SCTRL_R1SEB;
1586 else
1587 s->sctrl &= ~SCTRL_R1SEB;
1588 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1589 spin_unlock_irqrestore(&s->lock, flags);
1590 }
1591 if (file->f_mode & FMODE_WRITE) {
1592 stop_dac2(s);
1593 s->dma_dac2.ready = 0;
1594 spin_lock_irqsave(&s->lock, flags);
1595 if (val == AFMT_S16_LE)
1596 s->sctrl |= SCTRL_P2SEB;
1597 else
1598 s->sctrl &= ~SCTRL_P2SEB;
1599 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1600 spin_unlock_irqrestore(&s->lock, flags);
1601 }
1602 }
1603 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ?
1604 AFMT_S16_LE : AFMT_U8, (int *)arg);
1605
1606 case SNDCTL_DSP_POST:
1607 return 0;
1608
1609 case SNDCTL_DSP_GETTRIGGER:
1610 val = 0;
1611 if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN)
1612 val |= PCM_ENABLE_INPUT;
1613 if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN)
1614 val |= PCM_ENABLE_OUTPUT;
1615 return put_user(val, (int *)arg);
1616
1617 case SNDCTL_DSP_SETTRIGGER:
1618 get_user_ret(val, (int *)arg, -EFAULT);
1619 if (file->f_mode & FMODE_READ) {
1620 if (val & PCM_ENABLE_INPUT) {
1621 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1622 return ret;
1623 start_adc(s);
1624 } else
1625 stop_adc(s);
1626 }
1627 if (file->f_mode & FMODE_WRITE) {
1628 if (val & PCM_ENABLE_OUTPUT) {
1629 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1630 return ret;
1631 start_dac2(s);
1632 } else
1633 stop_dac2(s);
1634 }
1635 return 0;
1636
1637 case SNDCTL_DSP_GETOSPACE:
1638 if (!(file->f_mode & FMODE_WRITE))
1639 return -EINVAL;
1640 if (!(s->ctrl & CTRL_DAC2_EN) && (val = prog_dmabuf_dac2(s)) != 0)
1641 return val;
1642 spin_lock_irqsave(&s->lock, flags);
1643 es1371_update_ptr(s);
1644 abinfo.fragsize = s->dma_dac2.fragsize;
1645 count = s->dma_dac2.count;
1646 if (count < 0)
1647 count = 0;
1648 abinfo.bytes = s->dma_dac2.dmasize - count;
1649 abinfo.fragstotal = s->dma_dac2.numfrag;
1650 abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift;
1651 spin_unlock_irqrestore(&s->lock, flags);
1652 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1653
1654 case SNDCTL_DSP_GETISPACE:
1655 if (!(file->f_mode & FMODE_READ))
1656 return -EINVAL;
1657 if (!(s->ctrl & CTRL_ADC_EN) && (val = prog_dmabuf_adc(s)) != 0)
1658 return val;
1659 spin_lock_irqsave(&s->lock, flags);
1660 es1371_update_ptr(s);
1661 abinfo.fragsize = s->dma_adc.fragsize;
1662 count = s->dma_adc.count;
1663 if (count < 0)
1664 count = 0;
1665 abinfo.bytes = count;
1666 abinfo.fragstotal = s->dma_adc.numfrag;
1667 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1668 spin_unlock_irqrestore(&s->lock, flags);
1669 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1670
1671 case SNDCTL_DSP_NONBLOCK:
1672 file->f_flags |= O_NONBLOCK;
1673 return 0;
1674
1675 case SNDCTL_DSP_GETODELAY:
1676 if (!(file->f_mode & FMODE_WRITE))
1677 return -EINVAL;
1678 spin_lock_irqsave(&s->lock, flags);
1679 es1371_update_ptr(s);
1680 count = s->dma_dac2.count;
1681 spin_unlock_irqrestore(&s->lock, flags);
1682 if (count < 0)
1683 count = 0;
1684 return put_user(count, (int *)arg);
1685
1686 case SNDCTL_DSP_GETIPTR:
1687 if (!(file->f_mode & FMODE_READ))
1688 return -EINVAL;
1689 spin_lock_irqsave(&s->lock, flags);
1690 es1371_update_ptr(s);
1691 cinfo.bytes = s->dma_adc.total_bytes;
1692 count = s->dma_adc.count;
1693 if (count < 0)
1694 count = 0;
1695 cinfo.blocks = count >> s->dma_adc.fragshift;
1696 cinfo.ptr = s->dma_adc.hwptr;
1697 if (s->dma_adc.mapped)
1698 s->dma_adc.count &= s->dma_adc.fragsize-1;
1699 spin_unlock_irqrestore(&s->lock, flags);
1700 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1701
1702 case SNDCTL_DSP_GETOPTR:
1703 if (!(file->f_mode & FMODE_WRITE))
1704 return -EINVAL;
1705 spin_lock_irqsave(&s->lock, flags);
1706 es1371_update_ptr(s);
1707 cinfo.bytes = s->dma_dac2.total_bytes;
1708 count = s->dma_dac2.count;
1709 if (count < 0)
1710 count = 0;
1711 cinfo.blocks = count >> s->dma_dac2.fragshift;
1712 cinfo.ptr = s->dma_dac2.hwptr;
1713 if (s->dma_dac2.mapped)
1714 s->dma_dac2.count &= s->dma_dac2.fragsize-1;
1715 spin_unlock_irqrestore(&s->lock, flags);
1716 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1717
1718 case SNDCTL_DSP_GETBLKSIZE:
1719 if (file->f_mode & FMODE_WRITE) {
1720 if ((val = prog_dmabuf_dac2(s)))
1721 return val;
1722 return put_user(s->dma_dac2.fragsize, (int *)arg);
1723 }
1724 if ((val = prog_dmabuf_adc(s)))
1725 return val;
1726 return put_user(s->dma_adc.fragsize, (int *)arg);
1727
1728 case SNDCTL_DSP_SETFRAGMENT:
1729 get_user_ret(val, (int *)arg, -EFAULT);
1730 if (file->f_mode & FMODE_READ) {
1731 s->dma_adc.ossfragshift = val & 0xffff;
1732 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1733 if (s->dma_adc.ossfragshift < 4)
1734 s->dma_adc.ossfragshift = 4;
1735 if (s->dma_adc.ossfragshift > 15)
1736 s->dma_adc.ossfragshift = 15;
1737 if (s->dma_adc.ossmaxfrags < 4)
1738 s->dma_adc.ossmaxfrags = 4;
1739 }
1740 if (file->f_mode & FMODE_WRITE) {
1741 s->dma_dac2.ossfragshift = val & 0xffff;
1742 s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff;
1743 if (s->dma_dac2.ossfragshift < 4)
1744 s->dma_dac2.ossfragshift = 4;
1745 if (s->dma_dac2.ossfragshift > 15)
1746 s->dma_dac2.ossfragshift = 15;
1747 if (s->dma_dac2.ossmaxfrags < 4)
1748 s->dma_dac2.ossmaxfrags = 4;
1749 }
1750 return 0;
1751
1752 case SNDCTL_DSP_SUBDIVIDE:
1753 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1754 (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision))
1755 return -EINVAL;
1756 get_user_ret(val, (int *)arg, -EFAULT);
1757 if (val != 1 && val != 2 && val != 4)
1758 return -EINVAL;
1759 if (file->f_mode & FMODE_READ)
1760 s->dma_adc.subdivision = val;
1761 if (file->f_mode & FMODE_WRITE)
1762 s->dma_dac2.subdivision = val;
1763 return 0;
1764
1765 case SOUND_PCM_READ_RATE:
1766 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, (int *)arg);
1767
1768 case SOUND_PCM_READ_CHANNELS:
1769 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, (int *)arg);
1770
1771 case SOUND_PCM_READ_BITS:
1772 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, (int *)arg);
1773
1774 case SOUND_PCM_WRITE_FILTER:
1775 case SNDCTL_DSP_SETSYNCRO:
1776 case SOUND_PCM_READ_FILTER:
1777 return -EINVAL;
1778
1779 }
1780 return s->codec.mixer_ioctl(&s->codec, cmd, arg);
1781 }
1782
1783 static int es1371_open(struct inode *inode, struct file *file)
1784 {
1785 int minor = MINOR(inode->i_rdev);
1786 DECLARE_WAITQUEUE(wait, current);
1787 unsigned long flags;
1788 struct list_head *list;
1789 struct es1371_state *s;
1790
1791 for (list = devs.next; ; list = list->next) {
1792 if (list == &devs)
1793 return -ENODEV;
1794 s = list_entry(list, struct es1371_state, devs);
1795 if (!((s->dev_audio ^ minor) & ~0xf))
1796 break;
1797 }
1798 VALIDATE_STATE(s);
1799 file->private_data = s;
1800 /* wait for device to become free */
1801 down(&s->open_sem);
1802 while (s->open_mode & file->f_mode) {
1803 if (file->f_flags & O_NONBLOCK) {
1804 up(&s->open_sem);
1805 return -EBUSY;
1806 }
1807 add_wait_queue(&s->open_wait, &wait);
1808 __set_current_state(TASK_INTERRUPTIBLE);
1809 up(&s->open_sem);
1810 schedule();
1811 remove_wait_queue(&s->open_wait, &wait);
1812 set_current_state(TASK_RUNNING);
1813 if (signal_pending(current))
1814 return -ERESTARTSYS;
1815 down(&s->open_sem);
1816 }
1817 if (file->f_mode & FMODE_READ) {
1818 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1819 set_adc_rate(s, 8000);
1820 }
1821 if (file->f_mode & FMODE_WRITE) {
1822 s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0;
1823 set_dac2_rate(s, 8000);
1824 }
1825 spin_lock_irqsave(&s->lock, flags);
1826 if (file->f_mode & FMODE_READ) {
1827 s->sctrl &= ~SCTRL_R1FMT;
1828 if ((minor & 0xf) == SND_DEV_DSP16)
1829 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT;
1830 else
1831 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT;
1832 }
1833 if (file->f_mode & FMODE_WRITE) {
1834 s->sctrl &= ~SCTRL_P2FMT;
1835 if ((minor & 0xf) == SND_DEV_DSP16)
1836 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT;
1837 else
1838 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT;
1839 }
1840 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1841 spin_unlock_irqrestore(&s->lock, flags);
1842 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1843 up(&s->open_sem);
1844 MOD_INC_USE_COUNT;
1845 return 0;
1846 }
1847
1848 static int es1371_release(struct inode *inode, struct file *file)
1849 {
1850 struct es1371_state *s = (struct es1371_state *)file->private_data;
1851
1852 VALIDATE_STATE(s);
1853 if (file->f_mode & FMODE_WRITE)
1854 drain_dac2(s, file->f_flags & O_NONBLOCK);
1855 down(&s->open_sem);
1856 if (file->f_mode & FMODE_WRITE) {
1857 stop_dac2(s);
1858 dealloc_dmabuf(s, &s->dma_dac2);
1859 }
1860 if (file->f_mode & FMODE_READ) {
1861 stop_adc(s);
1862 dealloc_dmabuf(s, &s->dma_adc);
1863 }
1864 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
1865 up(&s->open_sem);
1866 wake_up(&s->open_wait);
1867 MOD_DEC_USE_COUNT;
1868 return 0;
1869 }
1870
1871 static /*const*/ struct file_operations es1371_audio_fops = {
1872 llseek: es1371_llseek,
1873 read: es1371_read,
1874 write: es1371_write,
1875 poll: es1371_poll,
1876 ioctl: es1371_ioctl,
1877 mmap: es1371_mmap,
1878 open: es1371_open,
1879 release: es1371_release,
1880 };
1881
1882 /* --------------------------------------------------------------------- */
1883
1884 static ssize_t es1371_write_dac(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1885 {
1886 struct es1371_state *s = (struct es1371_state *)file->private_data;
1887 DECLARE_WAITQUEUE(wait, current);
1888 ssize_t ret = 0;
1889 unsigned long flags;
1890 unsigned swptr;
1891 int cnt;
1892
1893 VALIDATE_STATE(s);
1894 if (ppos != &file->f_pos)
1895 return -ESPIPE;
1896 if (s->dma_dac1.mapped)
1897 return -ENXIO;
1898 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
1899 return ret;
1900 if (!access_ok(VERIFY_READ, buffer, count))
1901 return -EFAULT;
1902 add_wait_queue(&s->dma_dac1.wait, &wait);
1903 while (count > 0) {
1904 spin_lock_irqsave(&s->lock, flags);
1905 if (s->dma_dac1.count < 0) {
1906 s->dma_dac1.count = 0;
1907 s->dma_dac1.swptr = s->dma_dac1.hwptr;
1908 }
1909 swptr = s->dma_dac1.swptr;
1910 cnt = s->dma_dac1.dmasize-swptr;
1911 if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize)
1912 cnt = s->dma_dac1.dmasize - s->dma_dac1.count;
1913 if (cnt <= 0)
1914 __set_current_state(TASK_INTERRUPTIBLE);
1915 spin_unlock_irqrestore(&s->lock, flags);
1916 if (cnt > count)
1917 cnt = count;
1918 if (cnt <= 0) {
1919 start_dac1(s);
1920 if (file->f_flags & O_NONBLOCK) {
1921 if (!ret)
1922 ret = -EAGAIN;
1923 break;
1924 }
1925 schedule();
1926 if (signal_pending(current)) {
1927 if (!ret)
1928 ret = -ERESTARTSYS;
1929 break;
1930 }
1931 continue;
1932 }
1933 if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) {
1934 if (!ret)
1935 ret = -EFAULT;
1936 break;
1937 }
1938 swptr = (swptr + cnt) % s->dma_dac1.dmasize;
1939 spin_lock_irqsave(&s->lock, flags);
1940 s->dma_dac1.swptr = swptr;
1941 s->dma_dac1.count += cnt;
1942 s->dma_dac1.endcleared = 0;
1943 spin_unlock_irqrestore(&s->lock, flags);
1944 count -= cnt;
1945 buffer += cnt;
1946 ret += cnt;
1947 start_dac1(s);
1948 }
1949 remove_wait_queue(&s->dma_dac1.wait, &wait);
1950 set_current_state(TASK_RUNNING);
1951 return ret;
1952 }
1953
1954 static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait)
1955 {
1956 struct es1371_state *s = (struct es1371_state *)file->private_data;
1957 unsigned long flags;
1958 unsigned int mask = 0;
1959
1960 VALIDATE_STATE(s);
1961 poll_wait(file, &s->dma_dac1.wait, wait);
1962 spin_lock_irqsave(&s->lock, flags);
1963 es1371_update_ptr(s);
1964 if (s->dma_dac1.mapped) {
1965 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
1966 mask |= POLLOUT | POLLWRNORM;
1967 } else {
1968 if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize)
1969 mask |= POLLOUT | POLLWRNORM;
1970 }
1971 spin_unlock_irqrestore(&s->lock, flags);
1972 return mask;
1973 }
1974
1975 static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma)
1976 {
1977 struct es1371_state *s = (struct es1371_state *)file->private_data;
1978 int ret;
1979 unsigned long size;
1980
1981 VALIDATE_STATE(s);
1982 if (!(vma->vm_flags & VM_WRITE))
1983 return -EINVAL;
1984 if ((ret = prog_dmabuf_dac1(s)) != 0)
1985 return ret;
1986 if (vma->vm_pgoff != 0)
1987 return -EINVAL;
1988 size = vma->vm_end - vma->vm_start;
1989 if (size > (PAGE_SIZE << s->dma_dac1.buforder))
1990 return -EINVAL;
1991 if (remap_page_range(vma->vm_start, virt_to_phys(s->dma_dac1.rawbuf), size, vma->vm_page_prot))
1992 return -EAGAIN;
1993 s->dma_dac1.mapped = 1;
1994 return 0;
1995 }
1996
1997 static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1998 {
1999 struct es1371_state *s = (struct es1371_state *)file->private_data;
2000 unsigned long flags;
2001 audio_buf_info abinfo;
2002 count_info cinfo;
2003 int count;
2004 int val, ret;
2005
2006 VALIDATE_STATE(s);
2007 switch (cmd) {
2008 case OSS_GETVERSION:
2009 return put_user(SOUND_VERSION, (int *)arg);
2010
2011 case SNDCTL_DSP_SYNC:
2012 return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/);
2013
2014 case SNDCTL_DSP_SETDUPLEX:
2015 return -EINVAL;
2016
2017 case SNDCTL_DSP_GETCAPS:
2018 return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
2019
2020 case SNDCTL_DSP_RESET:
2021 stop_dac1(s);
2022 synchronize_irq();
2023 s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0;
2024 return 0;
2025
2026 case SNDCTL_DSP_SPEED:
2027 get_user_ret(val, (int *)arg, -EFAULT);
2028 if (val >= 0) {
2029 stop_dac1(s);
2030 s->dma_dac1.ready = 0;
2031 set_dac1_rate(s, val);
2032 }
2033 return put_user(s->dac1rate, (int *)arg);
2034
2035 case SNDCTL_DSP_STEREO:
2036 get_user_ret(val, (int *)arg, -EFAULT);
2037 stop_dac1(s);
2038 s->dma_dac1.ready = 0;
2039 spin_lock_irqsave(&s->lock, flags);
2040 if (val)
2041 s->sctrl |= SCTRL_P1SMB;
2042 else
2043 s->sctrl &= ~SCTRL_P1SMB;
2044 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2045 spin_unlock_irqrestore(&s->lock, flags);
2046 return 0;
2047
2048 case SNDCTL_DSP_CHANNELS:
2049 get_user_ret(val, (int *)arg, -EFAULT);
2050 if (val != 0) {
2051 stop_dac1(s);
2052 s->dma_dac1.ready = 0;
2053 spin_lock_irqsave(&s->lock, flags);
2054 if (val >= 2)
2055 s->sctrl |= SCTRL_P1SMB;
2056 else
2057 s->sctrl &= ~SCTRL_P1SMB;
2058 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2059 spin_unlock_irqrestore(&s->lock, flags);
2060 }
2061 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, (int *)arg);
2062
2063 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2064 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
2065
2066 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2067 get_user_ret(val, (int *)arg, -EFAULT);
2068 if (val != AFMT_QUERY) {
2069 stop_dac1(s);
2070 s->dma_dac1.ready = 0;
2071 spin_lock_irqsave(&s->lock, flags);
2072 if (val == AFMT_S16_LE)
2073 s->sctrl |= SCTRL_P1SEB;
2074 else
2075 s->sctrl &= ~SCTRL_P1SEB;
2076 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2077 spin_unlock_irqrestore(&s->lock, flags);
2078 }
2079 return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, (int *)arg);
2080
2081 case SNDCTL_DSP_POST:
2082 return 0;
2083
2084 case SNDCTL_DSP_GETTRIGGER:
2085 return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, (int *)arg);
2086
2087 case SNDCTL_DSP_SETTRIGGER:
2088 get_user_ret(val, (int *)arg, -EFAULT);
2089 if (val & PCM_ENABLE_OUTPUT) {
2090 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2091 return ret;
2092 start_dac1(s);
2093 } else
2094 stop_dac1(s);
2095 return 0;
2096
2097 case SNDCTL_DSP_GETOSPACE:
2098 if (!(s->ctrl & CTRL_DAC2_EN) && (val = prog_dmabuf_dac1(s)) != 0)
2099 return val;
2100 spin_lock_irqsave(&s->lock, flags);
2101 es1371_update_ptr(s);
2102 abinfo.fragsize = s->dma_dac1.fragsize;
2103 count = s->dma_dac1.count;
2104 if (count < 0)
2105 count = 0;
2106 abinfo.bytes = s->dma_dac1.dmasize - count;
2107 abinfo.fragstotal = s->dma_dac1.numfrag;
2108 abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift;
2109 spin_unlock_irqrestore(&s->lock, flags);
2110 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2111
2112 case SNDCTL_DSP_NONBLOCK:
2113 file->f_flags |= O_NONBLOCK;
2114 return 0;
2115
2116 case SNDCTL_DSP_GETODELAY:
2117 spin_lock_irqsave(&s->lock, flags);
2118 es1371_update_ptr(s);
2119 count = s->dma_dac1.count;
2120 spin_unlock_irqrestore(&s->lock, flags);
2121 if (count < 0)
2122 count = 0;
2123 return put_user(count, (int *)arg);
2124
2125 case SNDCTL_DSP_GETOPTR:
2126 if (!(file->f_mode & FMODE_WRITE))
2127 return -EINVAL;
2128 spin_lock_irqsave(&s->lock, flags);
2129 es1371_update_ptr(s);
2130 cinfo.bytes = s->dma_dac1.total_bytes;
2131 count = s->dma_dac1.count;
2132 if (count < 0)
2133 count = 0;
2134 cinfo.blocks = count >> s->dma_dac1.fragshift;
2135 cinfo.ptr = s->dma_dac1.hwptr;
2136 if (s->dma_dac1.mapped)
2137 s->dma_dac1.count &= s->dma_dac1.fragsize-1;
2138 spin_unlock_irqrestore(&s->lock, flags);
2139 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
2140
2141 case SNDCTL_DSP_GETBLKSIZE:
2142 if ((val = prog_dmabuf_dac1(s)))
2143 return val;
2144 return put_user(s->dma_dac1.fragsize, (int *)arg);
2145
2146 case SNDCTL_DSP_SETFRAGMENT:
2147 get_user_ret(val, (int *)arg, -EFAULT);
2148 s->dma_dac1.ossfragshift = val & 0xffff;
2149 s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff;
2150 if (s->dma_dac1.ossfragshift < 4)
2151 s->dma_dac1.ossfragshift = 4;
2152 if (s->dma_dac1.ossfragshift > 15)
2153 s->dma_dac1.ossfragshift = 15;
2154 if (s->dma_dac1.ossmaxfrags < 4)
2155 s->dma_dac1.ossmaxfrags = 4;
2156 return 0;
2157
2158 case SNDCTL_DSP_SUBDIVIDE:
2159 if (s->dma_dac1.subdivision)
2160 return -EINVAL;
2161 get_user_ret(val, (int *)arg, -EFAULT);
2162 if (val != 1 && val != 2 && val != 4)
2163 return -EINVAL;
2164 s->dma_dac1.subdivision = val;
2165 return 0;
2166
2167 case SOUND_PCM_READ_RATE:
2168 return put_user(s->dac1rate, (int *)arg);
2169
2170 case SOUND_PCM_READ_CHANNELS:
2171 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, (int *)arg);
2172
2173 case SOUND_PCM_READ_BITS:
2174 return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, (int *)arg);
2175
2176 case SOUND_PCM_WRITE_FILTER:
2177 case SNDCTL_DSP_SETSYNCRO:
2178 case SOUND_PCM_READ_FILTER:
2179 return -EINVAL;
2180
2181 }
2182 return s->codec.mixer_ioctl(&s->codec, cmd, arg);
2183 }
2184
2185 static int es1371_open_dac(struct inode *inode, struct file *file)
2186 {
2187 int minor = MINOR(inode->i_rdev);
2188 DECLARE_WAITQUEUE(wait, current);
2189 unsigned long flags;
2190 struct list_head *list;
2191 struct es1371_state *s;
2192
2193 for (list = devs.next; ; list = list->next) {
2194 if (list == &devs)
2195 return -ENODEV;
2196 s = list_entry(list, struct es1371_state, devs);
2197 if (!((s->dev_dac ^ minor) & ~0xf))
2198 break;
2199 }
2200 VALIDATE_STATE(s);
2201 /* we allow opening with O_RDWR, most programs do it although they will only write */
2202 #if 0
2203 if (file->f_mode & FMODE_READ)
2204 return -EPERM;
2205 #endif
2206 if (!(file->f_mode & FMODE_WRITE))
2207 return -EINVAL;
2208 file->private_data = s;
2209 /* wait for device to become free */
2210 down(&s->open_sem);
2211 while (s->open_mode & FMODE_DAC) {
2212 if (file->f_flags & O_NONBLOCK) {
2213 up(&s->open_sem);
2214 return -EBUSY;
2215 }
2216 add_wait_queue(&s->open_wait, &wait);
2217 __set_current_state(TASK_INTERRUPTIBLE);
2218 up(&s->open_sem);
2219 schedule();
2220 remove_wait_queue(&s->open_wait, &wait);
2221 set_current_state(TASK_RUNNING);
2222 if (signal_pending(current))
2223 return -ERESTARTSYS;
2224 down(&s->open_sem);
2225 }
2226 s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0;
2227 set_dac1_rate(s, 8000);
2228 spin_lock_irqsave(&s->lock, flags);
2229 s->sctrl &= ~SCTRL_P1FMT;
2230 if ((minor & 0xf) == SND_DEV_DSP16)
2231 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT;
2232 else
2233 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT;
2234 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2235 spin_unlock_irqrestore(&s->lock, flags);
2236 s->open_mode |= FMODE_DAC;
2237 up(&s->open_sem);
2238 MOD_INC_USE_COUNT;
2239 return 0;
2240 }
2241
2242 static int es1371_release_dac(struct inode *inode, struct file *file)
2243 {
2244 struct es1371_state *s = (struct es1371_state *)file->private_data;
2245
2246 VALIDATE_STATE(s);
2247 drain_dac1(s, file->f_flags & O_NONBLOCK);
2248 down(&s->open_sem);
2249 stop_dac1(s);
2250 dealloc_dmabuf(s, &s->dma_dac1);
2251 s->open_mode &= ~FMODE_DAC;
2252 up(&s->open_sem);
2253 wake_up(&s->open_wait);
2254 MOD_DEC_USE_COUNT;
2255 return 0;
2256 }
2257
2258 static /*const*/ struct file_operations es1371_dac_fops = {
2259 llseek: es1371_llseek,
2260 write: es1371_write_dac,
2261 poll: es1371_poll_dac,
2262 ioctl: es1371_ioctl_dac,
2263 mmap: es1371_mmap_dac,
2264 open: es1371_open_dac,
2265 release: es1371_release_dac,
2266 };
2267
2268 /* --------------------------------------------------------------------- */
2269
2270 static ssize_t es1371_midi_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
2271 {
2272 struct es1371_state *s = (struct es1371_state *)file->private_data;
2273 DECLARE_WAITQUEUE(wait, current);
2274 ssize_t ret;
2275 unsigned long flags;
2276 unsigned ptr;
2277 int cnt;
2278
2279 VALIDATE_STATE(s);
2280 if (ppos != &file->f_pos)
2281 return -ESPIPE;
2282 if (!access_ok(VERIFY_WRITE, buffer, count))
2283 return -EFAULT;
2284 if (count == 0)
2285 return 0;
2286 ret = 0;
2287 add_wait_queue(&s->midi.iwait, &wait);
2288 while (count > 0) {
2289 spin_lock_irqsave(&s->lock, flags);
2290 ptr = s->midi.ird;
2291 cnt = MIDIINBUF - ptr;
2292 if (s->midi.icnt < cnt)
2293 cnt = s->midi.icnt;
2294 if (cnt <= 0)
2295 __set_current_state(TASK_INTERRUPTIBLE);
2296 spin_unlock_irqrestore(&s->lock, flags);
2297 if (cnt > count)
2298 cnt = count;
2299 if (cnt <= 0) {
2300 if (file->f_flags & O_NONBLOCK) {
2301 if (!ret)
2302 ret = -EAGAIN;
2303 break;
2304 }
2305 schedule();
2306 if (signal_pending(current)) {
2307 if (!ret)
2308 ret = -ERESTARTSYS;
2309 break;
2310 }
2311 continue;
2312 }
2313 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2314 if (!ret)
2315 ret = -EFAULT;
2316 break;
2317 }
2318 ptr = (ptr + cnt) % MIDIINBUF;
2319 spin_lock_irqsave(&s->lock, flags);
2320 s->midi.ird = ptr;
2321 s->midi.icnt -= cnt;
2322 spin_unlock_irqrestore(&s->lock, flags);
2323 count -= cnt;
2324 buffer += cnt;
2325 ret += cnt;
2326 break;
2327 }
2328 __set_current_state(TASK_RUNNING);
2329 remove_wait_queue(&s->midi.iwait, &wait);
2330 return ret;
2331 }
2332
2333 static ssize_t es1371_midi_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
2334 {
2335 struct es1371_state *s = (struct es1371_state *)file->private_data;
2336 DECLARE_WAITQUEUE(wait, current);
2337 ssize_t ret;
2338 unsigned long flags;
2339 unsigned ptr;
2340 int cnt;
2341
2342 VALIDATE_STATE(s);
2343 if (ppos != &file->f_pos)
2344 return -ESPIPE;
2345 if (!access_ok(VERIFY_READ, buffer, count))
2346 return -EFAULT;
2347 if (count == 0)
2348 return 0;
2349 ret = 0;
2350 add_wait_queue(&s->midi.owait, &wait);
2351 while (count > 0) {
2352 spin_lock_irqsave(&s->lock, flags);
2353 ptr = s->midi.owr;
2354 cnt = MIDIOUTBUF - ptr;
2355 if (s->midi.ocnt + cnt > MIDIOUTBUF)
2356 cnt = MIDIOUTBUF - s->midi.ocnt;
2357 if (cnt <= 0) {
2358 __set_current_state(TASK_INTERRUPTIBLE);
2359 es1371_handle_midi(s);
2360 }
2361 spin_unlock_irqrestore(&s->lock, flags);
2362 if (cnt > count)
2363 cnt = count;
2364 if (cnt <= 0) {
2365 if (file->f_flags & O_NONBLOCK) {
2366 if (!ret)
2367 ret = -EAGAIN;
2368 break;
2369 }
2370 schedule();
2371 if (signal_pending(current)) {
2372 if (!ret)
2373 ret = -ERESTARTSYS;
2374 break;
2375 }
2376 continue;
2377 }
2378 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2379 if (!ret)
2380 ret = -EFAULT;
2381 break;
2382 }
2383 ptr = (ptr + cnt) % MIDIOUTBUF;
2384 spin_lock_irqsave(&s->lock, flags);
2385 s->midi.owr = ptr;
2386 s->midi.ocnt += cnt;
2387 spin_unlock_irqrestore(&s->lock, flags);
2388 count -= cnt;
2389 buffer += cnt;
2390 ret += cnt;
2391 spin_lock_irqsave(&s->lock, flags);
2392 es1371_handle_midi(s);
2393 spin_unlock_irqrestore(&s->lock, flags);
2394 }
2395 __set_current_state(TASK_RUNNING);
2396 remove_wait_queue(&s->midi.owait, &wait);
2397 return ret;
2398 }
2399
2400 static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait)
2401 {
2402 struct es1371_state *s = (struct es1371_state *)file->private_data;
2403 unsigned long flags;
2404 unsigned int mask = 0;
2405
2406 VALIDATE_STATE(s);
2407 if (file->f_mode & FMODE_WRITE)
2408 poll_wait(file, &s->midi.owait, wait);
2409 if (file->f_mode & FMODE_READ)
2410 poll_wait(file, &s->midi.iwait, wait);
2411 spin_lock_irqsave(&s->lock, flags);
2412 if (file->f_mode & FMODE_READ) {
2413 if (s->midi.icnt > 0)
2414 mask |= POLLIN | POLLRDNORM;
2415 }
2416 if (file->f_mode & FMODE_WRITE) {
2417 if (s->midi.ocnt < MIDIOUTBUF)
2418 mask |= POLLOUT | POLLWRNORM;
2419 }
2420 spin_unlock_irqrestore(&s->lock, flags);
2421 return mask;
2422 }
2423
2424 static int es1371_midi_open(struct inode *inode, struct file *file)
2425 {
2426 int minor = MINOR(inode->i_rdev);
2427 DECLARE_WAITQUEUE(wait, current);
2428 unsigned long flags;
2429 struct list_head *list;
2430 struct es1371_state *s;
2431
2432 for (list = devs.next; ; list = list->next) {
2433 if (list == &devs)
2434 return -ENODEV;
2435 s = list_entry(list, struct es1371_state, devs);
2436 if (s->dev_midi == minor)
2437 break;
2438 }
2439 VALIDATE_STATE(s);
2440 file->private_data = s;
2441 /* wait for device to become free */
2442 down(&s->open_sem);
2443 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2444 if (file->f_flags & O_NONBLOCK) {
2445 up(&s->open_sem);
2446 return -EBUSY;
2447 }
2448 add_wait_queue(&s->open_wait, &wait);
2449 __set_current_state(TASK_INTERRUPTIBLE);
2450 up(&s->open_sem);
2451 schedule();
2452 remove_wait_queue(&s->open_wait, &wait);
2453 set_current_state(TASK_RUNNING);
2454 if (signal_pending(current))
2455 return -ERESTARTSYS;
2456 down(&s->open_sem);
2457 }
2458 spin_lock_irqsave(&s->lock, flags);
2459 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2460 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2461 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2462 outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL);
2463 outb(0, s->io+ES1371_REG_UART_CONTROL);
2464 outb(0, s->io+ES1371_REG_UART_TEST);
2465 }
2466 if (file->f_mode & FMODE_READ) {
2467 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2468 }
2469 if (file->f_mode & FMODE_WRITE) {
2470 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2471 }
2472 s->ctrl |= CTRL_UART_EN;
2473 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2474 es1371_handle_midi(s);
2475 spin_unlock_irqrestore(&s->lock, flags);
2476 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
2477 up(&s->open_sem);
2478 MOD_INC_USE_COUNT;
2479 return 0;
2480 }
2481
2482 static int es1371_midi_release(struct inode *inode, struct file *file)
2483 {
2484 struct es1371_state *s = (struct es1371_state *)file->private_data;
2485 DECLARE_WAITQUEUE(wait, current);
2486 unsigned long flags;
2487 unsigned count, tmo;
2488
2489 VALIDATE_STATE(s);
2490 if (file->f_mode & FMODE_WRITE) {
2491 add_wait_queue(&s->midi.owait, &wait);
2492 for (;;) {
2493 __set_current_state(TASK_INTERRUPTIBLE);
2494 spin_lock_irqsave(&s->lock, flags);
2495 count = s->midi.ocnt;
2496 spin_unlock_irqrestore(&s->lock, flags);
2497 if (count <= 0)
2498 break;
2499 if (signal_pending(current))
2500 break;
2501 if (file->f_flags & O_NONBLOCK) {
2502 remove_wait_queue(&s->midi.owait, &wait);
2503 set_current_state(TASK_RUNNING);
2504 return -EBUSY;
2505 }
2506 tmo = (count * HZ) / 3100;
2507 if (!schedule_timeout(tmo ? : 1) && tmo)
2508 printk(KERN_DEBUG PFX "midi timed out??\n");
2509 }
2510 remove_wait_queue(&s->midi.owait, &wait);
2511 set_current_state(TASK_RUNNING);
2512 }
2513 down(&s->open_sem);
2514 s->open_mode &= (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE);
2515 spin_lock_irqsave(&s->lock, flags);
2516 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2517 s->ctrl &= ~CTRL_UART_EN;
2518 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2519 }
2520 spin_unlock_irqrestore(&s->lock, flags);
2521 up(&s->open_sem);
2522 wake_up(&s->open_wait);
2523 MOD_DEC_USE_COUNT;
2524 return 0;
2525 }
2526
2527 static /*const*/ struct file_operations es1371_midi_fops = {
2528 llseek: es1371_llseek,
2529 read: es1371_midi_read,
2530 write: es1371_midi_write,
2531 poll: es1371_midi_poll,
2532 open: es1371_midi_open,
2533 release: es1371_midi_release,
2534 };
2535
2536 /* --------------------------------------------------------------------- */
2537
2538 /*
2539 * for debugging purposes, we'll create a proc device that dumps the
2540 * CODEC chipstate
2541 */
2542
2543 #ifdef ES1371_DEBUG
2544 static int proc_es1371_dump (char *buf, char **start, off_t fpos, int length, int *eof, void *data)
2545 {
2546 struct es1371_state *s;
2547 int cnt, len = 0;
2548
2549 if (list_empty(&devs))
2550 return 0;
2551 s = list_entry(devs.next, struct es1371_state, devs);
2552 /* print out header */
2553 len += sprintf(buf + len, "\t\tCreative ES137x Debug Dump-o-matic\n");
2554
2555 /* print out CODEC state */
2556 len += sprintf (buf + len, "AC97 CODEC state\n");
2557 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
2558 len+= sprintf (buf + len, "reg:0x%02x val:0x%04x\n", cnt, rdcodec(&s->codec, cnt));
2559
2560 if (fpos >=len){
2561 *start = buf;
2562 *eof =1;
2563 return 0;
2564 }
2565 *start = buf + fpos;
2566 if ((len -= fpos) > length)
2567 return length;
2568 *eof =1;
2569 return len;
2570
2571 }
2572 #endif /* ES1371_DEBUG */
2573
2574 /* --------------------------------------------------------------------- */
2575
2576 /* maximum number of devices; only used for command line params */
2577 #define NR_DEVICE 5
2578
2579 static int joystick[NR_DEVICE] = { 0, };
2580 static int spdif[NR_DEVICE] = { 0, };
2581
2582 static unsigned int devindex = 0;
2583
2584 MODULE_PARM(joystick, "1-" __MODULE_STRING(NR_DEVICE) "i");
2585 MODULE_PARM_DESC(joystick, "sets address and enables joystick interface (still need separate driver)");
2586 MODULE_PARM(spdif, "1-" __MODULE_STRING(NR_DEVICE) "i");
2587 MODULE_PARM_DESC(spdif, "if 1 the output is in S/PDIF digital mode");
2588
2589 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2590 MODULE_DESCRIPTION("ES1371 AudioPCI97 Driver");
2591
2592 /* --------------------------------------------------------------------- */
2593
2594 static struct initvol {
2595 int mixch;
2596 int vol;
2597 } initvol[] __initdata = {
2598 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2599 { SOUND_MIXER_WRITE_CD, 0x4040 },
2600 { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 },
2601 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2602 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2603 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2604 { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 },
2605 { SOUND_MIXER_WRITE_OGAIN, 0x4040 },
2606 { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 },
2607 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2608 { SOUND_MIXER_WRITE_MIC, 0x4040 },
2609 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2610 { SOUND_MIXER_WRITE_IGAIN, 0x4040 }
2611 };
2612
2613 #define RSRCISIOREGION(dev,num) ((dev)->resource[(num)].start != 0 && \
2614 ((dev)->resource[(num)].flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
2615 #define RSRCADDRESS(dev,num) ((dev)->resource[(num)].start)
2616
2617 static int __devinit es1371_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2618 {
2619 struct es1371_state *s;
2620 mm_segment_t fs;
2621 int i, val;
2622 unsigned long tmo;
2623 signed long tmo2;
2624 unsigned int cssr;
2625
2626 if (!RSRCISIOREGION(pcidev, 0))
2627 return -1;
2628 if (pcidev->irq == 0)
2629 return -1;
2630 if (!pci_dma_supported(pcidev, 0xffffffff)) {
2631 printk(KERN_WARNING "es1371: architecture does not support 32bit PCI busmaster DMA\n");
2632 return -1;
2633 }
2634 if (!(s = kmalloc(sizeof(struct es1371_state), GFP_KERNEL))) {
2635 printk(KERN_WARNING PFX "out of memory\n");
2636 return -1;
2637 }
2638 memset(s, 0, sizeof(struct es1371_state));
2639 init_waitqueue_head(&s->dma_adc.wait);
2640 init_waitqueue_head(&s->dma_dac1.wait);
2641 init_waitqueue_head(&s->dma_dac2.wait);
2642 init_waitqueue_head(&s->open_wait);
2643 init_waitqueue_head(&s->midi.iwait);
2644 init_waitqueue_head(&s->midi.owait);
2645 init_MUTEX(&s->open_sem);
2646 spin_lock_init(&s->lock);
2647 s->magic = ES1371_MAGIC;
2648 s->dev = pcidev;
2649 s->io = RSRCADDRESS(pcidev, 0);
2650 s->irq = pcidev->irq;
2651 s->vendor = pcidev->vendor;
2652 s->device = pcidev->device;
2653 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
2654 s->codec.private_data = s;
2655 s->codec.id = 0;
2656 s->codec.codec_read = rdcodec;
2657 s->codec.codec_write = wrcodec;
2658 printk(KERN_INFO PFX "found chip, vendor id 0x%04x device id 0x%04x revision 0x%02x\n",
2659 s->vendor, s->device, s->rev);
2660 if (!request_region(s->io, ES1371_EXTENT, "es1371")) {
2661 printk(KERN_ERR PFX "io ports %#lx-%#lx in use\n", s->io, s->io+ES1371_EXTENT-1);
2662 goto err_region;
2663 }
2664 if (request_irq(s->irq, es1371_interrupt, SA_SHIRQ, "es1371", s)) {
2665 printk(KERN_ERR PFX "irq %u in use\n", s->irq);
2666 goto err_irq;
2667 }
2668 pci_enable_device(pcidev);
2669 printk(KERN_INFO PFX "found es1371 rev %d at io %#lx irq %u\n"
2670 KERN_INFO PFX "features: joystick 0x%x\n", s->rev, s->io, s->irq, joystick[devindex]);
2671 /* register devices */
2672 if ((s->dev_audio = register_sound_dsp(&es1371_audio_fops, -1)) < 0)
2673 goto err_dev1;
2674 if ((s->codec.dev_mixer = register_sound_mixer(&es1371_mixer_fops, -1)) < 0)
2675 goto err_dev2;
2676 if ((s->dev_dac = register_sound_dsp(&es1371_dac_fops, -1)) < 0)
2677 goto err_dev3;
2678 if ((s->dev_midi = register_sound_midi(&es1371_midi_fops, -1)) < 0)
2679 goto err_dev4;
2680 #ifdef ES1371_DEBUG
2681 /* intialize the debug proc device */
2682 s->ps = create_proc_read_entry("es1371",0,NULL,proc_es1371_dump,NULL);
2683 #endif /* ES1371_DEBUG */
2684
2685 /* initialize codec registers */
2686 s->ctrl = 0;
2687 if ((joystick[devindex] & ~0x18) == 0x200) {
2688 if (check_region(joystick[devindex], JOY_EXTENT))
2689 printk(KERN_ERR PFX "joystick address 0x%x already in use\n", joystick[devindex]);
2690 else {
2691 s->ctrl |= CTRL_JYSTK_EN | (((joystick[devindex] >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT);
2692 }
2693 }
2694 s->sctrl = 0;
2695 cssr = 0;
2696 /* check to see if s/pdif mode is being requested */
2697 if (spdif[devindex]) {
2698 if (s->rev >= 4) {
2699 printk(KERN_INFO PFX "enabling S/PDIF output\n");
2700 cssr |= STAT_EN_SPDIF;
2701 s->ctrl |= CTRL_SPDIFEN_B;
2702 } else {
2703 printk(KERN_ERR PFX "revision %d does not support S/PDIF\n", s->rev);
2704 }
2705 }
2706 /* initialize the chips */
2707 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2708 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2709 outl(0, s->io+ES1371_REG_LEGACY);
2710 pci_set_master(pcidev); /* enable bus mastering */
2711 /* if we are a 5880 turn on the AC97 */
2712 if (s->vendor == PCI_VENDOR_ID_ENSONIQ &&
2713 ((s->device == PCI_DEVICE_ID_ENSONIQ_CT5880 && s->rev == CT5880REV_CT5880_C) ||
2714 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_CT5880_A))) {
2715 cssr |= CSTAT_5880_AC97_RST;
2716 outl(cssr, s->io+ES1371_REG_STATUS);
2717 /* need to delay around 20ms(bleech) to give
2718 some CODECs enough time to wakeup */
2719 tmo = jiffies + (HZ / 50) + 1;
2720 for (;;) {
2721 tmo2 = tmo - jiffies;
2722 if (tmo2 <= 0)
2723 break;
2724 schedule_timeout(tmo2);
2725 }
2726 }
2727 /* AC97 warm reset to start the bitclk */
2728 outl(s->ctrl | CTRL_SYNCRES, s->io+ES1371_REG_CONTROL);
2729 udelay(2);
2730 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2731 /* init the sample rate converter */
2732 src_init(s);
2733 /* codec init */
2734 if (!ac97_probe_codec(&s->codec))
2735 goto err_dev4;
2736 /* set default values */
2737
2738 fs = get_fs();
2739 set_fs(KERNEL_DS);
2740 val = SOUND_MASK_LINE;
2741 s->codec.mixer_ioctl(&s->codec, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2742 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
2743 val = initvol[i].vol;
2744 s->codec.mixer_ioctl(&s->codec, initvol[i].mixch, (unsigned long)&val);
2745 }
2746 set_fs(fs);
2747 /* turn on S/PDIF output driver if requested */
2748 outl(cssr, s->io+ES1371_REG_STATUS);
2749 /* store it in the driver field */
2750 pcidev->driver_data = s;
2751 pcidev->dma_mask = 0xffffffff;
2752 /* put it into driver list */
2753 list_add_tail(&s->devs, &devs);
2754 /* increment devindex */
2755 if (devindex < NR_DEVICE-1)
2756 devindex++;
2757 return 0;
2758
2759 err_dev4:
2760 unregister_sound_dsp(s->dev_dac);
2761 err_dev3:
2762 unregister_sound_mixer(s->codec.dev_mixer);
2763 err_dev2:
2764 unregister_sound_dsp(s->dev_audio);
2765 err_dev1:
2766 printk(KERN_ERR PFX "cannot register misc device\n");
2767 free_irq(s->irq, s);
2768 err_irq:
2769 release_region(s->io, ES1371_EXTENT);
2770 err_region:
2771 kfree_s(s, sizeof(struct es1371_state));
2772 return -1;
2773 }
2774
2775 static void __devinit es1371_remove(struct pci_dev *dev)
2776 {
2777 struct es1371_state *s = (struct es1371_state *)dev->driver_data;
2778
2779 if (!s)
2780 return;
2781 list_del(&s->devs);
2782 #ifdef ES1371_DEBUG
2783 if (s->ps)
2784 remove_proc_entry("es1371", NULL);
2785 #endif /* ES1371_DEBUG */
2786 outl(0, s->io+ES1371_REG_CONTROL); /* switch everything off */
2787 outl(0, s->io+ES1371_REG_SERIAL_CONTROL); /* clear serial interrupts */
2788 synchronize_irq();
2789 free_irq(s->irq, s);
2790 release_region(s->io, ES1371_EXTENT);
2791 unregister_sound_dsp(s->dev_audio);
2792 unregister_sound_mixer(s->codec.dev_mixer);
2793 unregister_sound_dsp(s->dev_dac);
2794 unregister_sound_midi(s->dev_midi);
2795 kfree_s(s, sizeof(struct es1371_state));
2796 dev->driver_data = NULL;
2797 }
2798
2799 static struct pci_device_id id_table[] __devinitdata = {
2800 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2801 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2802 { PCI_VENDOR_ID_ECTIVA, PCI_DEVICE_ID_ECTIVA_EV1938, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2803 { 0, 0, 0, 0, 0, 0 }
2804 };
2805
2806 MODULE_DEVICE_TABLE(pci, id_table);
2807
2808 static struct pci_driver es1371_driver = {
2809 name: "es1371",
2810 id_table: id_table,
2811 probe: es1371_probe,
2812 remove: es1371_remove
2813 };
2814
2815 static int __init init_es1371(void)
2816 {
2817 if (!pci_present()) /* No PCI bus in this machine! */
2818 return -ENODEV;
2819 printk(KERN_INFO "es1371: version v0.25 time " __TIME__ " " __DATE__ "\n");
2820 if (!pci_register_driver(&es1371_driver)) {
2821 pci_unregister_driver(&es1371_driver);
2822 return -ENODEV;
2823 }
2824 return 0;
2825 }
2826
2827 static void __exit cleanup_es1371(void)
2828 {
2829 printk(KERN_INFO PFX "unloading\n");
2830 pci_unregister_driver(&es1371_driver);
2831 }
2832
2833 module_init(init_es1371);
2834 module_exit(cleanup_es1371);
2835
2836 /* --------------------------------------------------------------------- */
2837
2838 #ifndef MODULE
2839
2840 /* format is: es1371=[joystick] */
2841
2842 static int __init es1371_setup(char *str)
2843 {
2844 static unsigned __initlocaldata nr_dev = 0;
2845
2846 if (nr_dev >= NR_DEVICE)
2847 return 0;
2848 if (get_option(&str, &joystick[nr_dev]) == 2)
2849 (void)get_option(&str, &spdif[nr_dev]);
2850 nr_dev++;
2851 return 1;
2852 }
2853
2854 __setup("es1371=", es1371_setup);
2855
2856 #endif /* MODULE */
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