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Merge with 2.3.48.
[linux-2.6/linux-mips.git] / drivers / block / hpt34x.c
blob7a077368edb5f08e60fd1d3ebe7704223e149453
1 /*
2 * linux/drivers/block/hpt34x.c Version 0.29 Feb. 10, 2000
3 *
4 * Copyright (C) 1998-2000 Andre Hedrick (andre@suse.com)
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 *
8 * 00:12.0 Unknown mass storage controller:
9 * Triones Technologies, Inc.
10 * Unknown device 0003 (rev 01)
11 *
12 * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
13 * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
14 * hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010)
15 * hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030)
16 * hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070)
17 * hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0)
18 *
19 * ide-pci.c reference
20 *
21 * Since there are two cards that report almost identically,
22 * the only discernable difference is the values reported in pcicmd.
23 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
24 * Non-bootable card or HPT343 :: pcicmd == 0x05
25 */
26
27 #include <linux/config.h>
28 #include <linux/types.h>
29 #include <linux/kernel.h>
30 #include <linux/delay.h>
31 #include <linux/timer.h>
32 #include <linux/mm.h>
33 #include <linux/ioport.h>
34 #include <linux/blkdev.h>
35 #include <linux/hdreg.h>
36 #include <linux/interrupt.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/ide.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include "ide_modes.h"
44
45 #ifndef SPLIT_BYTE
46 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
47 #endif
48
49 #define HPT343_DEBUG_DRIVE_INFO 1
50
51 #define DISPLAY_HPT34X_TIMINGS
52 #if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
53 #include <linux/stat.h>
54 #include <linux/proc_fs.h>
55
56 static int hpt34x_get_info(char *, char **, off_t, int);
57 extern int (*hpt34x_display_info)(char *, char **, off_t, int); /* ide-proc.c */
58 extern char *ide_media_verbose(ide_drive_t *);
59 static struct pci_dev *bmide_dev;
60
61 static int hpt34x_get_info (char *buffer, char **addr, off_t offset, int count)
62 {
63 char *p = buffer;
64 u32 bibma = bmide_dev->resource[4].start;
65 u8 c0 = 0, c1 = 0;
66
67 /*
68 * at that point bibma+0x2 et bibma+0xa are byte registers
69 * to investigate:
70 */
71 c0 = inb_p((unsigned short)bibma + 0x02);
72 c1 = inb_p((unsigned short)bibma + 0x0a);
73
74 p += sprintf(p, "\n HPT34X Chipset.\n");
75 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
76 p += sprintf(p, " %sabled %sabled\n",
77 (c0&0x80) ? "dis" : " en",
78 (c1&0x80) ? "dis" : " en");
79 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
80 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
81 (c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
82 (c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
83
84 p += sprintf(p, "UDMA\n");
85 p += sprintf(p, "DMA\n");
86 p += sprintf(p, "PIO\n");
87
88 return p-buffer; /* => must be less than 4k! */
89 }
90 #endif /* defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS) */
91
92 byte hpt34x_proc = 0;
93
94 extern char *ide_xfer_verbose (byte xfer_rate);
95
96 static void hpt34x_clear_chipset (ide_drive_t *drive)
97 {
98 int drive_number = ((HWIF(drive)->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
99 unsigned int reg1 = 0, tmp1 = 0;
100 unsigned int reg2 = 0, tmp2 = 0;
101
102 pci_read_config_dword(HWIF(drive)->pci_dev, 0x44, &reg1);
103 pci_read_config_dword(HWIF(drive)->pci_dev, 0x48, &reg2);
104 tmp1 = ((0x00 << (3*drive_number)) | (reg1 & ~(7 << (3*drive_number))));
105 tmp2 = (reg2 & ~(0x11 << drive_number));
106 pci_write_config_dword(HWIF(drive)->pci_dev, 0x44, tmp1);
107 pci_write_config_dword(HWIF(drive)->pci_dev, 0x48, tmp2);
108 }
109
110 static int hpt34x_tune_chipset (ide_drive_t *drive, byte speed)
111 {
112 int err;
113 byte hi_speed, lo_speed;
114 int drive_number = ((HWIF(drive)->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
115 unsigned int reg1 = 0, tmp1 = 0;
116 unsigned int reg2 = 0, tmp2 = 0;
117
118 SPLIT_BYTE(speed, hi_speed, lo_speed);
119
120 if (hi_speed & 7) {
121 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
122 } else {
123 lo_speed <<= 5;
124 lo_speed >>= 5;
125 }
126
127 pci_read_config_dword(HWIF(drive)->pci_dev, 0x44, &reg1);
128 pci_read_config_dword(HWIF(drive)->pci_dev, 0x48, &reg2);
129 tmp1 = ((lo_speed << (3*drive_number)) | (reg1 & ~(7 << (3*drive_number))));
130 tmp2 = ((hi_speed << drive_number) | reg2);
131 err = ide_config_drive_speed(drive, speed);
132 pci_write_config_dword(HWIF(drive)->pci_dev, 0x44, tmp1);
133 pci_write_config_dword(HWIF(drive)->pci_dev, 0x48, tmp2);
134
135 #if HPT343_DEBUG_DRIVE_INFO
136 printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
137 " (0x%02x 0x%02x) 0x%04x\n",
138 drive->name, ide_xfer_verbose(speed),
139 drive_number, reg1, tmp1, reg2, tmp2,
140 hi_speed, lo_speed, err);
141 #endif /* HPT343_DEBUG_DRIVE_INFO */
142
143 return(err);
144 }
145
146 /*
147 * This allows the configuration of ide_pci chipset registers
148 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
149 * after the drive is reported by the OS. Initally for designed for
150 * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
151 */
152 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
153 {
154 struct hd_driveid *id = drive->id;
155 byte speed = 0x00;
156
157 if (drive->media != ide_disk)
158 return ((int) ide_dma_off_quietly);
159
160 hpt34x_clear_chipset(drive);
161
162 if ((id->dma_ultra & 0x0010) && ultra) {
163 speed = XFER_UDMA_2;
164 } else if ((id->dma_ultra & 0x0008) && ultra) {
165 speed = XFER_UDMA_2;
166 } else if ((id->dma_ultra & 0x0004) && ultra) {
167 speed = XFER_UDMA_2;
168 } else if ((id->dma_ultra & 0x0002) && ultra) {
169 speed = XFER_UDMA_1;
170 } else if ((id->dma_ultra & 0x0001) && ultra) {
171 speed = XFER_UDMA_0;
172 } else if (id->dma_mword & 0x0004) {
173 speed = XFER_MW_DMA_2;
174 } else if (id->dma_mword & 0x0002) {
175 speed = XFER_MW_DMA_1;
176 } else if (id->dma_mword & 0x0001) {
177 speed = XFER_MW_DMA_0;
178 } else if (id->dma_1word & 0x0004) {
179 speed = XFER_SW_DMA_2;
180 } else if (id->dma_1word & 0x0002) {
181 speed = XFER_SW_DMA_1;
182 } else if (id->dma_1word & 0x0001) {
183 speed = XFER_SW_DMA_0;
184 } else {
185 return ((int) ide_dma_off_quietly);
186 }
187
188 (void) hpt34x_tune_chipset(drive, speed);
189
190 return ((int) ((id->dma_ultra >> 11) & 3) ? ide_dma_off :
191 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
192 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
193 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
194 ide_dma_off_quietly);
195 }
196
197 static void config_chipset_for_pio (ide_drive_t *drive)
198 {
199 unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
200 unsigned short xfer_pio = drive->id->eide_pio_modes;
201
202 byte timing, speed, pio;
203
204 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
205
206 if (xfer_pio> 4)
207 xfer_pio = 0;
208
209 if (drive->id->eide_pio_iordy > 0) {
210 for (xfer_pio = 5;
211 xfer_pio>0 &&
212 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
213 xfer_pio--);
214 } else {
215 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
216 (drive->id->eide_pio_modes & 2) ? 0x04 :
217 (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
218 }
219
220 timing = (xfer_pio >= pio) ? xfer_pio : pio;
221
222 switch(timing) {
223 case 4: speed = XFER_PIO_4;break;
224 case 3: speed = XFER_PIO_3;break;
225 case 2: speed = XFER_PIO_2;break;
226 case 1: speed = XFER_PIO_1;break;
227 default:
228 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
229 break;
230 }
231 (void) hpt34x_tune_chipset(drive, speed);
232 }
233
234 static void hpt34x_tune_drive (ide_drive_t *drive, byte pio)
235 {
236 byte speed;
237
238 switch(pio) {
239 case 4: speed = XFER_PIO_4;break;
240 case 3: speed = XFER_PIO_3;break;
241 case 2: speed = XFER_PIO_2;break;
242 case 1: speed = XFER_PIO_1;break;
243 default: speed = XFER_PIO_0;break;
244 }
245 hpt34x_clear_chipset(drive);
246 (void) hpt34x_tune_chipset(drive, speed);
247 }
248
249 static int config_drive_xfer_rate (ide_drive_t *drive)
250 {
251 struct hd_driveid *id = drive->id;
252 ide_dma_action_t dma_func = ide_dma_on;
253
254 if (id && (id->capability & 1) && HWIF(drive)->autodma) {
255 /* Consult the list of known "bad" drives */
256 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
257 dma_func = ide_dma_off;
258 goto fast_ata_pio;
259 }
260 dma_func = ide_dma_off_quietly;
261 if (id->field_valid & 4) {
262 if (id->dma_ultra & 0x0007) {
263 /* Force if Capable UltraDMA */
264 dma_func = config_chipset_for_dma(drive, 1);
265 if ((id->field_valid & 2) &&
266 (dma_func != ide_dma_on))
267 goto try_dma_modes;
268 }
269 } else if (id->field_valid & 2) {
270 try_dma_modes:
271 if ((id->dma_mword & 0x0007) ||
272 (id->dma_1word & 0x0007)) {
273 /* Force if Capable regular DMA modes */
274 dma_func = config_chipset_for_dma(drive, 0);
275 if (dma_func != ide_dma_on)
276 goto no_dma_set;
277 }
278 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
279 if (id->eide_dma_time > 150) {
280 goto no_dma_set;
281 }
282 /* Consult the list of known "good" drives */
283 dma_func = config_chipset_for_dma(drive, 0);
284 if (dma_func != ide_dma_on)
285 goto no_dma_set;
286 } else {
287 goto fast_ata_pio;
288 }
289 } else if ((id->capability & 8) || (id->field_valid & 2)) {
290 fast_ata_pio:
291 dma_func = ide_dma_off_quietly;
292 no_dma_set:
293 config_chipset_for_pio(drive);
294 }
295
296 #ifndef CONFIG_HPT34X_AUTODMA
297 if (dma_func == ide_dma_on)
298 dma_func = ide_dma_off;
299 #endif /* CONFIG_HPT34X_AUTODMA */
300
301 return HWIF(drive)->dmaproc(dma_func, drive);
302 }
303
304 /*
305 * hpt34x_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
306 *
307 * This is specific to the HPT343 UDMA bios-less chipset
308 * and HPT345 UDMA bios chipset (stamped HPT363)
309 * by HighPoint|Triones Technologies, Inc.
310 */
311
312 int hpt34x_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
313 {
314 ide_hwif_t *hwif = HWIF(drive);
315 unsigned long dma_base = hwif->dma_base;
316 unsigned int count, reading = 0;
317 byte dma_stat;
318
319 switch (func) {
320 case ide_dma_check:
321 return config_drive_xfer_rate(drive);
322 case ide_dma_read:
323 reading = 1 << 3;
324 case ide_dma_write:
325 if (!(count = ide_build_dmatable(drive, func)))
326 return 1; /* try PIO instead of DMA */
327 outl(hwif->dmatable_dma, dma_base + 4); /* PRD table */
328 reading |= 0x01;
329 outb(reading, dma_base); /* specify r/w */
330 outb(inb(dma_base+2)|6, dma_base+2); /* clear INTR & ERROR flags */
331 drive->waiting_for_dma = 1;
332 if (drive->media != ide_disk)
333 return 0;
334 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL); /* issue cmd to drive */
335 OUT_BYTE((reading == 9) ? WIN_READDMA : WIN_WRITEDMA, IDE_COMMAND_REG);
336 return 0;
337 case ide_dma_end: /* returns 1 on error, 0 otherwise */
338 drive->waiting_for_dma = 0;
339 outb(inb(dma_base)&~1, dma_base); /* stop DMA */
340 dma_stat = inb(dma_base+2); /* get DMA status */
341 outb(dma_stat|6, dma_base+2); /* clear the INTR & ERROR bits */
342 ide_destroy_dmatable(drive); /* purge DMA mappings */
343 return (dma_stat & 7) != 4; /* verify good DMA status */
344 default:
345 break;
346 }
347 return ide_dmaproc(func, drive); /* use standard DMA stuff */
348 }
349
350 /*
351 * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
352 */
353 #define HPT34X_PCI_INIT_REG 0x80
354
355 unsigned int __init pci_init_hpt34x (struct pci_dev *dev, const char *name)
356 {
357 int i = 0;
358 unsigned long hpt34xIoBase = dev->resource[4].start;
359 unsigned short cmd;
360 unsigned long flags;
361
362 __save_flags(flags); /* local CPU only */
363 __cli(); /* local CPU only */
364
365 pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
366 pci_read_config_word(dev, PCI_COMMAND, &cmd);
367
368 if (cmd & PCI_COMMAND_MEMORY) {
369 if (dev->resource[PCI_ROM_RESOURCE].start) {
370 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
371 printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n", dev->resource[PCI_ROM_RESOURCE].start);
372 }
373 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
374 } else {
375 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
376 }
377
378 pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
379 dev->resource[0].start = (hpt34xIoBase + 0x20);
380 dev->resource[1].start = (hpt34xIoBase + 0x34);
381 dev->resource[2].start = (hpt34xIoBase + 0x28);
382 dev->resource[3].start = (hpt34xIoBase + 0x3c);
383 for(i=0; i<4; i++)
384 dev->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
385 /*
386 * Since 20-23 can be assigned and are R/W, we correct them.
387 */
388 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, dev->resource[0].start);
389 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, dev->resource[1].start);
390 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, dev->resource[2].start);
391 pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, dev->resource[3].start);
392 pci_write_config_word(dev, PCI_COMMAND, cmd);
393
394 __restore_flags(flags); /* local CPU only */
395
396 #if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
397 hpt34x_proc = 1;
398 bmide_dev = dev;
399 hpt34x_display_info = &hpt34x_get_info;
400 #endif /* DISPLAY_HPT34X_TIMINGS && CONFIG_PROC_FS */
401
402 return dev->irq;
403 }
404
405 void __init ide_init_hpt34x (ide_hwif_t *hwif)
406 {
407 hwif->tuneproc = &hpt34x_tune_drive;
408 if (hwif->dma_base) {
409 unsigned short pcicmd = 0;
410
411 pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
412 hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
413 hwif->dmaproc = &hpt34x_dmaproc;
414 } else {
415 hwif->drives[0].autotune = 1;
416 hwif->drives[1].autotune = 1;
417 }
418 }
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