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[linux-2.6/linux-mips.git] / include / asm-v850 / ma.h
blobed153b642360d855e281e6424781bd3554d59963
1 /*
2 * include/asm-v850/ma.h -- V850E/MA series of cpu chips
4 * Copyright (C) 2001,02 NEC Corporation
5 * Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this
9 * archive for more details.
11 * Written by Miles Bader <miles@gnu.org>
14 #ifndef __V850_MA_H__
15 #define __V850_MA_H__
18 /* The MA series uses the NB85E cpu core. */
19 #include <asm/nb85e.h>
22 /* For <asm/entry.h> */
23 /* We use on-chip RAM, for a few miscellaneous variables that must be
24 accessible using a load instruction relative to R0. The amount
25 varies between chip models, but there's always at least 4K, and it
26 should always start at FFFFC000. */
27 #define R0_RAM_ADDR 0xFFFFC000
30 /* MA series UART details. */
31 #define NB85E_UART_BASE_FREQ CPU_CLOCK_FREQ
33 /* This is a function that gets called before configuring the UART. */
34 #define NB85E_UART_PRE_CONFIGURE ma_uart_pre_configure
35 #ifndef __ASSEMBLY__
36 extern void ma_uart_pre_configure (unsigned chan,
37 unsigned cflags, unsigned baud);
38 #endif
41 /* MA series timer C details. */
42 #define NB85E_TIMER_C_BASE_ADDR 0xFFFFF600
45 /* MA series timer D details. */
46 #define NB85E_TIMER_D_BASE_ADDR 0xFFFFF540
47 #define NB85E_TIMER_D_TMD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x0)
48 #define NB85E_TIMER_D_CMD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x2)
49 #define NB85E_TIMER_D_TMCD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x4)
51 #define NB85E_TIMER_D_BASE_FREQ CPU_CLOCK_FREQ
54 /* Port 0 */
55 /* Direct I/O. Bits 0-7 are pins P00-P07. */
56 #define MA_PORT0_IO_ADDR 0xFFFFF400
57 #define MA_PORT0_IO (*(volatile u8 *)MA_PORT0_IO_ADDR)
58 /* Port mode (for direct I/O, 0 = output, 1 = input). */
59 #define MA_PORT0_PM_ADDR 0xFFFFF420
60 #define MA_PORT0_PM (*(volatile u8 *)MA_PORT0_PM_ADDR)
61 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
62 #define MA_PORT0_PMC_ADDR 0xFFFFF440
63 #define MA_PORT0_PMC (*(volatile u8 *)MA_PORT0_PMC_ADDR)
64 /* Port function control (for P04-P07, 0 = IRQ, 1 = DMARQ). */
65 #define MA_PORT0_PFC_ADDR 0xFFFFF460
66 #define MA_PORT0_PFC (*(volatile u8 *)MA_PORT0_PFC_ADDR)
68 /* Port 1 */
69 /* Direct I/O. Bits 0-3 are pins P10-P13. */
70 #define MA_PORT1_IO_ADDR 0xFFFFF402
71 #define MA_PORT1_IO (*(volatile u8 *)MA_PORT1_IO_ADDR)
72 /* Port mode (for direct I/O, 0 = output, 1 = input). */
73 #define MA_PORT1_PM_ADDR 0xFFFFF420
74 #define MA_PORT1_PM (*(volatile u8 *)MA_PORT1_PM_ADDR)
75 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
76 #define MA_PORT1_PMC_ADDR 0xFFFFF442
77 #define MA_PORT1_PMC (*(volatile u8 *)MA_PORT1_PMC_ADDR)
79 /* Port 4 */
80 /* Direct I/O. Bits 0-5 are pins P40-P45. */
81 #define MA_PORT4_IO_ADDR 0xFFFFF408
82 #define MA_PORT4_IO (*(volatile u8 *)MA_PORT4_IO_ADDR)
83 /* Port mode (for direct I/O, 0 = output, 1 = input). */
84 #define MA_PORT4_PM_ADDR 0xFFFFF428
85 #define MA_PORT4_PM (*(volatile u8 *)MA_PORT4_PM_ADDR)
86 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
87 #define MA_PORT4_PMC_ADDR 0xFFFFF448
88 #define MA_PORT4_PMC (*(volatile u8 *)MA_PORT4_PMC_ADDR)
89 /* Port function control (for serial interfaces, 0 = CSI, 1 = UART). */
90 #define MA_PORT4_PFC_ADDR 0xFFFFF468
91 #define MA_PORT4_PFC (*(volatile u8 *)MA_PORT4_PFC_ADDR)
94 #ifndef __ASSEMBLY__
96 /* Initialize MA chip interrupts. */
97 extern void ma_init_irqs (void);
99 #endif /* !__ASSEMBLY__ */
102 #endif /* __V850_MA_H__ */