include/asm-parisc/cacheflush.h

   1 #ifndef _PARISC_CACHEFLUSH_H
   2 #define _PARISC_CACHEFLUSH_H
   3
   4 #include <linux/config.h>
   5 #include <linux/mm.h>
   6
   7 /* The usual comment is "Caches aren't brain-dead on the <architecture>".
   8  * Unfortunately, that doesn't apply to PA-RISC. */
   9
  10 /* Cache flush operations */
  11
  12 #ifdef CONFIG_SMP
  13 #define flush_cache_mm(mm) flush_cache_all()
  14 #else
  15 #define flush_cache_mm(mm) flush_cache_all_local()
  16 #endif
  17
  18 #define flush_kernel_dcache_range(start,size) \
  19         flush_kernel_dcache_range_asm((start), (start)+(size));
  20
  21 extern void flush_cache_all_local(void);
  22
  23 static inline void cacheflush_h_tmp_function(void *dummy)
  24 {
  25         flush_cache_all_local();
  26 }
  27
  28 static inline void flush_cache_all(void)
  29 {
  30         on_each_cpu(cacheflush_h_tmp_function, NULL, 1, 1);
  31 }
  32
  33 /* The following value needs to be tuned and probably scaled with the
  34  * cache size.
  35  */
  36
  37 #define FLUSH_THRESHOLD 0x80000
  38
  39 static inline void
  40 flush_user_dcache_range(unsigned long start, unsigned long end)
  41 {
  42 #ifdef CONFIG_SMP
  43         flush_user_dcache_range_asm(start,end);
  44 #else
  45         if ((end - start) < FLUSH_THRESHOLD)
  46                 flush_user_dcache_range_asm(start,end);
  47         else
  48                 flush_data_cache();
  49 #endif
  50 }
  51
  52 static inline void
  53 flush_user_icache_range(unsigned long start, unsigned long end)
  54 {
  55 #ifdef CONFIG_SMP
  56         flush_user_icache_range_asm(start,end);
  57 #else
  58         if ((end - start) < FLUSH_THRESHOLD)
  59                 flush_user_icache_range_asm(start,end);
  60         else
  61                 flush_instruction_cache();
  62 #endif
  63 }
  64
  65 extern void __flush_dcache_page(struct page *page);
  66
  67 static inline void flush_dcache_page(struct page *page)
  68 {
  69         if (page->mapping && list_empty(&page->mapping->i_mmap) &&
  70                         list_empty(&page->mapping->i_mmap_shared)) {
  71                 set_bit(PG_dcache_dirty, &page->flags);
  72         } else {
  73                 __flush_dcache_page(page);
  74         }
  75 }
  76
  77 #define flush_icache_page(vma,page)     do { flush_kernel_dcache_page(page_address(page)); flush_kernel_icache_page(page_address(page)); } while (0)
  78
  79 #define flush_icache_range(s,e)         do { flush_kernel_dcache_range_asm(s,e); flush_kernel_icache_range_asm(s,e); } while (0)
  80
  81 #define flush_icache_user_range(vma, page, addr, len) \
  82         flush_icache_page((vma), (page))
  83
  84 static inline void flush_cache_range(struct vm_area_struct *vma,
  85                 unsigned long start, unsigned long end)
  86 {
  87         int sr3;
  88
  89         if (!vma->vm_mm->context) {
  90                 BUG();
  91                 return;
  92         }
  93
  94         sr3 = mfsp(3);
  95         if (vma->vm_mm->context == sr3) {
  96                 flush_user_dcache_range(start,end);
  97                 flush_user_icache_range(start,end);
  98         } else {
  99                 flush_cache_all();
 100         }
 101 }
 102
 103 static inline void
 104 flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr)
 105 {
 106         int sr3;
 107
 108         if (!vma->vm_mm->context) {
 109                 BUG();
 110                 return;
 111         }
 112
 113         sr3 = mfsp(3);
 114         if (vma->vm_mm->context == sr3) {
 115                 flush_user_dcache_range(vmaddr,vmaddr + PAGE_SIZE);
 116                 if (vma->vm_flags & VM_EXEC)
 117                         flush_user_icache_range(vmaddr,vmaddr + PAGE_SIZE);
 118         } else {
 119                 if (vma->vm_flags & VM_EXEC)
 120                         flush_cache_all();
 121                 else
 122                         flush_data_cache();
 123         }
 124 }
 125 #endif
 126