include/asm-i386/timex.h

   1 /*
   2  * linux/include/asm-i386/timex.h
   3  *
   4  * i386 architecture timex specifications
   5  */
   6 #ifndef _ASMi386_TIMEX_H
   7 #define _ASMi386_TIMEX_H
   8
   9 #include <linux/config.h>
  10 #include <asm/msr.h>
  11
  12 #ifdef CONFIG_X86_PC9800
  13    extern int CLOCK_TICK_RATE;
  14 #else
  15 #ifdef CONFIG_MELAN
  16 #  define CLOCK_TICK_RATE 1189200 /* AMD Elan has different frequency! */
  17 #else
  18 #  define CLOCK_TICK_RATE 1193182 /* Underlying HZ */
  19 #endif
  20 #endif
  21
  22 #define CLOCK_TICK_FACTOR       20      /* Factor of both 1000000 and CLOCK_TICK_RATE */
  23 #define FINETUNE ((((((long)LATCH * HZ - CLOCK_TICK_RATE) << SHIFT_HZ) * \
  24         (1000000/CLOCK_TICK_FACTOR) / (CLOCK_TICK_RATE/CLOCK_TICK_FACTOR)) \
  25                 << (SHIFT_SCALE-SHIFT_HZ)) / HZ)
  26
  27 /*
  28  * Standard way to access the cycle counter on i586+ CPUs.
  29  * Currently only used on SMP.
  30  *
  31  * If you really have a SMP machine with i486 chips or older,
  32  * compile for that, and this will just always return zero.
  33  * That's ok, it just means that the nicer scheduling heuristics
  34  * won't work for you.
  35  *
  36  * We only use the low 32 bits, and we'd simply better make sure
  37  * that we reschedule before that wraps. Scheduling at least every
  38  * four billion cycles just basically sounds like a good idea,
  39  * regardless of how fast the machine is.
  40  */
  41 typedef unsigned long long cycles_t;
  42
  43 extern cycles_t cacheflush_time;
  44
  45 static inline cycles_t get_cycles (void)
  46 {
  47 #ifndef CONFIG_X86_TSC
  48         return 0;
  49 #else
  50         unsigned long long ret;
  51
  52         rdtscll(ret);
  53         return ret;
  54 #endif
  55 }
  56
  57 extern unsigned long cpu_khz;
  58
  59 #endif