include/asm-parisc/superio.h

   1 #ifndef _PARISC_SUPERIO_H
   2 #define _PARISC_SUPERIO_H
   3
   4 /* Offsets to configuration and base address registers */
   5 #define IC_PIC1    0x20         /* PCI I/O address of master 8259 */
   6 #define IC_PIC2    0xA0         /* PCI I/O address of slave */
   7 #define SIO_CR     0x5A         /* Configuration Register */
   8 #define SIO_ACPIBAR 0x88                /* ACPI BAR */
   9 #define SIO_FDCBAR 0x90         /* Floppy Disk Controller BAR */
  10 #define SIO_SP1BAR 0x94         /* Serial 1 BAR */
  11 #define SIO_SP2BAR 0x98         /* Serial 2 BAR */
  12 #define SIO_PPBAR  0x9C         /* Parallel BAR */
  13
  14 /* Interrupt triggers and routing */
  15 #define TRIGGER_1  0x67         /* Edge/level trigger register 1 */
  16 #define TRIGGER_2  0x68         /* Edge/level trigger register 2 */
  17 #define IR_SER     0x69         /* Serial 1 [0:3] and Serial 2 [4:7] */
  18 #define IR_PFD     0x6a         /* Parallel [0:3] and Floppy [4:7] */
  19 #define IR_IDE     0x6b         /* IDE1 [0:3] and IDE2 [4:7] */
  20 #define IR_USB     0x6d         /* USB [4:7] */
  21 #define IR_LOW     0x69         /* Lowest interrupt routing reg */
  22 #define IR_HIGH    0x71         /* Highest interrupt routing reg */
  23
  24 /* 8259 operational control words */
  25 #define OCW2_EOI   0x20         /* Non-specific EOI */
  26 #define OCW2_SEOI  0x60         /* Specific EOI */
  27 #define OCW3_IIR   0x0A         /* Read request register */
  28 #define OCW3_ISR   0x0B         /* Read service register */
  29 #define OCW3_POLL  0x0C         /* Poll the PIC for an interrupt vector */
  30
  31 /* Interrupt lines. Only PIC1 is used */
  32 #define USB_IRQ    1            /* USB */
  33 #define SP1_IRQ    3            /* Serial port 1 */
  34 #define SP2_IRQ    4            /* Serial port 2 */
  35 #define PAR_IRQ    5            /* Parallel port */
  36 #define FDC_IRQ    6            /* Floppy controller */
  37 #define IDE_IRQ    7            /* IDE (pri+sec) */
  38
  39 /* ACPI registers */
  40 #define USB_REG_CR      0x1f    /* USB Regulator Control Register */
  41
  42 #define SUPERIO_NIRQS   8
  43
  44 struct superio_device {
  45         u16 fdc_base;
  46         u16 sp1_base;
  47         u16 sp2_base;
  48         u16 pp_base;
  49         u16 acpi_base;
  50         int iosapic_irq;
  51         int iosapic_irq_enabled;
  52         struct irq_region *irq_region;
  53         struct pci_dev *lio_pdev;       /* pci device for legacy IO fn */
  54 };
  55
  56 /*
  57  * Does NS make a 87415 based plug in PCI card? If so, because of this
  58  * macro we currently don't support it being plugged into a machine
  59  * that contains a SuperIO chip AND has CONFIG_SUPERIO enabled.
  60  *
  61  * This could be fixed by checking to see if function 1 exists, and
  62  * if it is SuperIO Legacy IO; but really now, is this combination
  63  * going to EVER happen?
  64  */
  65
  66 #define SUPERIO_IDE_FN 0 /* Function number of IDE controller */
  67 #define SUPERIO_LIO_FN 1 /* Function number of Legacy IO controller */
  68 #define SUPERIO_USB_FN 2 /* Function number of USB controller */
  69
  70 #define is_superio_device(x) \
  71         (((x)->vendor == PCI_VENDOR_ID_NS) && \
  72         (  ((x)->device == PCI_DEVICE_ID_NS_87415) \
  73         || ((x)->device == PCI_DEVICE_ID_NS_87560_LIO) \
  74         || ((x)->device == PCI_DEVICE_ID_NS_87560_USB) ) )
  75
  76 extern void superio_inform_irq(int irq);
  77 extern void superio_serial_init(void);          /* called by rs_init() */
  78 extern int superio_fixup_irq(struct pci_dev *pcidev); /* called by iosapic */
  79 extern int superio_get_ide_irq(void);
  80
  81 #endif /* _PARISC_SUPERIO_H */