drivers/sgi/audio/hal2.h

   1 /*
   2  * drivers/sgi/audio/hal2.h
   3  *
   4  * Copyright (C) 1998 Ulf Carlsson (ulfc@bun.falkenberg.se)
   5  *
   6  */
   7
   8 #define H2_HAL2_BASE            (HPC3_CHIP0_PBASE + 0x58000)
   9 #define H2_CTRL_PIO             (H2_HAL2_BASE + 0 * 0x200)
  10 #define H2_AES_PIO              (H2_HAL2_BASE + 1 * 0x200)
  11 #define H2_VOLUME_PIO           (H2_HAL2_BASE + 2 * 0x200)
  12 #define H2_SYNTH_PIO            (H2_HAL2_BASE + 3 * 0x200)
  13
  14 typedef volatile unsigned int hal_reg;
  15
  16 struct hal2_ctrl_regs {
  17         hal_reg _unused0[4];
  18         hal_reg isr;            /* 0x10 Status Register */
  19         hal_reg _unused1[3];
  20         hal_reg rev;            /* 0x20 Revision Register */
  21         hal_reg _unused2[3];
  22         hal_reg iar;            /* 0x30 Indirect Address Register */
  23         hal_reg _unused3[3];
  24         hal_reg idr0;           /* 0x40 Indirect Data Register 0 */
  25         hal_reg _unused4[3];
  26         hal_reg idr1;           /* 0x50 Indirect Data Register 1 */
  27         hal_reg _unused5[3];
  28         hal_reg idr2;           /* 0x60 Indirect Data Register 2 */
  29         hal_reg _unused6[3];
  30         hal_reg idr3;           /* 0x70 Indirect Data Register 3 */
  31 } volatile *h2_ctrl = (struct hal2_ctrl_regs *) KSEG1ADDR(H2_CTRL_PIO);
  32
  33 struct hal2_vol_regs {
  34         hal_reg right;          /* 0x00 Right volume */
  35         hal_reg left;           /* 0x04 Left volume */
  36 } volatile *h2_vol = (struct hal2_vol_regs *) KSEG1ADDR(H2_VOLUME_PIO);
  37
  38 /* AES and synth regs should end up here if we ever support them */
  39
  40 /* Indirect status register */
  41
  42 #define H2_ISR_TSTATUS          0x01    /* RO: transaction status 1=busy */
  43 #define H2_ISR_USTATUS          0x02    /* RO: utime status bit 1=armed */
  44 #define H2_ISR_CODEC_MODE       0x04    /* codec mode 0=indigo 1=quad */
  45 #define H2_ISR_GLOBAL_RESET_N   0x08    /* chip global reset 0=reset */
  46 #define H2_ISR_CODEC_RESET_N    0x10    /* codec/synth reset 0=reset  */
  47
  48         /* Revision register */
  49
  50 #define H2_REV_AUDIO_PRESENT    0x8000  /* RO: audio present 0=present */
  51 #define H2_REV_BOARD_M          0x7000  /* RO: bits 14:12, board revision */
  52 #define H2_REV_MAJOR_CHIP_M     0x00F0  /* RO: bits 7:4, major chip revision */
  53 #define H2_REV_MINOR_CHIP_M     0x000F  /* RO: bits 3:0, minor chip revision */
  54
  55 /* Indirect address register */
  56
  57 /*
  58  * Address of indirect internal register to be accessed. A write to this
  59  * register initiates read or write access to the indirect registers in the
  60  * HAL2. Note that there af four indirect data registers for write access to
  61  * registers larger than 16 byte.
  62  */
  63
  64 #define H2_IAR_TYPE_M           0xF000  /* bits 15:12, type of functional */
  65                                         /* block the register resides in */
  66                                         /* 1=DMA Port */
  67                                         /* 9=Global DMA Control */
  68                                         /* 2=Bresenham */
  69                                         /* 3=Unix Timer */
  70 #define H2_IAR_NUM_M            0x0F00  /* bits 11:8 instance of the */
  71                                         /* blockin which the indirect */
  72                                         /* register resides */
  73                                         /* If IAR_TYPE_M=DMA Port: */
  74                                         /* 1=Synth In */
  75                                         /* 2=AES In */
  76                                         /* 3=AES Out */
  77                                         /* 4=DAC Out */
  78                                         /* 5=ADC Out */
  79                                         /* 6=Synth Control */
  80                                         /* If IAR_TYPE_M=Global DMA Control: */
  81                                         /* 1=Control */
  82                                         /* If IAR_TYPE_M=Bresenham: */
  83                                         /* 1=Bresenham Clock Gen 1 */
  84                                         /* 2=Bresenham Clock Gen 2 */
  85                                         /* 3=Bresenham Clock Gen 3 */
  86                                         /* If IAR_TYPE_M=Unix Timer: */
  87                                         /* 1=Unix Timer */
  88 #define H2_IAR_ACCESS_SELECT    0x0080  /* 1=read 0=write */
  89 #define H2_IAR_PARAM            0x000C  /* Parameter Select */
  90 #define H2_IAR_RB_INDEX_M       0x0003  /* Read Back Index */
  91                                         /* 00:word0 */
  92                                         /* 01:word1 */
  93                                         /* 10:word2 */
  94                                         /* 11:word3 */
  95 /*
  96  * HAL2 internal addressing
  97  *
  98  * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
  99  * Indirect Data registers. Write the address to the Indirect Address register
 100  * to transfer the data.
 101  *
 102  * We define the H2IR_* to the read address and H2IW_* to the write address and
 103  * H2I_* to be fields in whatever register is referred to.
 104  *
 105  * When we write to indirect registers which are larger than one word (16 bit)
 106  * we have to fill more than one indirect register before writing. When we read
 107  * back however we have to read several times, each time with different Read
 108  * Back Indexes (there are defs for doing this easily).
 109  */
 110
 111 /*
 112  * Relay Control
 113  */
 114 #define H2IW_RELAY_C            0x9100  /* state of RELAY pin signal */
 115 #define H2IR_RELAY_C            0x9180  /* state of RELAY pin signal */
 116 #define H2I_RELAY_C_STATE       0x01    /* state of RELAY pin signal */
 117
 118 #define H2IW_DMA_PORT_EN        0x09104 /* dma port enable */
 119 #define H2IR_DMA_PORT_EN        0x9184  /* dma port enable */
 120 #define H2I_DMA_PORT_EN_SY_IN   0x01    /*    synth_in dma port */
 121 #define H2I_DMA_PORT_EN_AESRX   0x02    /*    aes receiver dma port */
 122 #define H2I_DMA_PORT_EN_AESTX   0x04    /*    aes transmitter dma port */
 123 #define H2I_DMA_PORT_EN_CODECTX 0x08    /*    codec transmit dma port */
 124 #define H2I_DMA_PORT_EN_CODECR  0x10    /*    codec receive dma port */
 125                                         /* 0=disable 1=enable */
 126
 127 #define H2IW_DMA_END            0x9108  /* global dma endian select */
 128 #define H2IR_DMA_END            0x9188  /* global dma endian select */
 129 #define H2I_DMA_END_SY_IN       0x01    /*    synth_in dma port */
 130 #define H2I_DMA_END_AESRX       0x02    /*    aes receiver dma port */
 131 #define H2I_DMA_END_AESTX       0x04    /*    aes transmitter dma port */
 132 #define H2I_DMA_END_CODECTX     0x08    /*    codec transmit dma port */
 133 #define H2I_DMA_END_CODECR      0x10    /*    codec receive dma port */
 134                                         /* 0=big endian 1=little endian */
 135
 136 #define H2IW_DMA_DRV            0x910C  /* global dma bus drive enable */
 137 #define H2IR_DMA_DRV            0x918C  /* global dma bus drive enable */
 138
 139 #define H2IW_SYNTH_C            0x1104  /* synth dma control write */
 140 #define H2IR_SYNTH_C            0x1184  /* synth dma control read */
 141
 142 #define H2IW_AESRX_C            0x1204  /* aes rx dma control write */
 143 #define H2IR_AESRX_C            0x1284  /* aes rx dma control read */
 144 #define H2I_AESRX_C_TS_EN       0x20    /* timestamp enable 0=no 1=yes */
 145 #define H2I_AESRX_C_TS_FMT      0x40    /* timestamp format */
 146 #define H2I_AESRX_C_NAUDIO      0x80    /* pbus dma data format */
 147                                         /* 0=sign_ext 1=pass_non_audio */
 148
 149 #define H2IW_AESTX_C            0x1304  /* aes tx dma control write */
 150 #define H2IR_AESTX_C            0x1384  /* aes tx dma control read */
 151 #define H2I_AESTX_C_CLKID_M     0x18    /* bits 4:3, clockid */
 152                                         /* 1=Bresenham Clock Gen 1 */
 153                                         /* 2=Bresenham Clock Gen 2 */
 154                                         /* 3=Bresenham Clock Gen 3 */
 155 #define H2I_AESTX_C_DTYPE       0x300   /* bits 9:8, datatype */
 156                                         /* 1=mono 2=stereo 3=quad */
 157
 158 /* DAC */
 159
 160 #define H2IW_DAC_C1             0x1404  /* dac tx dma control 1 write */
 161 #define H2IR_DAC_C1             0x1484  /* dac tx dma control 1 read */
 162 #define H2I_DAC_C1_CLKID        0x18    /* bits 4:3, clockid */
 163                                         /* 1=Bresenham Clock Gen 1 */
 164                                         /* 2=Bresenham Clock Gen 2 */
 165                                         /* 3=Bresenham Clock Gen 3 */
 166 #define H2I_DAC_C1_DTYPE        0x300   /* bits 9:8 datatype */
 167                                         /* 1=mono 2=stereo 3=quad */
 168
 169 #define H2IW_DAC_C2             0x1408  /* dac control 2 write word 0 */
 170 #define H2IR_DAC_C2_0           0x1488  /* dac control 2 read word 0 */
 171 #define H2IR_DAC_C2_1           0x1489  /* dac control 2 read word 1 */
 172                                         /* XXX: The spec says 0x1488 */
 173 #define H2I_DAC_C2_0_R_GAIN     0x0f    /* right a/d input gain bit 0-3 */
 174 #define H2I_DAC_C2_0_L_GAIN     0xf0    /* left a/d input gain bit 0-3 */
 175 #define H2I_DAC_C2_0_R_SEL      0x100   /* right a/d input select */
 176 #define H2I_DAC_C2_0_L_SEL      0x200   /* left a/d input select */
 177 #define H2I_DAC_C2_0_MUTE       0x400   /* 1=mute */
 178 #define H2I_DAC_C2_1_DO1        0x01    /* digital output port bit 1 */
 179 #define H2I_DAC_C2_1_DO2        0x02    /* digital output port bit 0 */
 180 #define H2I_DAC_C2_1_R_ATTEN    0x7c    /* bits 6:2 right a/d output */
 181                                         /* attenuation, bit 0-4 (4=msb) */
 182 #define H2I_DAC_C2_1_L_ATTEN    0xf80   /* bits 11:7 left a/d output */
 183                                         /* attenuation, bit 0-4 (4=msb) */
 184 /* ADC */
 185
 186 #define H2IW_ADC_C1             0x1504  /* adc tx dma control 1 write */
 187 #define H2IR_ADC_C1             0x1584  /* adc tx dma control 1 read */
 188 #define H2I_ADC_C1_CLKID        0x18    /* bits 4:3, clockid */
 189                                         /* 1=Bresenham Clock Gen 1 */
 190                                         /* 2=Bresenham Clock Gen 2 */
 191                                         /* 3=Bresenham Clock Gen 3 */
 192 #define H2I_ADC_C1_DTYPE        0x300   /* bits 9:8, datatype */
 193                                         /* 1=mono 2=stereo 3=quad */
 194
 195 #define H2IW_ADC_C2             0x1508  /* adc control 2 write word 0-1 */
 196                                         /* both words have to be written at */
 197                                         /* the same time, fill idr[0-1] */
 198 #define H2IR_ADC_C2_0           0x1588  /* adc control 2 read word 0 */
 199 #define H2IR_ADC_C2_1           0x1589  /* adc control 2 read word 1 */
 200                                         /* XXX: The spec says 0x1588 */
 201 #define H2I_ADC_C2_0_R_GAIN     0x0f    /* right a/d input gain bit 0-3 */
 202 #define H2I_ADC_C2_0_L_GAIN     0xf0    /* left a/d input gain bit 0-3 */
 203 #define H2I_ADC_C2_0_R_SEL      0x100   /* right a/d input select */
 204 #define H2I_ADC_C2_0_L_SEL      0x200   /* left a/d input select */
 205 #define H2I_ADC_C2_0_MUTE       0x400   /* 1=mute */
 206 #define H2I_ADC_C2_1_DO1        0x01    /* digital output port bit 1 */
 207 #define H2I_ADC_C2_1_DO2        0x02    /* digital output port bit 0 */
 208 #define H2I_ADC_C2_1_R_ATTEN    0x7c    /* bits 6:2, right a/d output */
 209                                         /* attenuation, bit 0-4 (4=msb) */
 210 #define H2I_ADC_C2_1_L_ATTEN    0xf80   /* bits 11:7, left a/d output */
 211                                         /* attenuation, bit 0-4 (4=msb) */
 212
 213 #define H2IW_SYNTH_MAP_C        0x1104  /* synth dma handshake ctrl write */
 214 #define H2IR_SYNTH_MAP_C        0x1184  /* synth dma handshake ctrl read */
 215
 216 #define H2IW_BRES1_C1           0x2104  /* clock gen 1 ctrl 1 write */
 217 #define H2IR_BRES1_C1           0x2184  /* clock gen 1 ctrl 1 read */
 218 #define H2I_BRES1_C1_FSRSEL     0x03    /* master clock source */
 219                                         /* 0=48.0 1=44.1 2=aes_rx */
 220
 221 #define H2IW_BRES1_C2           0x2108  /* clock gen 1 ctrl 2 write word 0-1 */
 222 #define H2IR_BRES1_C2_0         0x2188  /* clock gen 1 ctrl 2 read word 0 */
 223 #define H2IR_BRES1_C2_1         0x2189  /* clock gen 1 ctrl 2 read word 1 */
 224                                         /* XXX: The spec says 0x2188 */
 225 #define H2I_BRES1_C2_0_INC      0xffff  /* increment value, inc <= mod */
 226 #define H2I_BRES1_C2_1_INC      0xffff  /* modcontrol value, */
 227                                         /* modctrl=0x00ffff & (modinc-1) */
 228
 229 #define H2IW_BRES2_C1           0x2204  /* clock gen 2 ctrl 1 write */
 230 #define H2IR_BRES2_C1           0x2284  /* clock gen 2 ctrl 1 read */
 231 #define H2I_BRES2_C1_FSRSEL     0x03    /* master clock source */
 232                                         /* 0=48.0 1=44.1 2=aes_rx */
 233
 234 #define H2IW_BRES2_C2           0x2208  /* clock gen 2 ctrl 2 write word 0-1 */
 235 #define H2IR_BRES2_C2_0         0x2288  /* clock gen 2 ctrl 2 read word 0 */
 236 #define H2IR_BRES2_C2_1         0x2289  /* clock gen 2 ctrl 2 read word 1 */
 237 #define H2I_BRES2_C2_0_INC      0xffff  /* increment value, inc <= mod */
 238 #define H2I_BRES2_C2_1_INC      0xffff  /* modcontrol value, */
 239                                         /* modctrl=0x00ffff & (modinc-1) */
 240
 241 #define H2IW_BRES3_C1           0x2304  /* clock gen 3 ctrl 1 write */
 242 #define H2IR_BRES3_C1           0x2384  /* clock gen 3 ctrl 1 read */
 243 #define H2I_BRES3_C1_FSRSEL     0x03    /* master clock source */
 244                                         /* 0=48.0 1=44.1 2=aes_rx */
 245
 246 #define H2IW_BRES3_C2           0x2308  /* clock gen 3 ctrl 2 write word 0-1 */
 247 #define H2IR_BRES3_C2_0         0x2388  /* clock gen 3 ctrl 2 read word 0 */
 248 #define H2IR_BRES3_C2_1         0x2389  /* clock gen 3 ctrl 2 read word 1 */
 249 #define H2I_BRES3_C2_0_INC      0xffff  /* increment value, inc <= mod */
 250 #define H2I_BRES3_C2_1_INC      0xffff  /* modcontrol value, */
 251                                         /* modctrl=0x00ffff & (modinc-1) */
 252
 253 #define H2IW_UTIME              0x3104  /* unix timer write (preload time) */
 254 #define H2IR_UTIME              0x3184  /* unix timer read */
 255 #define H2I_UTIME_0_LD          0xffff  /* microseconds, LSB's */
 256 #define H2I_UTIME_1_LD0         0x0f    /* microseconds, MSB's */
 257 #define H2I_UTIME_1_LD1         0xf0    /* tenths of microseconds */
 258 #define H2I_UTIME_2_LD          0xffff  /* seconds, LSB's */
 259 #define H2I_UTIME_3_LD          0xffff  /* seconds, MSB's */