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Disable key sockets -- they make no sense without IPsec.
[linux-2.6/linux-mips.git] / arch / arm / mm / alignment.c
blob81f4a8a2d34b2c7af8c93074ca8f0c443fb80bc2
1 /*
2 * linux/arch/arm/mm/alignment.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2001 Russell King
6 * Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc.
7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
8 * Copyright (C) 1996, Cygnus Software Technologies Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14 #include <linux/config.h>
15 #include <linux/compiler.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/ptrace.h>
20 #include <linux/proc_fs.h>
21 #include <linux/init.h>
22
23 #include <asm/uaccess.h>
24 #include <asm/unaligned.h>
25
26 #include "fault.h"
27
28 /*
29 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
30 * /proc/sys/debug/alignment, modified and integrated into
31 * Linux 2.1 by Russell King
32 *
33 * Speed optimisations and better fault handling by Russell King.
34 *
35 * *** NOTE ***
36 * This code is not portable to processors with late data abort handling.
37 */
38 #define CODING_BITS(i) (i & 0x0e000000)
39
40 #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
41 #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
42 #define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
43 #define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
44 #define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
45
46 #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
47
48 #define LDSTH_I_BIT(i) (i & (1 << 22)) /* half-word immed */
49 #define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
50
51 #define RN_BITS(i) ((i >> 16) & 15) /* Rn */
52 #define RD_BITS(i) ((i >> 12) & 15) /* Rd */
53 #define RM_BITS(i) (i & 15) /* Rm */
54
55 #define REGMASK_BITS(i) (i & 0xffff)
56 #define OFFSET_BITS(i) (i & 0x0fff)
57
58 #define IS_SHIFT(i) (i & 0x0ff0)
59 #define SHIFT_BITS(i) ((i >> 7) & 0x1f)
60 #define SHIFT_TYPE(i) (i & 0x60)
61 #define SHIFT_LSL 0x00
62 #define SHIFT_LSR 0x20
63 #define SHIFT_ASR 0x40
64 #define SHIFT_RORRRX 0x60
65
66 static unsigned long ai_user;
67 static unsigned long ai_sys;
68 static unsigned long ai_skipped;
69 static unsigned long ai_half;
70 static unsigned long ai_word;
71 static unsigned long ai_multi;
72 static int ai_usermode;
73
74 #ifdef CONFIG_PROC_FS
75 static const char *usermode_action[] = {
76 "ignored",
77 "warn",
78 "fixup",
79 "fixup+warn",
80 "signal",
81 "signal+warn"
82 };
83
84 static int
85 proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
86 void *data)
87 {
88 char *p = page;
89 int len;
90
91 p += sprintf(p, "User:\t\t%lu\n", ai_user);
92 p += sprintf(p, "System:\t\t%lu\n", ai_sys);
93 p += sprintf(p, "Skipped:\t%lu\n", ai_skipped);
94 p += sprintf(p, "Half:\t\t%lu\n", ai_half);
95 p += sprintf(p, "Word:\t\t%lu\n", ai_word);
96 p += sprintf(p, "Multi:\t\t%lu\n", ai_multi);
97 p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode,
98 usermode_action[ai_usermode]);
99
100 len = (p - page) - off;
101 if (len < 0)
102 len = 0;
103
104 *eof = (len <= count) ? 1 : 0;
105 *start = page + off;
106
107 return len;
108 }
109
110 static int proc_alignment_write(struct file *file, const char __user *buffer,
111 unsigned long count, void *data)
112 {
113 char mode;
114
115 if (count > 0) {
116 if (get_user(mode, buffer))
117 return -EFAULT;
118 if (mode >= '0' && mode <= '5')
119 ai_usermode = mode - '0';
120 }
121 return count;
122 }
123
124 #endif /* CONFIG_PROC_FS */
125
126 union offset_union {
127 unsigned long un;
128 signed long sn;
129 };
130
131 #define TYPE_ERROR 0
132 #define TYPE_FAULT 1
133 #define TYPE_LDST 2
134 #define TYPE_DONE 3
135
136 #ifdef __ARMEB__
137 #define BE 1
138 #define FIRST_BYTE_16 "mov %1, %1, ror #8\n"
139 #define FIRST_BYTE_32 "mov %1, %1, ror #24\n"
140 #define NEXT_BYTE "ror #24"
141 #else
142 #define BE 0
143 #define FIRST_BYTE_16
144 #define FIRST_BYTE_32
145 #define NEXT_BYTE "lsr #8"
146 #endif
147
148 #define __get8_unaligned_check(ins,val,addr,err) \
149 __asm__( \
150 "1: "ins" %1, [%2], #1\n" \
151 "2:\n" \
152 " .section .fixup,\"ax\"\n" \
153 " .align 2\n" \
154 "3: mov %0, #1\n" \
155 " b 2b\n" \
156 " .previous\n" \
157 " .section __ex_table,\"a\"\n" \
158 " .align 3\n" \
159 " .long 1b, 3b\n" \
160 " .previous\n" \
161 : "=r" (err), "=&r" (val), "=r" (addr) \
162 : "0" (err), "2" (addr))
163
164 #define __get16_unaligned_check(ins,val,addr) \
165 do { \
166 unsigned int err = 0, v, a = addr; \
167 __get8_unaligned_check(ins,v,a,err); \
168 val = v << ((BE) ? 8 : 0); \
169 __get8_unaligned_check(ins,v,a,err); \
170 val |= v << ((BE) ? 0 : 8); \
171 if (err) \
172 goto fault; \
173 } while (0)
174
175 #define get16_unaligned_check(val,addr) \
176 __get16_unaligned_check("ldrb",val,addr)
177
178 #define get16t_unaligned_check(val,addr) \
179 __get16_unaligned_check("ldrbt",val,addr)
180
181 #define __get32_unaligned_check(ins,val,addr) \
182 do { \
183 unsigned int err = 0, v, a = addr; \
184 __get8_unaligned_check(ins,v,a,err); \
185 val = v << ((BE) ? 24 : 0); \
186 __get8_unaligned_check(ins,v,a,err); \
187 val |= v << ((BE) ? 16 : 8); \
188 __get8_unaligned_check(ins,v,a,err); \
189 val |= v << ((BE) ? 8 : 16); \
190 __get8_unaligned_check(ins,v,a,err); \
191 val |= v << ((BE) ? 0 : 24); \
192 if (err) \
193 goto fault; \
194 } while (0)
195
196 #define get32_unaligned_check(val,addr) \
197 __get32_unaligned_check("ldrb",val,addr)
198
199 #define get32t_unaligned_check(val,addr) \
200 __get32_unaligned_check("ldrbt",val,addr)
201
202 #define __put16_unaligned_check(ins,val,addr) \
203 do { \
204 unsigned int err = 0, v = val, a = addr; \
205 __asm__( FIRST_BYTE_16 \
206 "1: "ins" %1, [%2], #1\n" \
207 " mov %1, %1, "NEXT_BYTE"\n" \
208 "2: "ins" %1, [%2]\n" \
209 "3:\n" \
210 " .section .fixup,\"ax\"\n" \
211 " .align 2\n" \
212 "4: mov %0, #1\n" \
213 " b 3b\n" \
214 " .previous\n" \
215 " .section __ex_table,\"a\"\n" \
216 " .align 3\n" \
217 " .long 1b, 4b\n" \
218 " .long 2b, 4b\n" \
219 " .previous\n" \
220 : "=r" (err), "=&r" (v), "=&r" (a) \
221 : "0" (err), "1" (v), "2" (a)); \
222 if (err) \
223 goto fault; \
224 } while (0)
225
226 #define put16_unaligned_check(val,addr) \
227 __put16_unaligned_check("strb",val,addr)
228
229 #define put16t_unaligned_check(val,addr) \
230 __put16_unaligned_check("strbt",val,addr)
231
232 #define __put32_unaligned_check(ins,val,addr) \
233 do { \
234 unsigned int err = 0, v = val, a = addr; \
235 __asm__( FIRST_BYTE_32 \
236 "1: "ins" %1, [%2], #1\n" \
237 " mov %1, %1, "NEXT_BYTE"\n" \
238 "2: "ins" %1, [%2], #1\n" \
239 " mov %1, %1, "NEXT_BYTE"\n" \
240 "3: "ins" %1, [%2], #1\n" \
241 " mov %1, %1, "NEXT_BYTE"\n" \
242 "4: "ins" %1, [%2]\n" \
243 "5:\n" \
244 " .section .fixup,\"ax\"\n" \
245 " .align 2\n" \
246 "6: mov %0, #1\n" \
247 " b 5b\n" \
248 " .previous\n" \
249 " .section __ex_table,\"a\"\n" \
250 " .align 3\n" \
251 " .long 1b, 6b\n" \
252 " .long 2b, 6b\n" \
253 " .long 3b, 6b\n" \
254 " .long 4b, 6b\n" \
255 " .previous\n" \
256 : "=r" (err), "=&r" (v), "=&r" (a) \
257 : "0" (err), "1" (v), "2" (a)); \
258 if (err) \
259 goto fault; \
260 } while (0)
261
262 #define put32_unaligned_check(val,addr) \
263 __put32_unaligned_check("strb", val, addr)
264
265 #define put32t_unaligned_check(val,addr) \
266 __put32_unaligned_check("strbt", val, addr)
267
268 static void
269 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
270 {
271 if (!LDST_U_BIT(instr))
272 offset.un = -offset.un;
273
274 if (!LDST_P_BIT(instr))
275 addr += offset.un;
276
277 if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
278 regs->uregs[RN_BITS(instr)] = addr;
279 }
280
281 static int
282 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
283 {
284 unsigned int rd = RD_BITS(instr);
285
286 if ((instr & 0x01f00ff0) == 0x01000090)
287 goto swp;
288
289 if ((instr & 0x90) != 0x90 || (instr & 0x60) == 0)
290 goto bad;
291
292 ai_half += 1;
293
294 if (user_mode(regs))
295 goto user;
296
297 if (LDST_L_BIT(instr)) {
298 unsigned long val;
299 get16_unaligned_check(val, addr);
300
301 /* signed half-word? */
302 if (instr & 0x40)
303 val = (signed long)((signed short) val);
304
305 regs->uregs[rd] = val;
306 } else
307 put16_unaligned_check(regs->uregs[rd], addr);
308
309 return TYPE_LDST;
310
311 user:
312 if (LDST_L_BIT(instr)) {
313 unsigned long val;
314 get16t_unaligned_check(val, addr);
315
316 /* signed half-word? */
317 if (instr & 0x40)
318 val = (signed long)((signed short) val);
319
320 regs->uregs[rd] = val;
321 } else
322 put16t_unaligned_check(regs->uregs[rd], addr);
323
324 return TYPE_LDST;
325
326 swp:
327 printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
328 bad:
329 return TYPE_ERROR;
330
331 fault:
332 return TYPE_FAULT;
333 }
334
335 static int
336 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
337 {
338 unsigned int rd = RD_BITS(instr);
339
340 ai_word += 1;
341
342 if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
343 goto trans;
344
345 if (LDST_L_BIT(instr)) {
346 unsigned int val;
347 get32_unaligned_check(val, addr);
348 regs->uregs[rd] = val;
349 } else
350 put32_unaligned_check(regs->uregs[rd], addr);
351 return TYPE_LDST;
352
353 trans:
354 if (LDST_L_BIT(instr)) {
355 unsigned int val;
356 get32t_unaligned_check(val, addr);
357 regs->uregs[rd] = val;
358 } else
359 put32t_unaligned_check(regs->uregs[rd], addr);
360 return TYPE_LDST;
361
362 fault:
363 return TYPE_FAULT;
364 }
365
366 /*
367 * LDM/STM alignment handler.
368 *
369 * There are 4 variants of this instruction:
370 *
371 * B = rn pointer before instruction, A = rn pointer after instruction
372 * ------ increasing address ----->
373 * | | r0 | r1 | ... | rx | |
374 * PU = 01 B A
375 * PU = 11 B A
376 * PU = 00 A B
377 * PU = 10 A B
378 */
379 static int
380 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
381 {
382 unsigned int rd, rn, correction, nr_regs, regbits;
383 unsigned long eaddr, newaddr;
384
385 if (LDM_S_BIT(instr))
386 goto bad;
387
388 correction = 4; /* processor implementation defined */
389 regs->ARM_pc += correction;
390
391 ai_multi += 1;
392
393 /* count the number of registers in the mask to be transferred */
394 nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
395
396 rn = RN_BITS(instr);
397 newaddr = eaddr = regs->uregs[rn];
398
399 if (!LDST_U_BIT(instr))
400 nr_regs = -nr_regs;
401 newaddr += nr_regs;
402 if (!LDST_U_BIT(instr))
403 eaddr = newaddr;
404
405 if (LDST_P_EQ_U(instr)) /* U = P */
406 eaddr += 4;
407
408 /*
409 * For alignment faults on the ARM922T/ARM920T the MMU makes
410 * the FSR (and hence addr) equal to the updated base address
411 * of the multiple access rather than the restored value.
412 * Switch this message off if we've got a ARM92[02], otherwise
413 * [ls]dm alignment faults are noisy!
414 */
415 #if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T)
416 /*
417 * This is a "hint" - we already have eaddr worked out by the
418 * processor for us.
419 */
420 if (addr != eaddr) {
421 printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
422 "addr = %08lx, eaddr = %08lx\n",
423 instruction_pointer(regs), instr, addr, eaddr);
424 show_regs(regs);
425 }
426 #endif
427
428 if (user_mode(regs)) {
429 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
430 regbits >>= 1, rd += 1)
431 if (regbits & 1) {
432 if (LDST_L_BIT(instr)) {
433 unsigned int val;
434 get32t_unaligned_check(val, eaddr);
435 regs->uregs[rd] = val;
436 } else
437 put32t_unaligned_check(regs->uregs[rd], eaddr);
438 eaddr += 4;
439 }
440 } else {
441 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
442 regbits >>= 1, rd += 1)
443 if (regbits & 1) {
444 if (LDST_L_BIT(instr)) {
445 unsigned int val;
446 get32_unaligned_check(val, eaddr);
447 regs->uregs[rd] = val;
448 } else
449 put32_unaligned_check(regs->uregs[rd], eaddr);
450 eaddr += 4;
451 }
452 }
453
454 if (LDST_W_BIT(instr))
455 regs->uregs[rn] = newaddr;
456 if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
457 regs->ARM_pc -= correction;
458 return TYPE_DONE;
459
460 fault:
461 regs->ARM_pc -= correction;
462 return TYPE_FAULT;
463
464 bad:
465 printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
466 return TYPE_ERROR;
467 }
468
469 /*
470 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
471 * we can reuse ARM userland alignment fault fixups for Thumb.
472 *
473 * This implementation was initially based on the algorithm found in
474 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
475 * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
476 *
477 * NOTES:
478 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
479 * 2. If for some reason we're passed an non-ld/st Thumb instruction to
480 * decode, we return 0xdeadc0de. This should never happen under normal
481 * circumstances but if it does, we've got other problems to deal with
482 * elsewhere and we obviously can't fix those problems here.
483 */
484
485 static unsigned long
486 thumb2arm(u16 tinstr)
487 {
488 u32 L = (tinstr & (1<<11)) >> 11;
489
490 switch ((tinstr & 0xf800) >> 11) {
491 /* 6.5.1 Format 1: */
492 case 0x6000 >> 11: /* 7.1.52 STR(1) */
493 case 0x6800 >> 11: /* 7.1.26 LDR(1) */
494 case 0x7000 >> 11: /* 7.1.55 STRB(1) */
495 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */
496 return 0xe5800000 |
497 ((tinstr & (1<<12)) << (22-12)) | /* fixup */
498 (L<<20) | /* L==1? */
499 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
500 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
501 ((tinstr & (31<<6)) >> /* immed_5 */
502 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
503 case 0x8000 >> 11: /* 7.1.57 STRH(1) */
504 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */
505 return 0xe1c000b0 |
506 (L<<20) | /* L==1? */
507 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
508 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
509 ((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */
510 ((tinstr & (3<<9)) >> (9-8)); /* immed_5[4:3] */
511
512 /* 6.5.1 Format 2: */
513 case 0x5000 >> 11:
514 case 0x5800 >> 11:
515 {
516 static const u32 subset[8] = {
517 0xe7800000, /* 7.1.53 STR(2) */
518 0xe18000b0, /* 7.1.58 STRH(2) */
519 0xe7c00000, /* 7.1.56 STRB(2) */
520 0xe19000d0, /* 7.1.34 LDRSB */
521 0xe7900000, /* 7.1.27 LDR(2) */
522 0xe19000b0, /* 7.1.33 LDRH(2) */
523 0xe7d00000, /* 7.1.31 LDRB(2) */
524 0xe19000f0 /* 7.1.35 LDRSH */
525 };
526 return subset[(tinstr & (7<<9)) >> 9] |
527 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
528 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
529 ((tinstr & (7<<6)) >> (6-0)); /* Rm */
530 }
531
532 /* 6.5.1 Format 3: */
533 case 0x4800 >> 11: /* 7.1.28 LDR(3) */
534 /* NOTE: This case is not technically possible. We're
535 * loading 32-bit memory data via PC relative
536 * addressing mode. So we can and should eliminate
537 * this case. But I'll leave it here for now.
538 */
539 return 0xe59f0000 |
540 ((tinstr & (7<<8)) << (12-8)) | /* Rd */
541 ((tinstr & 255) << (2-0)); /* immed_8 */
542
543 /* 6.5.1 Format 4: */
544 case 0x9000 >> 11: /* 7.1.54 STR(3) */
545 case 0x9800 >> 11: /* 7.1.29 LDR(4) */
546 return 0xe58d0000 |
547 (L<<20) | /* L==1? */
548 ((tinstr & (7<<8)) << (12-8)) | /* Rd */
549 ((tinstr & 255) << 2); /* immed_8 */
550
551 /* 6.6.1 Format 1: */
552 case 0xc000 >> 11: /* 7.1.51 STMIA */
553 case 0xc800 >> 11: /* 7.1.25 LDMIA */
554 {
555 u32 Rn = (tinstr & (7<<8)) >> 8;
556 u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
557
558 return 0xe8800000 | W | (L<<20) | (Rn<<16) |
559 (tinstr&255);
560 }
561
562 /* 6.6.1 Format 2: */
563 case 0xb000 >> 11: /* 7.1.48 PUSH */
564 case 0xb800 >> 11: /* 7.1.47 POP */
565 if ((tinstr & (3 << 9)) == 0x0400) {
566 static const u32 subset[4] = {
567 0xe92d0000, /* STMDB sp!,{registers} */
568 0xe92d4000, /* STMDB sp!,{registers,lr} */
569 0xe8bd0000, /* LDMIA sp!,{registers} */
570 0xe8bd8000 /* LDMIA sp!,{registers,pc} */
571 };
572 return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
573 (tinstr & 255); /* register_list */
574 }
575 /* Else fall through for illegal instruction case */
576
577 default:
578 return 0xdeadc0de;
579 }
580 }
581
582 static int
583 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
584 {
585 union offset_union offset;
586 unsigned long instr = 0, instrptr;
587 int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
588 unsigned int type;
589 mm_segment_t fs;
590 unsigned int fault;
591 u16 tinstr = 0;
592
593 instrptr = instruction_pointer(regs);
594
595 fs = get_fs();
596 set_fs(KERNEL_DS);
597 if thumb_mode(regs) {
598 fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
599 if (!(fault))
600 instr = thumb2arm(tinstr);
601 } else
602 fault = __get_user(instr, (u32 *)instrptr);
603 set_fs(fs);
604
605 if (fault) {
606 type = TYPE_FAULT;
607 goto bad_or_fault;
608 }
609
610 if (user_mode(regs))
611 goto user;
612
613 ai_sys += 1;
614
615 fixup:
616
617 regs->ARM_pc += thumb_mode(regs) ? 2 : 4;
618
619 switch (CODING_BITS(instr)) {
620 case 0x00000000: /* ldrh or strh */
621 if (LDSTH_I_BIT(instr))
622 offset.un = (instr & 0xf00) >> 4 | (instr & 15);
623 else
624 offset.un = regs->uregs[RM_BITS(instr)];
625 handler = do_alignment_ldrhstrh;
626 break;
627
628 case 0x04000000: /* ldr or str immediate */
629 offset.un = OFFSET_BITS(instr);
630 handler = do_alignment_ldrstr;
631 break;
632
633 case 0x06000000: /* ldr or str register */
634 offset.un = regs->uregs[RM_BITS(instr)];
635
636 if (IS_SHIFT(instr)) {
637 unsigned int shiftval = SHIFT_BITS(instr);
638
639 switch(SHIFT_TYPE(instr)) {
640 case SHIFT_LSL:
641 offset.un <<= shiftval;
642 break;
643
644 case SHIFT_LSR:
645 offset.un >>= shiftval;
646 break;
647
648 case SHIFT_ASR:
649 offset.sn >>= shiftval;
650 break;
651
652 case SHIFT_RORRRX:
653 if (shiftval == 0) {
654 offset.un >>= 1;
655 if (regs->ARM_cpsr & PSR_C_BIT)
656 offset.un |= 1 << 31;
657 } else
658 offset.un = offset.un >> shiftval |
659 offset.un << (32 - shiftval);
660 break;
661 }
662 }
663 handler = do_alignment_ldrstr;
664 break;
665
666 case 0x08000000: /* ldm or stm */
667 handler = do_alignment_ldmstm;
668 break;
669
670 default:
671 goto bad;
672 }
673
674 type = handler(addr, instr, regs);
675
676 if (type == TYPE_ERROR || type == TYPE_FAULT)
677 goto bad_or_fault;
678
679 if (type == TYPE_LDST)
680 do_alignment_finish_ldst(addr, instr, regs, offset);
681
682 return 0;
683
684 bad_or_fault:
685 if (type == TYPE_ERROR)
686 goto bad;
687 regs->ARM_pc -= thumb_mode(regs) ? 2 : 4;
688 /*
689 * We got a fault - fix it up, or die.
690 */
691 do_bad_area(current, current->mm, addr, fsr, regs);
692 return 0;
693
694 bad:
695 /*
696 * Oops, we didn't handle the instruction.
697 */
698 printk(KERN_ERR "Alignment trap: not handling instruction "
699 "%0*lx at [<%08lx>]\n",
700 thumb_mode(regs) ? 4 : 8,
701 thumb_mode(regs) ? tinstr : instr, instrptr);
702 ai_skipped += 1;
703 return 1;
704
705 user:
706 ai_user += 1;
707
708 if (ai_usermode & 1)
709 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
710 "Address=0x%08lx FSR 0x%03x\n", current->comm,
711 current->pid, instrptr,
712 thumb_mode(regs) ? 4 : 8,
713 thumb_mode(regs) ? tinstr : instr,
714 addr, fsr);
715
716 if (ai_usermode & 2)
717 goto fixup;
718
719 if (ai_usermode & 4)
720 force_sig(SIGBUS, current);
721 else
722 set_cr(cr_no_alignment);
723
724 return 0;
725 }
726
727 /*
728 * This needs to be done after sysctl_init, otherwise sys/ will be
729 * overwritten. Actually, this shouldn't be in sys/ at all since
730 * it isn't a sysctl, and it doesn't contain sysctl information.
731 * We now locate it in /proc/cpu/alignment instead.
732 */
733 static int __init alignment_init(void)
734 {
735 #ifdef CONFIG_PROC_FS
736 struct proc_dir_entry *res;
737
738 res = proc_mkdir("cpu", NULL);
739 if (!res)
740 return -ENOMEM;
741
742 res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res);
743 if (!res)
744 return -ENOMEM;
745
746 res->read_proc = proc_alignment_read;
747 res->write_proc = proc_alignment_write;
748 #endif
749
750 hook_fault_code(1, do_alignment, SIGILL, "alignment exception");
751 hook_fault_code(3, do_alignment, SIGILL, "alignment exception");
752
753 return 0;
754 }
755
756 fs_initcall(alignment_init);
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